an1725

Application Note 1725
Authors: Gary Hendrickson and Michael Steffes
Ultra Low Power Broadband 8 to 14-Bit Data
Acquisition Platform
ISLA112P50/55210EV1Z High
Speed ADC/AMP Evaluation
Board
Evaluation Platform Overview
• ISLA112P50 High Speed, Low Power ADC [12Bits,500MSPS]
• ISL55210 High Performance, Low Power, Differential Amplifier
• Compatible with Existing Intersil High-Speed ADC Evaluation
Platform
• Optional Measurement Port to ADC Inputs
• Pin Compatible Family of 8- to 14-bit ADCs can be used.
Performance
• Clock Rate Range: 200MSPS to 500MSPS
• 200mVP-P Input (-10dBm) for -1dBFS ADC Input
• ±0.5dB flat response: 100kHz to 100MHz
The ISLA112P50/55210EV1Z is an evaluation platform
featuring Intersil’s high-speed FDA (Fully Differential Amplifier)
(ISL55210) and High Speed, Low Power 12-bit, 500Msps ADC
(ISLA112P50). The PCB is compatible with Intersil’s existing high
speed ADC evaluation platform allowing for easy performance
measurement and analysis. (See Intersil’s Application Notes
AN1433, AN1434 for more information). The ADC evaluation
platform consists of custom designed hardware and software.
The function of the hardware is to provide power to the ADC and
to excite and/or measure the appropriate analog and digital
inputs and outputs. The software is required to configure the
device for initial operation, to modify the device functionality or
parameters, and to process and display the output data.
Konverter software version 1.22c (or later) supports the
ISLA11XP50 family and the ISLA112P50/55210EV1Z PCB.
CONTACT THE FACTORY FOR ASSISTANCE IN USING THE
KONVERTER SOFTWARE TO MODIFY THIS BOARD TO A
DIFFERENT ADC.
• Typical SNR: 65dBFS
• Typical SFDR: 82dBC @ -1dBFS Input [10MHz to 100MHz
Analog Input]
Operating Precautions
System Requirements
IT IS STRONGLY RECOMMENDED TO INSERT THE +5V PLUG AT
THE MOTHERBOARD PRIOR TO PLUGGING IN THE AC ADAPTER
TO REDUCE THE POSSIBILITY OF POWER SURGES WHICH CAN
DAMAGE THE PCB. PROBING ON THE PCB SHOULD BE DONE
WITH CARE USING PROPER ESD TECHNIQUES WHILE HANDLING.
• ISLA112P50/55210EV1Z Evaluation Board
• KMB-001LEVALZ Intersil Motherboard (5V Supply Provided
with Motherboard)
• Intersil Konverter Software
http://www.intersil.com/converters/adc_eval_platform/
• Low Jitter Clock Source
• Bandpass Filter(s)
USB
To Host PC
Mezzanine
Connector
REF
IN
Analog Input
Low-Jitter
RF Generator
Test
Bandpass
Filter
Daughter
Card
SRAM
Optional
Attenuator
AMP
10MHz
Reference
Motherboard
KMB001
+5V
USB
ADC
FPGA
Analog Input
Low-Jitter
RF Generator
REF
OUT
Clock
(200-500MHz)
SRAM
Optional
Measurement
Port
Clock Inputs
FIGURE 1. TYPICAL CHARACTERIZATION SETUP
March 8, 2012
AN1725.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Application Note 1725
Hardware
Motherboard
There are two components in the hardware portion of the
evaluation platform: the daughter card and the motherboard
(Figure 1). The FDA and ADC are contained on the daughter card,
which routes power from the motherboard and contains the
analog input circuitry, clock drive and decoupling. The daughter
card interfaces to the motherboard through a mezzanine
connector. The motherboard contains a USB interface, an FPGA
and SRAM. The motherboard serves as the interface between the
host PC and the ADC daughter card. Most of the ADC
functionality is controlled through the motherboard by the
Konverter software. The FPGA accepts output data from the ADC
and buffers it in the SRAMs before passing it to the PC at a lower
speed for post-processing. The maximum buffer depth is
approximately one million words.
The only connections required for the motherboard are +5V
power and a USB connection to the PC running Konverter
Analyzer. No additional configuration of the motherboard is
required. IT IS STRONGLY RECOMMENDED TO INSERT THE +5V
PLUG AT THE MOTHERBOARD PRIOR TO PLUGGING IN THE AC
ADAPTER TO REDUCE THE POSSIBILITY OF POWER SURGES,
WHICH CAN DAMAGE THE PCB. PROBING ON THE PCB SHOULD
BE DONE WITH CARE USING PROPER ESD TECHNIQUES WHILE
HANDLING.
The user must supply a low-jitter RF generator for the clock input
to achieve the SNR shown here. Recommendations of suitable
generators can be found in “Appendix A: RF Generators” on
page 13. Note, a low cost, low jitter 500MHz clock source also is
available from Crystek - the RFPRO33-500.
Many low-jitter RF generators exhibit high harmonic spectral content
relative to the ADC performance. A band-pass filter is recommended
to attenuate the harmonics when testing the analog path.
Software
The software component is a Konverter Analyzer, a graphical
user interface (GUI) created with MATLAB™. A MATLAB
Component Runtime engine is supplied, which executes a
compiled version of the m-files. Therefore, a stand-alone version
of MATLAB is not required to run the Konverter Analyzer.
The GUI controls the ADC configuration through the SPI port,
reads data from the motherboard and performs post-processing
and display of the output data. Data can be viewed in the time or
frequency domain, and can be saved for later processing. Critical
performance parameters such as SNR, SFDR, harmonic
distortion, etc. are calculated and displayed on-screen when
viewing in the frequency domain. Different regions of the FFT
output may be easily viewed by zooming in using the settings
available in the Konverter software.
Initial Start-Up
Referring to Figure 1, connect the daughter card to the
motherboard by aligning the two matching mezzanine
connectors. Four screws on the motherboard (not shown) align
with mounting holes in the daughter card. Next, connect the
clock source (~10dBm) which is required for communication to
the Konverter software, then connect a test source or signal of
interest coming from your signal channel at a maximum VP-P <
200mV (-10dBm). With the RF generators on, apply +5V power
(minimum 5W supply) to the motherboard. The daughter card is
powered by linear regulators on the motherboard. A USB cable
should then be connected after +5V power has been applied.
(Use the same USB port that was used when Konverter was
initially installed so the hardware is recognized).
2
Software Start-Up
The FPGA clock is derived from the ADC output clock, and the
FPGA clock must be active for the software to run properly.
Therefore, it’s important that the evaluation platform is powered
and receiving a conversion clock prior to initializing the Konverter
Analyzer Software.
The compressed MATLAB files are unpacked the first time the
GUI is invoked after installation. Subsequently, the graphical
window will open more quickly. Complete information can be
found in the KMB-001 Installer manual.
http://www.intersil.com/converters/adc_eval_platform/
The main Konverter Analyzer window is shown in Figure 4. The
application opens in FFT mode by default, but other modes can
be selected using the radio buttons in the lower left corner. In
each mode, relevant parameters are displayed in the data box on
the left side of the window.
The following parameters are displayed in the data box in all
operating modes:
• Fsamp: Sample clock frequency, automatically detected
• Ffund: Input frequency, automatically detected (assumes sine
wave single tone input)
• Fund: Input amplitude (in dBFS)
• Samples: Record length
• Power: Total ADC power dissipation (FDA Power is in addition
to this), as well as the voltage and current of each ADC supply
Data Acquisition
Press the Run button in the lower left corner of the screen to
produce a single FFT plot. The Continuous check box can be
selected to capture and display successive FFT plots. Multiple
acquisitions can be averaged by selecting the Average check box.
The number of averaged acquisitions defaults to 10, but can be
changed in the Setup Conditions dialog. The FFT window also
allows for tuning the number of frequency bins used in the FFT
calculations.
Menu items and the toolbar buttons may not function properly if
data is being captured in Continuous mode. Stop the acquisition
before selecting a menu item or using a toolbar button.
AN1725.0
March 8, 2012
Application Note 1725
Menus
AN1433 should be consulted for more information on the File,
Setup, and Help software menus. AN1434 has information on
software installation if needed.
FIGURE 5. KONVERTER MENUS
FIGURE 2. ISLA112P50/55210 DAUGHTERBOARD
Analog Signal Path Description
.
The amplifier implementation on this daughterboard is intended
to:
1. Terminate a single-ended input source with an AC-coupled
broadband 50Ω impedance.
2. Convert the single-ended source to differential inputs for the
ADC.
3. Provide extremely low noise and distortion amplification from
a nominal -10dBm (200mVP-P single tone) input to a
differential VP-P at the ADC inputs of approximately 1.3VP-P.
This 6.45V/V gain (16.2dB) gain is a combination of input
transformer step up, amplifier gain, and interstage filter
insertion loss.
FIGURE 3. DAUGHTERBOARD WITH KMB MOTHERBOARD
4. The interstage filter between the amplifier’s differential
outputs and the ADC, also level shifts the Vcm output voltage
from the amplifier to a lower Vcm voltage required by the
ADC.
ISLA112P50 (SN−000011)
30−Jan−2012 15:14:38, 25C
0
−20
The signal path circuit can be broken into an input side operation
and then an output interstage filter.
−40
dBfs
Fsamp: 500 MHz
Ffund: 70.12 MHz
Fund: −1.12 dBFS
SNRFS: 64.9 dBFS
SNR:
63.8 dBc
SFDR: 84 dBc +
SINAD: 63.7 dBc
THD: −82.2 dBc
HD2: −88 dBc
HD3: −84 dBc
HD4: −95 dBc
HD5: −98 dBc
HD6: −100 dBc
HD7: −98 dBc
FIS
−112 dBc
OS
−87 dBc
ENOB:
10.3
ENOBFS: 10.5
Samples: 200000
Window: BH4T
Power: 553 mW
Ovdd 1.80V @ 123 mA
Vdd2 1.80V @ 183 mA
Figure 6 shows the input circuit for this daughterboard. Elements
in green are optional and not populated for the nominal design
board as delivered.
−60
−80
+3
2
7
−100
6
10
9
8
OS
4
5
FIS
−120
0
50
100
150
Frequency (MHz)
200
250
FIGURE 4. FFT OUTPUT WITH 70MHZ ANALOG INPUT
Figure 4 shows a typical FFT for the PCB with a 70MHz Analog
Input with the drive level adjusted to ~ -9.4dBm at the card edge
resulting in a -1dBFS signal for the ADC. The ISLA112P50 is a
low power 500Msps 12-bit ADC, more detailed information on
the ADC can be found in the datasheet
(http://www.intersil.com/data/fn/fn7604.pdf)
FIGURE 6. POWER SUPPLY DECOUPLING AND INPUT SIDE
TRANSFORMER/FILTER BEFORE ADC
3
AN1725.0
March 8, 2012
Application Note 1725
The input is AC-coupled through a 4.7μF blocking cap into the
primary side of a 1:2 turns ratio step-up transformer; a
Minicircuits ADT4-6T device. The blocking cap protects the
source from accidental DC shorts while adding a 1.4kHz highpass pole (if the source is 50Ω). The 2nd transformer (ADTL1-475) acts as a common mode choke improving the differential
balance for the amplifier stage. Ignoring it for a moment, the two
100Ω resistors (R1006 and R1007) act as both the gain resistors
for the ISL55210 Fully Differential Amplifier (FDA) and the input
termination elements. They drive into the differential summing
junction of the FDA, which will appear as a broadband virtual
ground for the differential signal. Since the input transformer is a
1:4 ohms ratio step up, those two 100Ω elements will add
together to look like a 200Ω termination. They input refer
through the transformer to appear as a 50Ω termination to the
source. Detailed specifications on the 4GHz, 0.85nV/√Hz input
noise ISL55210 may be found at –
http://www.intersil.com/data/fn/fn7811.pdf
Frequency Response Flatness Issues
Each of the elements in the signal path have fine scale rolloffs
that need to be considered to achieve the final ±0.5dB flatness
through the 100kHz to 100MHz range.
The ADT4-6T input transformer was selected mainly for its low
frequency performance. While specified as -1dB flat from
150kHz to 200MHz, it actually does better than this in lab tests.
Figure 7 shows the measured S21 response for several of the
transformer options (for 1:2 turns ratio) possible on this board.
Here, the ADT4-6T is clearly very flat down to 100kHz while
hitting about -1dB at its specified 200MHz on this 2dB/div plot.
These measurements included a resistor output network that
looks like 200Ω to the transformer but 50Ω to the network
analyzer – giving an insertion loss to the measurement but more
accurately measuring the S21 flatness.
The purely differential signal at the output side of 2nd
transformer then gets through to the amplifier differential output
gained up by the two 412Ω feedback resistors. A complete
description of the noise, loop gain, and signal path balance of
this implementation may be found in this series of 4 articles.
• Part 1. Advantages to transformer input in a single to
differential AC-coupled application.
http://www.eetimes.com/design/analogdesign/4215415/Deliver-the-lowest-distortion-and-noise-in-alow-power--wideband--ADC-interface--Part-1-of-4• Part 2. Calculating integrated noise at the ADC for different
filters and input pin SNR with the ADC for a net result.
http://www.eetimes.com/design/analogdesign/4215416/Deliver-the-lowest-distortion-and-noise-in-alow-power--wideband--ADC-interface--Part-2-of-4• Part3. Distortion issues and combining SFDR at input pins
with ADC for a net result.
http://www.eetimes.com/design/analogdesign/4215417/Deliver-the-lowest-distortion-and-noise-in-alow-power--wideband--ADC-interface--Part-3-of-4• Part 4. Summary amplifier + ADC data on the Rev. A
daughterboard and transformer modeling.
http://www.eetimes.com/design/analogdesign/4215418/Deliver-the-lowest-distortion-and-noise-in-alow-power--wideband--ADC-interface--Part-4-of-4?Ecosystem=analog-design
This article series was not including the 2nd common mode
choke transformer (T2). Significant HD2 improvement at higher
frequencies was found in adding this to the design. Thus, going
from the Rev. A board described in the article series to the Rev. C
final implementation, added that component. One of the options
on this board is to eliminate that transformer and short across its
pins with 0Ω resistors.
4
FIGURE 7. OPTIONAL INPUT 1:2 TURNS RATIO TRANSFORMERS
MEASURED IN 50Ω SYSTEM
The ADT4-6T is a good match to this 100kHz to 100MHz design.
To modify this board to higher frequencies, the Macom
MABA0096-CF48A0 seems to give a little better flatness range
vs the ADT4-1WT from Mini-circuits. The Macom device
measures very flat over a 1MHz to 200MHz range.
The 2nd common mode choke transformer (ADTL-4-75, T2 in
Figure 6) is extremely broadband, showing < 0.25dB insertion
loss from DC to 100MHz. While not specified by MiniCircuits,
since these elements are in fact a DC short, the loss below the
minimum specified frequency of 500kHz actually decreases. For
higher frequency designs, the pin compatible ADTL1-12 holds
lower insertion loss through 200MHz.
The amplifier will have its own frequency response from these
source impedances and gain settings. One of the subtle
advantages of this configuration is that the signal gain is higher
than the amplifier noise gain. In the default circuit, the amplifier
is operating at a signal gain from the output of the transformer
that is simply the ratio of the feedback to gain setting resistors
(4.12V/V here). However, looking at the noise gain for this
Voltage Feedback Amplifier (VFA) implementation will also see
the source element coming through the transformers as another
100Ω element on each side if the source signal is coming from a
50Ω impedance. Thus, the amplifier believes it is in a 1+
412/200 = 3.06V/V noise gain while delivering a signal gain of
AN1725.0
March 8, 2012
Application Note 1725
4.12V/V. These issues are described and explored in detail in the
ISL55210 EVM board users guide available at http://www.intersil.com/data/an/an1649.pdf
From that, a series of bandwidth vs Rf value curves were taken.
These are using a different input transformer, ADT2-1T, that has
a bit broader response on the high end. Stepping Rf is stepping
the gain, with fixed 50Ω Rg resistors, which provide the match
for the 1:2 ohms ratio input transformer used for this data. The
Rf = 300Ω curve (between the 200Ω and 400Ω curves in
Figure 8) is the same noise gain as that described on the ADC
daughterboard where we see a very flat response through
100MHz.
Amplifier to ADC Interstage Circuit and Vcm
Issues
Figure 9 shows the signal path from the amplifier outputs to the
ADC inputs.
1
NORMALIZED GAIN (dB)
0
Rf = 200Ω
-1
-2
Rf = 800Ω
-3
-4
Rf = 400Ω
Rf = 600Ω
-5
-6
-7
-8
-9
1.E+06
1.E+07
1.E+08
1.E+09
FREQUENCY (Hz)
FIGURE 8. MEASURED AMPLIFIER FREQUENCY RESPONSE vs GAIN
SETTING (1VP-P OUTPUT)
Increasing the amplifier gain does of course start to rolloff the
frequency response as you move higher for the VFA design. The
two input node capacitors in Figure 6 on page 3 (green, not
populated 2.2pF), can be used as a fine tune on the output rolloff
to the amplifier output pins. They were not used here as the
response using the ADT4-6T and this relatively low gain setting
on the ISL55210 did not require any equalization. This technique
should be used with caution as it is also peaking up the output
spot noise, which can quickly degrade the overall SNR for the
solution. The ISL55210 Device information page includes a Spice
Model that can be used to test these issues.
http://www.intersil.com/products/deviceinfo.asp?pn=ISL55210
Power Supply Decoupling Issues
The Daughterboard schematic of Figure 6 shows one example of
good power supply decoupling for this single 3.3V supply device.
Where possible, a large valued capacitor isolated towards this
4GHz amplifier with a high frequency ferrite and then another
1μF element provides a Pi filter on the board. Right at the device
pins, the daughterboard uses two X2Y capacitors on each side of
the package to get the best high frequency decoupling. Standard
0.01μF can also be used, which may reduce the HD2
performance at higher frequencies.
FIGURE 9. INTERSTAGE CONNECTIONS FROM THE AMPLIFIER TO
THE ADC
The basic signal path is from the two amplifier output pins on the
left through the differential RLC filter to the two ADC input pins
on the right (Vinp and Vinm). The circuit here looks a little more
involved than an actual end equipment implementation as it
includes some optional features.
The ISL55210 includes an internally regulated 1.2V common
mode voltage generator. The circuit implemented here uses that
and no connection to the external Vcm adjustment pin on the
ISL55210 is required. These are the resistor and pot elements at
the top of Figure 9. If a very high insertion loss filter needs to be
tested on this board, where the required VP-P at the amplifier
outputs exceeds 3VP-P, moving the default amplifier Vcm up will
give more output swing range. This can be done by populating
the optional amplifier Vcm adjustment elements (R1001 and
R1005).
On the lower part of Figure 9 is a logic gate to drive the disable
line on the ISL55210. With the 50Ω termination tied to ground
with no input signal, this 74AHC1G04 single inverter holds the
amplifier enable line high (keeping it turned on) but it can
certainly be connected to control signal input to test this feature.
Interstage Filter Design and Vcm Bias
Figure 10 shows an iSim PE simulation circuit for the filter and
Vcm bias circuit implemented on the board as shown in Figure 9.
This is a free Spice and Power simulator available in the Intersil
web site at
http://web.transim.com/intersil/iSimPE.aspx
5
AN1725.0
March 8, 2012
Application Note 1725
ISL55210 + ISLA112P50 daughterboard
Interstage filter design and Vcm bias
47n
5%
1%
R7
20k
C4
L1
AC 1
V1
29.4
1%
1%
R8
20k
4.7u
10%
47n
5%
R4
C2
L2
1%
R6
216
1%
R5
216
-5
0.0013
I2
1%
C1
10p
20%
C8
1.9p
-10
20%
R2
500
0.0013
I1
578.655m
dBV(I2-pos - I1-pos) / dB
4.7u
10%
29.4
1%
R1
578.655m
ISLA112P50 Input
characteristic at 500MSPS
-15
-20
ISLA112P50 Vcm model
-25
422
1%
3.3
V2
107
1%
R3
R11
859.455m
20
1%
1%
R10
130
R9
0.535
V3
-30
10k
20k
50k
100k
200k
500k
1M
2M
5M
10M
20M
50M
100M
200M
500M
1G
Frequency / Hertz
FIGURE 10. SIMULATION MODEL FOR THE INTERSTAGE FILTER AND
VCM SETUP
The numbering does not follow Figure 9, but this is the same
circuit with the ADC input and Vcm terms added. The amplifier
output shows up as AC1 and the R7 and R8 elements are
simulation artifacts to get DC operation points set. Aside from
simply implementing a 2nd order differential RLC filter, this
circuit also provides the bias voltage for the ADC input Vcm pins.
The ISLA112P50 has a clock rate dependent common input
current (shown in Figure 10 as two 1.3mA current sources). The
network on the lower part of Figure 10 generates a DC bias
voltage as a Thevenin equivalent from the converter’s Vcm
output pin (modeled above as a 0.535V and 20Ω internal
element) and the +3.3V supply. This voltage ends up being
greater than the required voltage at the ADC inputs and it is
pulled down through the two 216Ω resistors that are part of the
filter design to be in range for the ADC. It is important to
recognize that the filter design must be including the differential
input impedance of the ADC – shown in Figure 10 as 500Ω in
parallel with 1.9pF.
Running the simulation with the DC probes included, shows this
circuit provides a Vcm at the ADC of approximately 0.578V for
this 500MSPS Icm. Remember the actual amplifier outputs are
sitting at approx. 1.2Vcm and that is being level shifted to this
ADC voltage through the two 4.7μF blocking caps. Figure 11
shows the simulated response for this design.
FIGURE 11. SIMULATED DIFFERENTIAL FILTER RESPONSE
The key information in this response is the midband insertion
loss of only 2dB and the moderate peaking in the nominal
response. It is very desirable to limit the insertion loss as this will
reduce the maximum amplifier output VP-P to reach -1dBFS at
the ADC. For instance, here we need 1.3VP-P at the ADC to be
delivering a -1dBFS signal, which moves back through this filter
to be a (10(2/20))*1.3V = 1.63VP-P at the amplifier outputs. This
simulated response is peaking approximately 1.5dB but in the
actual board, there are parasitic C’s in the interstage path that
rolls this off to be perfectly flat.
Measurement Port Option
The Vcm bias setup resistors in the simulation circuit (216Ω) are
actually implemented on the board as a passive sense path for
the signal response right up to the ADC input pins. Going back to
Figure 9 on page 5, those resistors are split into 4 elements that
show the correct differential impedance for the filter, but divide
down the differential signal at the ADC inputs while presenting
two 25Ω source impedance elements into a very broadband 1:1
transformer (ADT1-1WT), where it is converted back to
single-ended and delivered to a measurement port on the board.
Using this technique, a direct network analyzer measurement of
the response to the ADC inputs can be made. End equipment
implementations would not use this feature and the sense path
transformer can be eliminated from the design. However, this
provides a relatively quick and easy way to measure the
frequency response to the ADC inputs. Figure 12 shows a typical
small signal measurement with the ADC clocking at 500MSPS,
while Figure 13 shows the same thing running the ADC at
200MSPS. Note that the board as shipped does not have the
measurement path populated; to install it add 0.1µF input
capacitors C1017, C1018, the transformer and the transformer
output DC blocking capacitor C1019, as shown in the schematic
at Figure 39.
Nearly identical results occur at the minimum clock rate of
200MSPS.
6
AN1725.0
March 8, 2012
Application Note 1725
2. -0.3dB midband insertion loss for the ADT4-6T
3. -0.25dB Insertion Loss for the ADT1-4-75
4. +12.3dB amplifier gain from the transformer outputs to the
amplifier outputs
5. -2dB interstage filter insertion loss, which comes to 15.75dB
nominal gain – very close to the measured 16.0dB result.
Figures 14 and 15 show typical AC performance for the ADC
alone as a function of analog input frequency. These figures are
from the ISLA112P50 datasheet.
90
SNR (dBFS) AND SFDR (dBc)
FIGURE 12. AMPLIFIER FREQUENCY RESPONSE AT 500MSPS
85
80
75
SFDR
70
65
60
SNR
55
50
45
40
0M
200M
400M
600M
800M
1G
INPUT FREQUENCY (Hz)
FIGURE 14. SNR and SFDR vs ANALOG INPUT FREQUENCY AT
500MSPS (ADC ONLY)
HARMONIC MAGNITUDE (dBc)
-40
-50
HD3
-60
HD2
-70
-80
-90
-100
0M
200M
400M
600M
800M
1G
INPUT FREQUENCY (Hz)
FIGURE 13. AMPLIFIER FREQUENCY RESPONSE AT 200MSPS
The markers show very small deviation from 1MHz gain through
this 100MHz span. These measured responses are from the
board input SMA to the sense port output SMA.
While not shown in Figures 12 & 13, the response going down to
100kHz remains flat to within 0.5dB to the 1MHz gain. The total
insertion loss in the 4 resistor network, including two 50Ω
impedance reflected through from the output pin load, is
approximately 23.5dB for the resistor divider and then another
0.5dB insertion loss for the ADT1-1WT transformer. Adding this
24dB insertion loss to the -8.0dB 1MHz number measured
above, gives a nominal gain from the input of the board to the
ADC inputs of 16.0dB. Going from the input SMA to the ADC
inputs, we should be seeing:
1. +6dB for the input ADT4-6T
7
FIGURE 15. H2 and H3 vs ANALOG INPUT FREQUENCY AT 500MSPS
(ADC ONLY)
The SNR curves are always referenced to full scale. Thus, if an
SNR is developed at -1dBFS, the resulting number is increased by
1dB to project the SNR if the exact full scale input swing was
being delivered.
Generally, up through 100MHz, the ISLA112P50 typical data
shows:
1. SNR of about 65.5dBFS
2. HD2 of about -90dBc
3. HD3 of about -86dBc
These are remarkable numbers for an ADC consuming < 500mW
at this maximum 500MSPS clock rate.
AN1725.0
March 8, 2012
Application Note 1725
Amplifier/ADC PCB AC Performance
The frequency response achieved here has exceptional flatness
over this 100kHz to 100MHz range and then rolls off with a bit
more than a 2nd order rolloff above that. This filtering is very
important to:
Very little degradation in ADC SNR is observed here. This is the
combined result of very low output spot noise from this low input
noise (0.85nV/√Hz) wideband FDA and good noise power
bandwidth control in the interstage filter.
-75
1. Control the integrated noise power bandwidth for the noise
out of the amplifier stage.
-80
-85
(dBc)
2. Help attenuate the HD terms present at the amplifier outputs.
For instance, the filter shows about 10dB attenuation at
200MHz. This will be knocking down the amplifier HD2 by
10dB for a 100MHz input signal while the HD3 will be getting
>10dB attenuation for frequencies above 67MHz.
-90
The board supports a 3rd order filter design as well with the C16
element shown in Figure 9. The measurement port path provides
an easy way to build and test alternate interstage filter designs.
Contact the factory for assistance in redesigning this filter.
Tested SNR and SFDR at 500MSPS
The goal for this analog signal path before the ADC is to greatly
reduce the required input signal level while suffering minimal
degradation from lab tested ADC performance and provide a very
broadband solution from 100kHz to 100MHz inputs. The
ISLA112P50 shows an SNR over frequency (and these are
always -1dBFS single tone test curves) in Figure 14 and HD2 and
HD3 curves in Figure 15. These are normally taken with a 2
transformer input circuit using the ADTL1-12. Thus, the signal
source is driving a very high amplitude single-ended test signal
but is heavily filtered by narrow bandpass filters for each data
point in Figure 15. The performance numbers shown are
implicitly very narrowband due to the bandpass filter used in ADC
characterization.
Figures 16 through 18 show tested SNRFS, HD2 and HD3 for 3
example amplifier + ADC daughterboards tested at 500MSPS.
BOARD #3
BOARD #2
-95
-100
10
30
110
-75
BOARD #1
-80
-85
BOARD #3
-90
-95
BOARD #2
65.1
10
30
50
70
90
ANALOG FREQUENCY (MHz)
110
FIGURE 18. TESTED HD3 FOR 3 BOARDS AT -10dBm BOARD EDGE
SINGLE TONE POWER
64.9
(dBFS)
90
Quite a bit of variability in the measured HD2 is seen in Fig. 17
and should be expected due to the cancellation nature of HD2.
However in any case, all 3 boards over 10MHz to 100MHz hold
lower than the -80dBc combined performance. This is
exceptional performance for a 115mW signal path solution.
-100
65.3
BOARD #2
64.5
BOARD #3
64.3
Figure 18 shows that the boards are much closer in HD3
performance and we can detect a clear pattern in the response
shape. As the frequency moves above 60MHz, the filter rolloff
above 180MHz is really starting to attenuate the HD3 at the ADC
inputs. Above 85MHz, the HD3 out of the amplifier appears to be
coming up faster than the filter is rolling it off. In any case, all 3
boards hold about -80dBc worst case over this 10MHz to
100MHz span.
BOARD #1
64.1
63.9
63.7
63.5
10
70
FIGURE 17. TESTED HD2 FOR 3 BOARDS AT -10dBm BOARD EDGE
SINGLE TONE POWER
65.5
64.7
50
ANALOG FREQUENCY (MHz)
(dBc)
It is of course also possible to use the ADC to measure the
frequency response through the FFT. A splitter is used at the
input to measure the change in input signal power required over
frequency to hold the output FFT amplitude for the single tone
input constant over frequency.
BOARD #1
30
50
70
90
110
ANALOG FREQUENCY (MHz)
FIGURE 16. TESTED SNRFS FOR 3 BOARDS AT -10dBm BOARD EDGE
SINGLE TONE POWER
8
Thus, the amplifier interface has degraded the SNRFS by about
0.5dB and the HD2 a varying amount but no more than 9dB,
while the HD3 has been degraded by no more than 6dB.
AN1725.0
March 8, 2012
Application Note 1725
Tested Performance at Lower ADC Clock
Rates
As the clock rate is reduced on the ADC, many fine scale changes
in performance will be observed. The very simple interface of
Figure 9 on page 5 develops the Vcm voltage for the ADC as a
fixed Thevenin source that is then adjusted down by the common
mode input current of the ADC. Measured results on this board
show a 2.8µA/MSPS common mode current into each input of
the ISLA112P50 ADC. As the clock rate decreases, the resulting
Vcm voltage at the ADC inputs will be shifting up. This also has a
lot of fine scale interaction with the ADC performance. Figure 19
shows a typical ADC Vcm vs Clock rate curve for the design
shown here.
Figures 20 through 37 give the typical SNRFS, HD2 and HD3 as
the clock is stepped down in 50MHz steps for 3 different boards.
And remember, all of these require a very low phase noise (or
jitter) clock to get these results.
These plots are mainly showing the variation coming from the
ADC performance as the clock rate and input Vcm voltage is
changing. The signal path up to the ADC inputs is not changing at
all as the clockrate is being swept. These seem to show the SNR
degrading more at low clock rates while the HD performance
actually improves significantly.
1.0
0.8
Vcm (V)
The goal here was to keep the interface as simple as possible
while holding performance. A more sophisticated approach
would be to include a Vcm servo loop to target a fixed ADC Vcm
vs clock rate. It is, however, this increase in Vcm that limits the
lower end of operation to 200MSPS before the ADC common
mode voltage goes out of range for this particular set of values.
However, 200MSPS also matches up with this 100MHz
maximum application bandwidth for a 1st Nyquist zone
implementation.
0.6
0.4
0.2
0
200
250
300
350
400
450
500
SAMPLE RATE (MSPS)
FIGURE 19. ADC Vcm vs CLOCK RATE
9
AN1725.0
March 8, 2012
Application Note 1725
450MSPS
400MSPS
66.0
65.5
65.3
65.5
65.1
BOARD #2
64.9
BOARD #3
BOARD #1
(dBFS)
(dBFS)
64.7
64.5
BOARD #2
65.0
BOARD #3
BOARD #1
64.5
64.3
64.1
64.0
63.9
63.7
63.5
10
63.5
30
50
70
90
110
10
30
ANALOG FREQUENCY (MHz)
110
FIGURE 21. SNR at 400MSPS
FIGURE 20. SNR at 450MSPS
-75
-75
-80
-80
-85
50
70
90
ANALOG FREQUENCY (MHz)
-85
BOARD #3
(dBc)
(dBc)
BOARD #3
-90
-90
BOARD #2
BOARD #2
-95
-95
BOARD #1
-100
10
30
50
70
90
-100
10
110
BOARD #1
30
ANALOG FREQUENCY (MHz)
-75
-80
-80
-85
(dBc)
-85
(dBc)
90
110
FIGURE 23. HD2 at 400MSPS
-75
BOARD #3
BOARD #1
BOARD #2
BOARD #1
BOARD #3
BOARD #2
-90
-95
-100
10
70
ANALOG FREQUENCY (MHz)
FIGURE 22. HD2 at 450MSPS
-90
50
-95
30
50
70
ANALOG FREQUENCY (MHz)
FIGURE 24. HD3 at 450MSPS)
10
90
110
-100
10
30
50
70
90
110
ANALOG FREQUENCY (MHz)
FIGURE 25. HD3 at 400MSPS
AN1725.0
March 8, 2012
Application Note 1725
350MSPS
300MSPS
66.0
66.0
65.5
65.5
BOARD #3
(dBFS)
(dBFS)
BOARD #2
65.0
BOARD #1
64.5
BOARD #2
BOARD #3
BOARD #1
64.5
64.0
63.5
10
65.0
64.0
30
50
70
90
63.5
10
110
30
50
70
90
110
ANALOG FREQUENCY (MHz)
ANALOG FREQUENCY (MHz)
FIGURE 27. SNR at 300MSPS
FIGURE 26. SNR at 350
-75
-75
-80
-80
BOARD #2
(dBc)
(dBc)
BOARD #1
BOARD #3
-85
-85
-90
-90
BOARD #3
-95
-100
10
30
50
70
90
BOARD #2
-95
BOARD #1
-100
10
110
30
ANALOG FREQUENCY (MHz)
-75
90
110
-75
-80
-80
BOARD #2
-85
(dBc)
(dBc)
-85
-90
-90
BOARD #3
-100
10
70
FIGURE 29. HD2 at 300MSPS
FIGURE 28. HD2 at 350MSPS
-95
50
ANALOG FREQUENCY (MHz)
BOARD #2
BOARD #3
BOARD #1
BOARD #1
-95
30
50
70
ANALOG FREQUENCY (MHz)
FIGURE 30. HD3 at 350MSPS
11
90
110
-100
10
30
50
70
90
ANALOG FREQUENCY (MHz)
110
FIGURE 31. HD3 at 300MSPS
AN1725.0
March 8, 2012
Application Note 1725
250MSPS
200MSPS
66.0
66.0
65.5
65.5
BOARD #2
BOARD #1
65.0
65.0
(dBFS)
(dBFS)
BOARD #2
BOARD #3
64.5
BOARD #3
64.5
BOARD #1
64.0
64.0
63.5
10
60
ANALOG FREQUENCY (MHz)
63.5
10
110
FIGURE 32. SNR at 250MSPS
30
50
70
90
ANALOG FREQUENCY (MHz)
110
FIGURE 33. SNR at 200MSPS)
-75
-75
-80
-80
BOARD #1
-85
(dBc)
(dBc)
-85
-90
-90
BOARD #3
BOARD #3
-95
-95
BOARD #2
-100
10
BOARD #1
BOARD #2
-100
30
50
70
90
10
110
30
50
70
90
110
ANALOG FREQUENCY (MHz)
ANALOG FREQUENCY (MHz)
FIGURE 34. HD2 at 250MSPS
FIGURE 35. HD2 at 200MSPS
-75
-75
-80
-80
BOARD #2
-85
(dBc)
(dBc)
-85
-90
BOARD #3
BOARD #1
BOARD #3
-90
BOARD #1
BOARD #2
-95
-95
-100
10
30
50
70
90
ANALOG FREQUENCY (MHz)
FIGURE 36. HD3 at 250MSPS
12
110
-100
10
30
50
70
90
110
ANALOG FREQUENCY (MHz)
FIGURE 37. HD3 at 200MSPS
AN1725.0
March 8, 2012
Application Note 1725
Conclusions
TABLE 1. PCB SUPPORTED ADCs (Continued)
This combination amplifier + DAQ/ADC board is essentially
delivering a much lower full scale input solution with minimal
degradation from ADC only performance. A rough set of
specifications might be in the following:
1. 200mVP-P full scale input
2. 100kHz to 100MHz flat response
4. <600mW combined power dissipation
5. 65dB SNRFS
6. -80dBc worst case HD2, -80dBc worst case HD3
Considerable flexibility exists on the board to modify the input
transformer selections, amplifier gain and interstage filter design
to target different frequency ranges for digitization. The ADC
itself can also be swapped out for numerous pin-compatible
alternatives. These include 8-, 10-, and 12-bit pin-compatible
parts in the ISLA1XXP50 family as well as 10-, 12-, and 14-bit pin
compatible parts in the KAD55XX family, See Table 1 for a list of
ADCs that this PCB supports.
TABLE 1. PCB SUPPORTED ADCs
RESOLUTION
RESOLUTION
MAXIMUM SAMPLE RATE(Msps)
KAD5514P
14
125/170/210/250 grades
KAD5512P
12
125/170/210/250 grades
KAD5512HP
12
125/170/210/250 grades
KAD5510P
10
125/170/210/250 grades
Swapping out the ISLA112P50 for these other options may
require a re-design of the interstage filter and Vcm setup circuit
values.
3. 200MSPS to 500MSPS clock rate
PART NUMBER
PART NUMBER
MAXIMUM SAMPLE RATE(Msps)
In addition, the board will need to be re-programmed to allow for
operation with the Konverter ADC software, contact the factory if
you need assistance.
In summary, this board offers a good breadboarding platform to
get performance measures over a large range of designs before
committing to end equipment layout.
Appendix A: RF Generators
Intersil uses the following RF generators as clock and signal
sources when characterizing high-speed ADCs:
• Rohde & Schwarz: SMA100A
ISLA112P50
12
500
• Agilent: 8644B (with Low-Noise option)
KAD5512P-50
12
500
ISLA110P50
10
500
KAD5510P-50
10
500
ISLA118P50
8
500
These generators provide very low jitter to optimize the SNR
performance of the ADC under test. Other generators with similar
phase noise performance can also be used. Contact Intersil
Technical Support for recommendations.
Bill of Materials
DESIGNATOR
C1, C6, C7, C31
COMMENT
33µF
DESCRIPTION
SIZE
NUMBER
MANUFACTURER
Capacitor
(Polarized)
C-SIZE
4
Kemet
MAN. PART NUMBER
T491C336K016AT
C2, C3, C1005
0.1µF
Capacitor
0603
3
Murata
GRM188R71E104KA01D
C1007
4.7µF
Capacitor
603
1
TDK
C1608X5R1A475K/0.80
C4, C5, C12, C13, C14, C15, 0.1µF
C20, C22, C24, C25, C26,
C27, C33, C34, C42, C43,
C44, C45, C48, C50, C52,
C1014
Capacitor
0402
22
TDK
C1005X7R1C104K
C28, C29, C49, C51
Capacitor
0402
4
Panasonic
ECJ-0EB1H102K
1000pF
C30
10000pF
Capacitor
0402
1
TDK
C1005X7R1C103K
C32
1000pF
Capacitor
0603
1
AVX
06035C102KAT2A
C1010,C1012
4.7µF
Capacitor
402
2
TDK
C1005X5R0J475K
C53
220pF
Capacitor
0603
1
TDK
C1608C0G1H221J
C1001
4.7µF
Capacitor
(Polarized)
3528
1
Kemet
T491B475K010AT
C1002
1.0µF
Capacitor
1206
1
TDK
C3216X7R1C105K/1.15
C1004, C1009
0.047µF
Capacitor
0603_X2Y
2
Johanson
Dielectrics Inc
160X14W473MV4T
Cdiff
10pF
Capacitor
0603_X2Y
1
Johanson
Dielectrics Inc
500X14N100MV4T
13
AN1725.0
March 8, 2012
Application Note 1725
Bill of Materials (Continued)
DESIGNATOR
COMMENT
DESCRIPTION
SIZE
NUMBER
MANUFACTURER
MAN. PART NUMBER
INPUT
SMA END
LAUNCH
Edge Launch SMA
1
Emerson
142-0701-851
J1
2MM HDR 14P
SMT
JTAG
1
Molex
87832-1420
J4
SMA
SMA
2
Amphenol
901-144-8RFX
J6
1
Molex
53475-1879
L3, L4, L13, L14, L15, L16, Bead
L17, L18
connector
0805
8
TDK
MMZ2012R102A
L1001
BEAD
1206
1
Laird signal
HZ1206E601R-10
L1002, L1003
47nH
Inductor
0603
2
Coilcraft
0603CS-47NXGLU
R1016, R1017
28.7Ω
Resistor
0402
2
Panasonic
ERJ-2RKF28R7X
R1, R3, R4, R5, R6, R7, R8, 1k
R9, R10, R11, R12, R13,
R30, R35, R36, R38, R40,
R41, R42
Resistor
0402
19
Vishay
CRCW04021K00FKED
R2, R29, R31, R37, R39
4.7k
Resistor
0603
5
Yageo
RC0603FR-074K7L
R14, R28
1k
Resistor
0603
2
Yageo
RC0603FR-071KL
R27,
200
Resistor
0402
1
Panasonic
ERJ-2RKF2000X
R1008, R1011
412Ω
Resistor
0402
2
Panasonic
ERJ-2RKF4120X
R32, R33, R1000
0Ω
Resistor
0603
7
Stackpole
RMCF0603ZT0R00
R1013, R1014
29.4Ω
Resistor
0402
2
Panasonic
ERJ-2RKF29R4X
R1019
392Ω
Resistor
0402
1
Panasonic
ERJ-2RKF3920X
R48, R1006, R1007,
R1021
100Ω
Resistor
0402
4
Yageo
RC0402FR-07100RL
R1020
118Ω
Resistor
0402
1
Panasonic
ERJ-2RKF1180X
R34
10k
Resistor
0603
1
Yageo
RC0603FR-0710KL
R46
10k
Resistor
0402
1
Stackpole
RMCF0402FT10K0
R49, R50, R51, R52, R53,
R54, R55, R56
49.9
Resistor
0402
8
Panasonic
ERJ-2RKF49R9X
R18, R1009, R1010
0Ω
Resistor
0402
3
Panasonic
ERJ-2GE0R00X
R1015, R1018
187Ω
Resistor
0402
2
Panasonic
ERJ-2RKF1870X
Rterm3
50
Resistor
0603
1
Panasonic
ERJ-3EKF49R9V
T1
ADT4-6T
Transformer
CD542
1
Minicircuits
ADT4-6T
T2
ADTL1-4-75+
1:1 Transmission
Line Transformer
CD542
1
Minicircuits
ADTL1-4-75+
T3
TC4-1W
Center-Tapped
Transformer
AT224
1
Minicircuits
TC4-1W+
U7
74AHC1G04
Inverter
SOT23-5
1
TI
SN74AHC1G04DBVR
U2, U3
24FC128-I/SN
EEPROM
SO8
2
Microchip Tech
24FC128-I/SN
U4
XC2C64A6VQG44C
CPLD
VQFP44
1
Xilinx
XC2C64A-5VQG44C
U6
ISL55210
Hi Speed Ultra Low
Distortion
Differential
Amplifier
TQFN16
1
Intersil
ISL55210IRTZ
U1
ISLA112P50
500MSPS,
12-bit ADC
QFN
10X10 72
1
Intersil
ISLA112P50IRZ
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
AN1725.0
March 8, 2012
C13
C15
C20
C22
C25
C26
C42
C43
C44
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C12
C36
DNP
C37
DNP
SDO
CSB
OVDD
SDIO
C35
DNP
C27
0.1uF
SCLK
C24
0.1uF
pin36
OVDD
pin27
OVDD
C14
0.1uF
C45
pin56
pin70
pin23
OUTFMT
pin22
nap_sleep_normal
output_mode
pin16
clkdivn
pin15
Vcm
pin71
pin24
AVDD
pin19
AVDD
AVDD
pin12
AVDD
pin6
pin1
AVDD
AVDD
ISLA112P50/55210EV1Z Schematics
C38
DNP
0.1uF
Bead
L14
Bead
C9
DNP
C10
DNP
2
3
4
5
SCL
SDA
AVDD
GND
GND
C11
DNP
6
7
8
9
10
Vinm
Vinp
GND
AVDD
OVDD
DGND
56
55
ORP
ORN
D13P
D13N
D12P
D12N
D11P
D11N
DGND
64
63
62
61
60
59
58
57
65
OVSS
ORP
ORN
D11P
D11N
D10P
D10N
D9P
D9N
SDIO
SCLK
CSB
SDO
69
68
67
66
D8P
D8N
D7P
D7N
D6P
D6N
DNC
DNC
DNC
DNC
AVDD
AVSS
AVSS
CLKOUTP
CLKOUTN
VINN
VINP
RLVDS
OVSS
AVSS
AVDD
DNC
DNC
VCM
CLKDIV
DNC
DNC
AVDD
CLKP
CLKN
Vcm
clkdivn
11
12
13
14
15
16
17
18
AVDD
OVDD
OVSS
L13
C8
DNP
SCL
SDA
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
54
53
52
51
50
49
D10P
D10N
D9P
D9N
D8P
D8N
48
47
CLKOUTP
CLKOUTN
46
10K
45 DGND
44
43
42
41
40
39
38
37
R46
D7P
D7N
D6P
D6N
D5P
D5N
D4P
D4N
OVDD
Bead
SYNC_RES_N
SYNC_RES_P
DNC
DNC
D0N
D0P
D1N
D1P
Bead
L3
RESETN
OVSS
OVDD
L4
SD0
U1
ISLA112P50
Application Note 1725
SC0
1
OUTMODE
NAPSLP
AVDD
AVDD
SDIO
SCLK
CSB
SDO
EP
AVSS
AVDD
OUTFMT
0
GND
15
72 GND
71 AVDD
70
OUTFMT
0.1uF
OVDD36
D1N
D1P
D2N
D2P
D3N
D3P
28
29
30
31
32
33
34
35
25
DGND26
OVDD27
RESETN
22
output_mode
nap_sleep_normal23
AVDD24
clk_inp
clk_inn
AVDD19
20
21
Under DUT.
L15
bead
L16
bead
R16
L17
bead
L18
bead
D0N
D0P
DNP
R17
DNP
anlg_1.8V
HI= Gray_Code
LO= Unsign
Ft=Twos_Comp
R15
DNP
anlg_1.8V
R25
DNP
OUTFMT
R14
1K
HI=2mA LVDS
LO= LVCMOS
Ft= 3mA LVDS
anlg_1.8V
R22
DNP
output_mode
R24
DNP
HI= clk_div4
LO= clk_div2
Ft=clk_div1
anlg_1.8V
R26
DNP
clkdivn
R23
DNP
HI= Nap
LO = Normal
Ft= Sleep
nap_sleep_normal
R28
1K
INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGR
Title
Size
B
FIGURE 38. ISLA112P50/55210EV1Z (1 OF 3)
ISLA112P50/ISL55210
Number
page1
Revision
C
AN1725.0
March 8, 2012
ISLA112P50/55210EV1Z Schematics (Continued)
ANLG_3.3V
2
R1000
2 1
L1001
1 +anlg_3.3V
C1001 + BEAD
4.7uF
0
R1001
VS_AMP
C1002
1.0uF
5kohm/DNP
C1004
R1003
2.05kohm/DNP
C1003
DNP
X2Y
0.09uF
VS_AMP
R1002
20ohm/DNP
34
5
NC
NC
Rterm1
DNP
4
R1007
0
100ohm
Rbypass2
1 2
DNP
2
1
Rbypass4
1 2
DNP
Cterm2
2.2pF/DNP
3
Vi+
R1010 0ohm
4
FBR1011 412ohm
VCM
13
15
14
Vs+
Vcm
R1008 412ohm
1
Fb+
R1009 0ohm
2
Vi-
R1005
7.68kohm/DNP
Vo+
NC
NC
Vo-
R1021
130ohm
C1010
R1013
12
Vinm
29.4ohm
11
L1002
47nH
4.7uF
C16
DNP
10
R1014
9
29.4ohm
Cdiff
10pF
L1003
47nH
C1012
C1015
DNP
C1016
DNP
To ADC
Vinp
4.7uF
R1015
187ohm
2
C1017
VS_AMP
R1016
28.7ohm
0.1uF
C1009
X2Y
0.09uF
ADT1-1WT
Vtest
C1019
C1008
DNP
R1017
28.7ohm
1
C1018
R1018
187ohm
R1016, R1017 default populate as 1uH Inductors
U7
1
2
3
0.1uF
2
VS_AMP
NC
VCC
5
A
GND
74AHC1G04
Y
4
Rterm2
50ohm/DNP
Pd
1
2
DNP
Rterm3
50ohm
FIGURE 39. ISLA112P50/55210EV1Z (2 OF 3)
0.1uF
Application Note 1725
1
Cterm1
2.2pF/DNP
GND
100ohm
R1019
422ohm R1020
107ohm
C1014
1uF
U6
ISL55210
GND
25
R1006
.
R1004
10kohm/DNP
8
2
3
R18
ADTL1-4-75
6
Pd
2
4.7uF
16
Vs+
1
7
.
ADT4-6T
C1007
1
2
6
INPUT
Rbypass3
1 2
DNP
EP
GND
1
GND
16
2
5
Rbypass1
1 2
DNP
1
0
16
C1005
0.1uf
AN1725.0
March 8, 2012
ISLA112P50/55210EV1Z Schematics (Continued)
anlg_3.3V
Anlg_5V
RESETN
D13P
D13N
R37
4.7K
D11P
D11N
0.1uF
R39
R3
1K
D5P
D5N
D4P
D4N
D3P
D3N
D2P
D2N
VCC
VCC
0.1uF
ID EEPROM
U3
1
2
3
4
WP
A0
A1
A2
Vss
8
7
6
5
Vcc
WP
SCL
SDA
WP_2V
SC2
SD2
24FC128-I/SN
U4
=value
dig_1.8V
IO(2)
IO(2)
IO(2)
IO(2)
I(2)
GND
IO(1)
VCC
IO(1)
IO(1)
IO(1)
R2
4.7K
23
24
TDO
25
26
dig_1.8V
SCLK
27
SDO
28
R5
1K 29
R6
1K 30
31
SDIO
CSB
32
33
C3
dig_1.8V
SPI_CONF
R35
1K
R1
1K
D6P
D6N
0.1uF
IO(2)
TDO
GND
VCCIO2
IO(2)
IO(2)
IO(2)
IO_GLB_S/R
IO_GOE
IO_GOE
IO_GOE
R7
1K
TCK
TMS
TDI
IO(1)
VCCIO1
I/O(1)
I/O(1)
GND
I/O(1)
I/O(1)
I/O(GCK)
11
TCK
10
TMS
9
TDI
8 R9
1K
7
VCC
6
R10
1K
5
R11
1K
4
3
R12
1K
2
R13
1K
CPLD SPARE1
1
C2
D1P
D1N
D0P
D0N
dig_1.8V
0.1uF
SPARE EEPROM
U2
1
2
3
4
PC3
A0
A1
A2
Vss
Vcc
WP
SCL
SDA
4.7K
4.7K
D7P
D7N
C5
0.1uF
8
7
6 R33
5 R32
WP_2V
0
0
R31
R29
dig_1.8V
CLKOUTP
CLKOUTN
C34
0.1uF
10K
D8P
D8N
C33
dig_1.8V
22
21
20
19
18
R4 1K
17
16
R8 1K
15 dig_1.8V
14
R41 1K
13
R40 1K
12
PC1
D10P
D10N
dig_1.8V
C1
33uF
dig_1.8V
4.7K
D9P
D9N
dig_1.8V
C4
R34
D12P
D12N
PORn_ExtResetn_fpga
33uF
C7
ORP
ORN
dig_1.8V
dig_1.8V
VCC
SC0
SD0
24FC128-I/SN
PC6
PC7
PC0 daughter card detected
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC4
PC5
PC2
WP
SPI_master_drive
CPLD SPARE1
SCLK_3V
CSB_3V
MISO_3V
MOSI_3V
SD0
SC0
SD2
SC2
PORn_ExtResetn_fpga
MH1
MH2
MH3
MH4
JTAG connector
PLCD Programing
J1
DGND
GND
Tooling Hole Tooling Hole Tooling Hole Tooling Hole
1
3
5
7
9
11
13
2
4
6
8
10
12
14
VCC
TMS
TCK
TDO
TDI
INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDI
2MM HDR 14P SMT
Title
Size
B
AN1725.0
March 8, 2012
Date:
File:
53475 1879
FIGURE 40. ISLA112P50/55210EV1Z (3 OF 3)
ISLA112P50/ISL55210
Number
R
page3
16-Nov-2011
Sheet of
C:\Documents and Settings\GHENDRIC\Desktop\New
Drawn By: Fol
Application Note 1725
AVDD
33uF anlg_1.8V
C31
C_vdd3_anlg
Dig_5V
IO_GOE
VAUX
IO(2)
IO(2)
IO(2)
IO(1)
IO(1)
IO(1)
IO(1)
IO(GCK)
IO(GCK)
17
DGND
GND
AVDD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
34
35
36
37
38
39
40
41
42
43
44
33uF
C6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
R30
1K
VCC
R36
1K
R38
1K
WP_2V
SCLK_3V
CSB_3V
SPI_master_drive
R42
1K
MISO_3V
MOSI_3V
J6
dig_1.8V
OVDD
OVDD
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