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AN-1101
1
Applicatiion Note
Application
n with
h SCAL
LE™-2
2 Gate
e Drive
er Corres
Single an
nd Dual-C
Channel SCALE™S
-2 IGBT and
a MOSF
FET Driveer Cores
Introdu
uction an
nd Overvie
ew
The SCALE™
™-2 IGBT an
nd MOSFET gate
g
driver ccores are highly integrate
ed low-cost ccomponents which provid
de
the user witth the highe
est level of te
echnology an
nd functionality for indusstrial and traaction require
ements. These
features, co
oupled with their
t
flexibilitty of design,, have alread
dy made man
ny power co nverters highly successfu
ul.
Neverthelesss, SCALE-2 gate driver cores are n
not plug-and
d-play gate drivers.
d
A m
minimum und
derstanding of
power electtronics is therefore necesssary to deveelop reliable inverter
i
syste
ems with theese cores.
This Applica
ation Note will
w highlightt important design ruless to help ussers and avooid qualificattion problem
ms.
Moreover itt will help to
o speed up the developm
ment time by
y showing de
etailed exam
mples about how to desig
gn
SCALE-2 gate driver corres successfu
ully.
Considered SCALE-2 ga
ate driver co
ores are: 2S
SC0106T, 2SC0108T, 2SC0435T,
2
P, 1SC2060P,
2SC0650P
T, 2SC0635T
T and 1SC04
450V.
2SC0535T
Fig. 1 SCA
ALE-2 gate drriver cores
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Pag
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AN-1101
Application Note
Contents
Applications with SCALE-2 Products .............................................................................................. 3 SCALE-2 in Different Topologies .................................................................................................... 3 Use of SCALE-2 gate driver cores in three-level or multilevel topologies .................................... 3 Use of a single SCALE-2 gate driver for paralleled IGBTs/MOSFETs ........................................... 4 Direct paralleling.................................................................................................................... 5 Application Circuits ........................................................................................................................ 6 Minimum pulse suppression for inputs INA and INB ................................................................. 6 Increase of the noise immunity at inputs INA and INB (excluding 2SC0635T) ............................ 7 Use of external optical interface with SCALE-2 gate drivers with internal electrical interface ....... 8 Half-bridge mode ................................................................................................................... 9 External implementation of half-bridge mode......................................................................... 10 External implementation of minimum channel interlock time................................................... 11 Use of SOx fault outputs ...................................................................................................... 11 Use of gate resistors ............................................................................................................ 12 VEx terminal characteristics .................................................................................................. 13 Required blocking capacitors C1x and C2x ............................................................................... 14 VCEsat detection with SCALE-2 gate driver cores (excluding 2SC0108T) .................................... 15 Disable VCEsat detection by SCALE-2 (excluding 2SC0106T and 2SC0108T) ............................... 19 Disabling the Advanced Active Clamping ............................................................................... 20 Rail-to-rail output and gate voltage clamping......................................................................... 20 MOSFET mode (not available on 2SC0106T and 2SC0108T) ................................................... 21 Paralleling a dual-channel driver to a single output (not available on 2SC0106T) ..................... 22 Disabling one channel for chopper applications ...................................................................... 23 Position of the Gate Driver in the Converter................................................................................ 24 Driver placement on top of 17mm IGBT modules or close to high magnetic fields .................... 24 AC and DC bus bar .............................................................................................................. 24 PCB Layout ................................................................................................................................... 25 PCB thickness ...................................................................................................................... 25 Separation of areas with different high-voltage potentials ...................................................... 25 Use of planes ...................................................................................................................... 26 Clearance and creepage distances for PCBs ........................................................................... 27 Gate driver cores in applications at higher altitudes ............................................................... 27 CONCEPT base boards ......................................................................................................... 28 Typical Application Failures ......................................................................................................... 29 Bibliography ................................................................................................................................. 30 Legal Disclaimer ........................................................................................................................... 30 Manufacturer................................................................................................................................ 30 www.IGBT-Driver.com
Page 2
AN-1101
Application Note
Applications with SCALE-2 Products
A successful use of SCALE-2 gate driver cores is coupled with an appropriate overall design. The key points
listed below are success factors for the use of SCALE-2 gate drivers:

Topology (e.g. how to parallelize IGBT modules)

Schematics and right choice of components

Geometrical location of IGBT gate drivers (where to place gate drivers)

Magnetic field influences

Clearance and creepage distances

PCB layout

Use of standards

EMI considerations
SCALE-2 in Different Topologies
Use of SCALE-2 gate driver cores in three-level or multilevel topologies
During the operation of three-level converters, regular semiconductor commutation ensures that the inner
IGBTs/MOSFETs are not turned off when the outer IGBTs/MOSFETs are in the on-state in order to avoid the
full DC-link voltage being applied to the corresponding power semiconductors.
This situation must be considered when using CONCEPT SCALE-2 gate drivers. Such events could happen if
the protection function of the gate drivers detects a short circuit or in the case of power-supply under-voltage.
After fault detection, the gate driver turns the corresponding channel off immediately (exceptions are
2SC0635T and 1SC0450V, where a delay between secondary fault detection and IGBT turn-off can be
programmed, see the corresponding product documentation /1/, /2/). The power semiconductors are not
usually designed to withstand the full DC-link voltage. Destruction of the power semiconductor can
consequently be prevented only if an adequate protection scheme is applied.
SCALE-2 Advanced Active Clamping protects the IGBTs/MOSFETs from excessive collector-emitter voltages in
such situations. It therefore obviates the need to provide a dedicated turn-off sequence for the driver channels
to be turned off in the fault condition - instead, the turn-off commands may be applied immediately after fault
feedback. It is recommended to apply a common turn-off command to all IGBT drivers within the converter to
achieve a stable system state after fault feedback.
Please also refer to Application Note AN-0901 /3/ or to the paper “Safe Driving of Multi-Level Converters Using
Sophisticated Gate Driver Technology” /5/ for more information.
Note: The under-voltage protection function of the SCALE-2 chipset cannot be disabled. The gate driver
channel is turned off as soon as an under-voltage event is detected on the primary or secondary side
(exceptions: 2SC0635T and 1SC0450V, for which a delay can be programmed in case of a secondary-side
fault). The use of active clamping consequently offers the best protection. In such cases, however, CONCEPT
highly recommends testing the effectiveness of the active clamping function in the final converter design.
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AN-1101
1
Applicatiion Note
Fig. 2 Thre
ree-level convverter with use
u of Advancced Active Clamping
Cl
Use of a single SC
CALE-2 ga
ate driver for parallleled IGB
BTs/MOSF
FETs
Advanced Active Clam
mping in pa
arallel IGBT
T operation with one common
c
driiver core
Active clamping is a technique desig
gned to partiially turn on the power se
emiconductoor as soon ass the collecto
orain-source) voltage
v
excee
eds a predeffined thresho
old. The power semicond uctor is then
n kept in line
ear
emitter (dra
operation.
e clamping to
opologies imp
plement a sin
ngle feedbacck path from the IGBT’s ccollector thro
ough transie
ent
Basic active
voltage sup
ppressor devvices (TVS) to
t the IGBT
T gate. Most SCALE-2 prroducts suppport CONCEP
PT’s Advance
ed
Active Clam
mping, where
e feedback iss also provid ed to the drriver’s second
dary side at pin ACLx: As
A soon as th
he
voltage on tthe right side of the 20Ω
Ω resistor of Fig. 3 excee
eds about 1.3V, the turnn-off MOSFET
T of the drivver
stage is pro
ogressively sw
witched off in
n order to im
mprove the effectiveness
e
of the activee clamping and
a reduce th
he
losses in the TVS. The turn-off MOS
SFET is com pletely switcched off whe
en the voltagge on the rig
ght side of th
he
es 20V (mea
asured with respect to COMx).
C
In pa
arallel IGBT operation with
w
the use of
20Ω resistors approache
A
Acctive Clampin
ng needs to control all parallel-connnected IGBTs/MOSFETs. A
only one drriver core, Advanced
separate fee
edback to evvery gate is required
r
acco
ording to Fig. 3.
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Pag
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AN-1101
Application Note
Gate 1
D4x
SCALE-2
Gate 2
Driver Core
ACLx
Caclx
D4x
20
D4x
D1x
D2x
D1x
D2x
Collector 1
Collector 2
Raclx
Caclx
COMx
D2x
Raclx
Caclx
Gate 3
D3x
D1x
Collector 3
Raclx
Fig. 3 Active clamping by paralleling three IGBTs/MOSFETs with one common gate driver core
It is recommended to use the circuit shown in Fig. 3 for parallel operation with one gate driver core
(exceptions: 2SC0635T and 1SC0450V, for which D3x and the 20 resistors are already included in the driver
core and therefore need not be used externally). For dimensioning the TVS, Raclx, Caclx, D3x and D4x, please
refer to the corresponding application manual /1/. Note that at least one of the series connected TVS must be
of bidirectional type.
VCEsat in parallel operation with one driver core
In general, CONCEPT recommends the use of only one VCEsat detection circuit by using only one central gate
driver core for paralleled IGBTs/MOSFETs, as this is sufficient to efficiently protect the system. The VCEsat
detection is connected to one of the parallel-connected IGBTs/MOSFETs. All paralleled IGBTs desaturate at the
same time in the short-circuit condition. The maximum short-circuit current is limited by the IGBTs.
It is not recommended to connect auxiliary collectors of paralleled high-side IGBTs, as:

A large offset current may flow and

oscillations may occur.
Moreover, the measurement of over-current via the VCEsat detection is not recommended.
VISOx
SCALE-2
DC-Bus +
D6x
Driver Core
Collector 2
Collector 1
VCEx
Cax
COMx
120k
Collector 3
Rvcex
Rg(on)
Rg(off)
Rg(on)
Rg(on)
Rg(off)
Rg(off)
Phase Leg
Fig. 4 VCEsat detection by paralleling three IGBTs with one gate driver core
Direct paralleling
Parallel-connected IGBTs are conventionally driven by a common driver, with individual gate and emitter
resistors for each IGBT (see last paragraph). An alternative approach for driving parallel-connected IGBT
modules is to use an individual driver for each module (direct paralleling). This driving option is available for all
driver cores with electrical interface considered in this Application Note.
If direct paralleling of SCALE-2 drivers is required, please refer to the Application Note AN-0904 /4/.
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Page 5
AN-1101
Application Note
Application Circuits
Minimum pulse suppression for inputs INA and INB
SCALE-2 gate drivers with electrical interface feature very fast signal propagation delays of typically <90ns.
This includes a minimum pulse suppression time of 35ns. To avoid false gate switching caused by potential
EMI, the inputs INA and INB may be equipped with additional filters. Fig. 5 illustrates how to increase the
minimum pulse suppression time for driver cores with electrical interface if the SCALE-2 internal minimum
suppression time is not long enough.
Fig. 5 shows that it is not recommended to apply a RC network directly to INA or INB as the jitter of the
propagation delay may increase considerably. The use of a Schmitt-trigger is recommended to avoid this
drawback.
Note that it is recommended to parallel the inputs INA/INB of the drivers after the Schmitt-trigger inverters if
direct paralleling is used together with minimum pulse suppression. The use of a Schmitt-trigger inverter for
each driver core is not recommended by direct paralleling as the delay divergence of the Schmitt-trigger
inverters may be too high, leading to an excessive dynamic current imbalance during IGBT commutation.
VDC
SO1
SO2
MOD
R1
INA
GND
TB
VCC
C1
GND
INA
R1
INB
GND
INB
GND
C1
VDC
SO1
SO2
INA
GND
A
R1
1
2
3
CD40106
C1
INB
GND
B
CD40106
TB
VCC
GND
C
R1
4
MOD
5
C1
INA
D
6
9
CD40106
8
CD40106
INB
GND
1
2
3
4
5
SCALE-2
6
Driver Core
7
8
9
10
1
2
3
4
5
SCALE-2
6
Driver Core
7
8
9
10
Fig. 5 Minimum pulse suppression for INA and INB for SCALE-2 driver cores
The R1/C1 combination together with a 15V Schmitt-trigger inverter CD40106 create minimum pulse
suppression. As an example, the Schmitt-trigger input hysteresis is 5V if the turn-on level is 10V and the turnoff level is 5V. If INx turns on with 15V logic, the capacitor C1 is charged by R1. When the voltage across C1
reaches 10V, the Schmitt trigger switches. If INx becomes low (turn-off command) and the voltage across the
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Page 6
AN-1101
Application Note
capacitor C1 falls below 5V, the Schmitt trigger switches. In the example, which uses two Schmitt-trigger
inverters, the input signals do not need to be inverted.
The minimum pulse suppression time Tmin,on at turn-on can be calculated as follows:
VDD
)
Tmin,on  R1  C1  ln(
VDD  VTH , high
Eq. 1
where VTH,high is the upper Schmitt-trigger threshold and VDD is the logic level of INx.
The minimum pulse suppression time Tmin,off at turn-off can be calculated as follows:
V
Tmin,off  R1  C1  ln( DD )
VTH ,low
Eq. 2
where VTH,low is the lower Schmitt-trigger threshold and VDD is the logic level of INx.
Example:

Tmin,on=500ns: R1=3.3kΩ, VTH,high=10V, VDD=15V, C1= 138pF

Tmin,off=1μs: R1=3.3kΩ, VTH,low=5V, VDD=15V, C1= 276pF
Increase of the noise immunity at inputs INA and INB (excluding 2SC0635T)
Most SCALE-2 gate driver cores with electrical interface turn on the corresponding channel when INA/INB
reaches a threshold voltage of about 2.6V (exception: 2SC0635T). The turn-off threshold voltage is about
1.3V, resulting in a hysteresis of 1.3V. In some applications with very high noise interference voltages (EMI),
or when long cables are used, increasing the input threshold voltage helps to avoid irregular switching events.
For this purpose, a voltage divider R2/R3 is placed as close as possible to the gate driver core according to Fig.
6. The minimum distance between the voltage divider R2/R3 and the gate driver is essential to avoid inductive
coupling on the PCB layout.
VDC
SO1
SO2
MOD
R2
INA
GND
TB
R3
VCC
GND
INA
R2
INB
GND
INB
R3
GND
1
2
3
4
5
6
SCALE-2
Driver Core
7
8
9
10
Fig. 6 Increased threshold voltages INA and INB with SCALE-2 gate driver cores
Example: Setting R2=3.3kΩ, R3=1kΩ and INA=15V at turn-on. Without R2 and R3, the gate driver turns on as
soon as INA reaches 2.6V. The voltage divider increases the turn-on threshold voltage to about
11.2V. The turn-off threshold voltage is now about 5.6V. In this example, the INA and INB signal
drivers have to provide 3.5mA during the IGBT on-state.
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Page 7
AN-1101
1
Applicatiion Note
Use of ex
xternal op
ptical inte
erface witth SCALE--2 gate drivers witth interna
al
electrical interfac
ce
For applicattions requirin
ng optical PW
WM inputs an
nd fault outp
puts, CONCEPT products permit different solution
ns.
Beside stan
ndard plug-a
and-play driv
ver solutionss for high-vo
oltage IGBTs and the ddriver core 1SC0450V, an
a
alternative solution is to
t just use an
a optical in
nterface in frront of a SC
CALE-2 IGBT
T gate driverr core with an
a
n example off how to drive a SCALE--2 driver corre with a sta
andard AVAG
GO
electrical interface. Fig. 7 shows an
anufacturerss, e.g. TOSHIIBA, PANASO
ONICS, … con
ntact the CO
ONCEPT supp
port service). A
HFBR type ((for other ma
Schmitt trig
gger CD4010
06 (supplied with 5V) invverts the ou
utput signal of the HFBR
R-2522ETZ in
nto a 5V log
gic
signal. This signal drivess the SCALE--2 gate driveer core. The open drain fault
f
outputss SO1 and SO
O2 have a 1kkΩ
e the optical interface. T he light is on during the
e normal conndition and off
o in the fau
ult
pull-up resisstor to drive
condition. T
The diode cu
urrent during
g normal opeeration is about 15mA. During
D
the faault condition, this curre
ent
flows via op
pen drain SO1 and/or SO2, respectiveely. The max
ximum allowe
ed SO1/SO2 load current is 20mA.
Fig. 7 Opti
tical interfacee driving a SC
CALE-2 gate driver core
Only direct mode is reccommended (MOD is co
onnected to GND)
G
with the use of tw
wo or more SCALE-2 ga
ate
(
8). Thee inputs INA and INB of each driver are connectted in paralle
el.
driver coress with direct paralleling (Fig.
The SOx fault outputs can
c be connected togeth
her or each can be wired to a fiber--optics interfface. A pull-u
up
d as close as possible to
o the gate driver
d
core. This resistorr is calculate
ed for a diod
de
resistor must be placed
approximatelyy 13mA and a maximum open collecttor current of 20mA per cchannel.
current of a
Note that b
both pins TB are parallele
ed. The resisstor value off RB given in the data shheet /2/ musst therefore be
b
divided by ttwo to obtain
n the corresp
ponding blockking time. Th
he power sup
pply of CD400106 must be
e 5V.
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Pag
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AN-1101
1
Applicatiion Note
Fig. 8 Opti
tical interfacee driving para
alleled SCALE
LE-2 gate drivver cores (ex
xample with 22SC0435T)
Note that both circuits of
o Fig. 7 and
d Fig. 8 cann
not be used with
w 2SC0635
5T, as the innput thresholds of INA an
nd
her (adjustm
ment for 15V logic requireed).
INB are high
Half-brid
dge mode
e
The MOD pin – if available – can be
e used to con
nfigure direct or half-brid
dge mode onn dual-channel drivers (se
ee
corresponding applicatio
nformation).
on manual /1
1/ for more in
mended to place the com
mponents Rm and Cm (see
e corresponding applicatioon manual /1/) as close as
It is recomm
possible to tthe MOD pin
ns and to avo
oid big loops..
The dead ttime toleran
nce may varry from prod
duct to prod
duct and fro
om the deadd time setup and is also
dependent o
on the target PCB layout. A tolerancee of approxim
mately ±15%
% may be exppected.
Moreover, it is impermissible to change betweeen direct an
nd half-bridge mode, or the reverse
e during drivver
operation. T
This may result in high-frrequency burrst pulses tha
at may destroy the driverr.
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Pag
ge 9
AN-1101
1
Applicatiion Note
External impleme
entation of
o half-briidge mode
Dead timess between bo
oth channelss of a driverr core can also be generrated with eexternal circu
uitry using th
he
e of the SCA
ALE-2 driver. This can bee useful if th
he required dead
d
time leength is outsside the rang
ge
direct mode
provided byy the SCALE-2 technology
y (about 0.6--4.1µs) or wh
hen higher timing precisioon is needed
d.
The PWM p
pattern, inclu
uding the req
quired dead ttimes, can be
b generated
d using digitaal circuits (e.g. µP, FPGA
As,
CPLDs) or w
with external circuits. Fig
g. 9 below s hows a circu
uit example that
t
generattes dead times in a simillar
way as the SCALE-2 technology, using an enablee signal and a switching signal.
s
Fig. 9 Reco
commended circuit
c
for the
e external geeneration of half-bridge dead
d
times
R and C co
The require
ed dead times TD can be
b approxim
mately set up
p with the components
c
onsidering th
he
thresholds o
of the NAND gates used:
VDDD
TD  R  C  ln(
)
VDD  VTH ,high
Eq. 3
where VTH,hhigh is the upper
u
Schm
mitt-trigger th
nd VDD is th
he logic levvel of the Schmitt-trigg
S
ger
hreshold an
inverters/NA
AND gates, that
t
may be
e 5V…15V. Itt is recomme
ended to use high-speedd switching diodes for th
he
diodes D.
e of TD≈7.7
7µs can be set up witth R=4.7kΩ and C=1.5nF (VDD=15V,
Example: A half-bridge dead time
VTH,high=10V))
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Page
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AN-1101
1
Applicatiion Note
External impleme
entation of
o minimu
um channel interlock time
When dead times are generated extternally using
g the direct mode of the
e SCALE-2 drriver cores, itt is possible to
an interlock circuit accorrding to Fig. 10 that avo
oids simultan
neous switchhing of the in
nputs/outputts,
implement a
even if the g
generated sw
witching sign
nals are incorrrect.
Fig. 10 Reecommended
d circuitry forr setting a mi
minimum interrlock time
The circuit sshown in Fig
g. 10 does no
ot significanttly modify the switching signals INA** and INB* iff the minimu
um
programme
ed interlock tiime TI is not undercut:
VDDD
TI  R  C  ln(
)
VDD  VTH ,high
Eq. 4
hreshold an
where VTH,hhigh is the upper
u
Schm
mitt-trigger th
nd VDD is th
he logic levvel of the Schmitt-trigg
S
ger
inverters/NA
AND gates, that
t
may be
e 5V…15V. Itt is recomme
ended to use high-speedd switching diodes for th
he
diodes D.
als INA* and INB* have a dead timee which is low
wer than the
e programmeed minimum interlock tim
me
If the signa
TI, the dead
d time betwe
een both channels is auto
omatically ex
xtended to TI.
If both signals INA* and
d INB* are high at the saame time, bo
oth channels are turned ooff.
he use of extternal compo
onents increaases the overrall propagattion delay tim
me of the gatte driver.
Note that th
Use of SO
Ox fault outputs
o
The longer the distance
e to the microcontroller, the more EMI-sensitive
E
does the SO
Ox line beco
ome. When no
n
fault condittion is deteccted, the SO
Ox output h
has high imp
pedance. Vo
oltage spikess can thereffore easily b
be
induced.
ecommends the use of the
t circuit sh
hown in Fig. 11 if long cable
c
distancces are necessary or if th
he
CONCEPT re
SOx currentt capability of
o 20mA is not sufficient.. The MOSFE
ETs T11/T12 protect the driver’s SOx
x outputs fro
om
EMI influences. It is add
ditionally reccommended to use pull-d
down resisto
ors on the hoost controller cable side to
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Page
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AN-1101
1
Applicatiion Note
e logic in casse the SOx signal
s
should
d not be connected prope
erly (e.g. brooken cable). Note that th
he
provide safe
pull-down re
esistor value
es must not be
b too low, aas a voltage divider
d
is built with the M
MOSFET pull-up resistors.
The SOx driiving currentt can be easily increased by reducing the 2.7k pulll-up resistorr values of th
he MOSFETs.
Fig. 11 Use
se of SOx fau
ult signals ove
ver long distaances
Note that a protection circuit
c
for the SOx pins aas well as a pull-up resisstor of 10kΩ
Ω is available
e on the drivver
635T and 1S
SC0450V.
cores 2SC06
Use of ga
ate resisttors
Most of the
e SCALE-2 drriver cores fe
eature separrated paths GHx and GL
Lx to connecct the turn-on and turn-o
off
gate resisto
ors. It is ma
andatory to use separate
ted turn-on and turn-offf gate resistoors, as show
wn in Fig. 12.
1
Increased p
power losses and oscillatiions may occcur if GHx is directly connected to GLLx. However, this does not
n
apply to 2SC
C0106T.
Fig. 12 Use
se of gate ressistors with the
t terminalss GHx and GLLx
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Page
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AN-1101
Application Note
Moreover, it is necessary for several reasons to keep the inductance of the gate loop as small as possible:

High gate-loop inductances will alter the switching performance of the IGBT. In particular, faster
commutation may occur during turn-on, which could cause SOA violation of the corresponding freewheeling diode.

The use of high-inductance resistors (e.g. wire wound resistors) is impermissible. It is recommended
to use high-power proofed 1206 SMD resistors (e.g. CRCW1206 resistors from Vishay) or leaded metal
film resistors (e.g. PR02 or PR03 from Vishay) and to measure the temperature increase of the gate
resistors at the target switching frequency to avoid thermal overload. A maximum temperature
increase of 40K or lower is usually recommended. Moreover, the peak power capability of the gate
resistors must not be exceeded.

Reducing the gate loop inductance reduces possible coupling from external magnetic fields into the
gate circuit. Such coupling may alter the gate driver performance, generate oscillations or even lead to
the IGBT SOA being exceeded under certain circumstances. If possible and/or required, shielding
planes can be used to reduce the influence of external magnetic fields.
VEx terminal characteristics
VEx corresponds to the emitter potential. It is an internally generated potential of the SCALE-2 ASIC. During
normal operation, the voltage between the pins VISOx and VEx is regulated to a nominal value of 15V. This is
done by means of a SCALE-2 internal current source and voltage measurement in the secondary ASIC IGD. Its
maximum sink/source capability is limited to ±2.5mA in order to avoid thermal overloading of the ASIC during
operation.
If the secondary voltage between VISOx and COMx begins to fall, the voltage between VISOx and VEx
remains constant at 15V in a first step. The voltage between VEx and COMx is reduced up to about 5.5V. If
the voltage still falls from VISOx to COMx, the voltage from VEx to COMx remains constant at 5.5V and the
voltage from VISOx to VEx begins to fall. This function ensures a proper turn-off of IGBTs even in the event of
a supply under-voltage.
No static load should be applied between VISOx and VEx or between VEx and COMx in order not to disturb the
15V regulation between VISOx and VEx. A static load can be applied between VISOx and COMx if necessary
(e.g. supply load for external electronic functions). This is illustrated in Fig. 13.
29
28
Channel 2
27
26
25
24
23
22
GL2
29
GH2
28
VISO2
VE2
R load
COM2
27
26
25
REF2
24
VCE2
23
ACL2
22
Driver
GH2
VISO2
VE2
COM2
REF2
VCE2
ACL2
Driver
2SC0435T
2SC0435T
18
17
Channel 1
Channel 2
GL2
16
15
14
13
12
11
GL1
18
GH1
17
VISO1
VE1
COM1
REF1
VCE1
ACL1
Channel 1
R load
16
15
14
13
12
11
GL1
GH1
VISO1
VE1
COM1
R load
REF1
VCE1
ACL1
Fig. 13 External loading of VISOx, VEx and COMx (example with 2SC0435T)
www.IGBT-Driver.com
Page 13
AN-1101
Application Note
Note that it is not permitted to insert a resistor between the gate and emitter as shown in Fig. 14, as this
would also statically load the 15V regulator.
COMx
ACLx
Cax
VCEx
Rax
REFx
BAS416
Rvcex
VISOx
Rthx
2SC0435T (one channel)
GHx
GLx
Rg(on)
Rg(off)
4.7k
10k
COMx
VEx
Fig. 14 Impermissible resistor between gate and emitter (example with 2SC0435T)
The voltage at VEx (and therefore the gate-emitter voltage) can also be set to a specific custom value by
means of external circuitry. The internally controlled 2.5mA DC current at VEx is then drawn/sourced by
external components such as a combination of a resistor with a Zener diode or by a linear regulator. When
realizing deviating voltage levels with external circuitry, several points have to be observed:

The voltage between VISOx and VEx as well as VEx and COMx must not exceed 20V.

The voltage between VISOx and VEx as well as VEx and COMx must not be set to a value which
triggers the under-voltage monitoring (UVLO). For specific values, refer to the respective data sheet
/2/ for the gate driver. The exception is MOSFET mode (see section “MOSFET mode (not available on
2SC0106T and 2SC0108T)”).

It is impermissible to switch VEx to COMx potential when the driver is supplied with power.
If voltage levels that violate the above rules are required, please contact the CONCEPT support service.
Required blocking capacitors C1x and C2x
The SCALE-2 gate drivers are equipped with blocking capacitors on the secondary side of the DC/DC converter
(for values, refer to the corresponding driver data sheet /2/). These blocking capacitors allow fast charging
and discharging of the gate capacitance of power semiconductors (which is characterized by the gate charge)
via the N-channel MOSFET driver stages.
For IGBTs or MOSFETs, a minimum total blocking capacitance of 3µF is recommended for every 1µC of gate
charge, unless otherwise specified in the corresponding application manual /1/. The missing blocking
capacitance on a SCALE-2 driver core must be added externally.
The blocking capacitors must be placed between VISOx and VEx (C1x in Fig. 15) as well as between VEx and
COMx (C2x in Fig. 15). They must be connected as close as possible to the driver’s terminal pins with minimum
inductance. It is recommended to use the same capacitance value for both C1x and C2x (IGBT mode). Ceramic
capacitors with a dielectric strength >20V are recommended. Note that during power-on, the capacitors are
charged with a limited current thanks to the soft start function implemented in the SCALE-2 gate drivers.
www.IGBT-Driver.com
Page 14
AN-1101
Application Note
If the required capacitances C1x or C2x exceed the maximum value given in the corresponding description and
application manual /1/, please contact CONCEPT’s support service.
Note that the use of electrolytic capacitors such as tantalum capacitors is not recommended.
4.7k
29
28
Channel 2
27
26
25
24
23
22
GL2
Rg,off2
GH2
Rg,on2
VISO2
VE2
Gate 2
D52
C12
Emitter 2
COM2
REF2
C22
VCE2
ACL2
Driver
2SC0435T
4.7k
18
17
Channel 1
16
15
14
13
12
11
GL2
Rg,off1
GH2
Rg,on1
VISO2
VE2
D51
C11
Emitter 1
COM2
REF2
Gate 1
C21
VCE2
ACL2
Fig. 15 Use of external blocking capacitors on the secondary side (example with 2SC0435T)
VCEsat detection with SCALE-2 gate driver cores (excluding 2SC0108T)
Desaturation protection with resistors (for 650V-1700V driver cores)
The collector sense must be connected to the IGBT collector or MOSFET drain with the circuit shown in Fig. 16
and Fig. 17 in order to detect an IGBT or MOSFET short-circuit.
During an IGBT off-state, the driver’s internal MOSFET connects pin VCEx to pin COMx. The capacitor Cax is
then pre-charged/discharged to the negative supply voltage, which is about -10V referred to VEx (red circle in
Fig. 16). During this time, a current flows from the collector (blue circle in Fig. 16) via the resistor network and
the diode BAS416 to VISOx. The current is limited by the resistor chain.
It is recommended to dimension the resistor value of Rvcex in order to obtain a current of about IRvcex=0.6-1mA
flowing through Rvcex (e.g. 1.2-1.8MΩ for VDC-LINK=1200V). A high-voltage resistor as well as series-connected
resistors may be used. It must be ensured that the resistors Rvcex are not overloaded in either voltage or
thermal respects:

A maximum temperature increase of 40K or lower is usually recommended in the worst case condition.

The maximum voltage withstand capability of the resistors used must not be exceeded. Moreover, the
minimum creepage distance relating to the application must be considered.
I Rvcex 
(VCEx  VISOx)
RVCEx
Eq. 5
The reference voltage is set by the resistor Rthx. It is calculated via the reference current (typically 150uA) and
the reference resistance Rthx (green circle in Fig. 16)
www.IGBT-Driver.com
Page 15
AN-1101
Application Note
Vrefx  150A  Rthx
Eq. 6
CONCEPT recommends the use of Rthx=68kΩ to detect short-circuits. Lower resistance values make the system
more sensitive and do not provide any advantages in the case of desaturated IGBTs (short-circuit). Note that
the resistor Rthx is already available on some driver cores such as 2SC0106T, 2SC0108T2D0-07, 2SC0108T2D012, 2SC0635T and 1SC0450V.
VISOx
COMx
VCEx
150uA
Vce Monitoring
Cax
ACLx
+
VCEx
-
REFx
0.6...1mA
Rax
BAS416
Rvcex
Fault
Vrefx
VISOx
PWM
Rthx
Vce sat
Rg(on)
GHx
t(us)
Rg(off)
GLx
4.7k
COMx
COMx
VEx
SCALE-2 Driver Core (Part of One Channel Shown)
Fig. 16 VCE desaturation protection with resistors (600V-1700V IGBT modules)
At IGBT turn-on and in the on-state, the above-mentioned MOSFET turns off. While VCE decreases (blue curve
in Fig. 16), Cax is charged from the COMx potential to the IGBT saturation voltage (red curve in Fig. 16). The
time required to charge Cax depends on the DC bus voltage, the value of the resistor Rax and the value of the
capacitor Cax. For 1200V and 1700V IGBTs it is recommended to set Rax=120kΩ. For 600V IGBTs the
recommended value is Rax=62kΩ. The resulting response time is given in the corresponding application
manual /1/. It is valid in the short-circuit condition for a minimum DC-link voltage of about 25V*Rvcex/Rax. Note
that the response time will increase for lower DC link voltages. However, the energy dissipated in the IGBT in
the short-circuit condition generally remains at the same level or is even lower.
The diode D1 in Fig. 17 must have a very low leakage current (in particular at elevated ambient/junction
temperatures) and a blocking voltage >40V (e.g. BAS416). Schottky diodes must be explicitly avoided.
VISOx
SCALE-2
Driver Core
D1
Collector
VCEx
Cax
Rax
Rvcex
COMx
Fig. 17 Recommended circuit for desaturation protection with resistors (600V-1700V IGBT modules)
Note: The related components Cax, Rax, Rthx and D1 must be placed as close as possible to the driver. A large
collector-emitter loop must also be avoided. See the layout proposal of 2BB0435T:
www.igbt-driver.com/go/2BB0435T
www.IGBT-Driver.com
Page 16
AN-1101
Application Note
It is recommended to implement a response time (short-circuit time) which is high enough to avoid false
tripping of the desaturation protection during IGBT turn-on. If the desaturation protection function is set up
with an insufficiently long response time, a fault may be triggered during IGBT turn-on, especially in cases
where the VCE voltage drop time is low (usually at high DC-link voltages, high collector currents and junction
temperatures). The ruggedness of the design can be tested in the following way:

The IGBT must be turned on at the highest DC-link voltages, collector current and junction
temperature (e.g. using the double pulse technique).

If no fault is generated, the sensitivity of the desaturation protection function can be increased by
reducing the capacitance value of Cax and/or reducing the driver supply voltage VDC. This allows the
design margin to be checked.

Alternatively, the turn-on speed of the IGBT module can be artificially reduced by increasing the
turn-on gate resistance to check the design margin.
If the design margin is insufficient, it is recommended to increase the response time. Note, however, that the
maximum allowed short-circuit time of the IGBT module must not be exceeded under the conditions stated in
the data sheet of the IGBT module (if in doubt, please consult the supplier of the IGBT module).
For driver cores of voltage classes higher or equal to 3300V, the recommended circuit for desaturation
protection can be found in the corresponding application manual /1/.
Desaturation protection with sense diodes (only for 650V-1700V driver cores)
SCALE-2 technology also provides desaturation protection with high-voltage diodes as shown in Fig. 18.
However, the use of high-voltage diodes has some disadvantages compared to the use of resistors:

Common-mode current relating to the rate of change dvce/dt of the collector-emitter voltage: Highvoltage diodes have large junction capacitances Cj. These capacitances in combination with the dvce/dt
generate a common-mode current Icom flowing in and out of the measurement circuit.
I com  C j 
dvce
dt
Eq. 7

Price: High-voltage diodes are more expensive than standard 0805/150V or 1206/200V SMD resistors.

Availability: Standard thick-film resistors are comparatively easier to source on the market.

Limited robustness: The reaction time does not increase at lower VCE levels. Consequently, false
triggering may occur at higher IGBT temperatures, higher collector currents, resonant switching or
phase-shift PWM, particularly when the reference voltage Vthx is set lower than about 10V. The upper
limit of the reference voltage is restricted to about 10V, which may lead to limited IGBT utilization: the
collector current may be limited to values smaller than twice the nominal current, or the short-circuit
withstand capability may be reduced.
During the IGBT off-state, D4 (and Rax) sets the VCEx pin to COMx potential, thereby pre-charging/discharging
the capacitor Cax to the negative supply voltage, which is about -10V referred to VEx. At IGBT turn-on, the
capacitor Cax is charged via Rax to 15V. When the IGBT collector-emitter voltage drops below that value, the
voltage of Cax is limited via the high-voltage diodes D1 and D2. The voltage across Cax can be calculated by:
Vcax  VCEsat  VF ( D1)  VF ( D2)  (330 
(15V  VCEsat  VF ( D1)  VF ( D2) )
( Rax  330)
)
Eq. 8
The reference voltage Vrefx needs to be higher than Vcax. It is set up by the resistor Rthx and can be calculated
via the reference current (typically 150uA) and the reference resistance Rthx:
Vrefx  150A  Rthx
Eq. 9
www.IGBT-Driver.com
Page 17
AN-1101
1
Applicatiion Note
Fig. 18 Reecommended
d circuit for desaturation
d
pprotection with
w sense dio
odes
It is recomm
mended to usse standard rectifier diod
des such as 1N4007
1
for D1 and D2 (2 diodes for 1200V IGBTs,, 3
diodes for 1700V IGBT
Ts). D3 and D4 must bee high-speed diodes (e.g
g. BAS316). Schottky diodes must be
b
avoided.
The value o
of the resista
ance Rax can be calculateed with the following
f
equ
uation in ordder to progra
am the desire
ed
response tim
me Tax at turrn-on:
Rax [k] ≈
1000  Tax [ s]
15V  VGLLx
Cax [ pF ]  lnn(
)
15V  Vrefxfx
Eq. 10
1
VGLx is the a
absolute valu
ue of the turn
n-off voltagee at the drive
er output. It depends
d
on the driver load and can be
b
found in the
e driver data sheet /2/.
Recommend
ded high-volttage diodes D1/D2 and vaalues for Rax and Cax are:

High-voltage dio
odes:

=24kΩ…62kΩ
Ω
Rax=

Cax=
=100pF…560
0pF
1x 1N4007
1
for 6
650V IGBTs
2x 1N4007
1
for 1
1200V IGBTs
3x 1N4007
1
for 1
1700V IGBTs
Note that Caax must inclu
ude the parassitic capacitaance of the PCB and the diode
d
D3.
Note also tthat the insttantaneous VCE threshold
d voltage iss determined
d by the volltage at pin REFx (150μ
μA
through Rthxx) minus the voltage acro
oss the 330Ω
Ω resistor as well
w as the fo
orward voltaages across D1 and D2.
Note that th
he minimum
m off-state du
uration shou
uld not be sh
horter than about
a
1µs inn order not to
t significanttly
reduce the response tim
me for the ne
ext turn-on p ulse.
m
be used
d to define a response time of 6μs w
with Cax=150pF, Rthx=33kkΩ
Example: A resistor of Rax≈46kΩ must
a
and VGLx=9V
V.
It is recommended to implement a response ttime (short-ccircuit time) which is hiigh enough to avoid false
ation protecttion during I GBT turn-on
n. If the desa
aturation prootection funcction is set up
u
tripping of tthe desatura
with an insufficiently lo
ong response
e time, a fau
ult may be triggered
t
during IGBT tuurn-on, espe
ecially in cases
d
time is low (usuallyy at high DC-link voltages, high colleector currents and junctio
on
where the VCE voltage drop
temperature
es). The rugg
gedness of the design caan be tested in the follow
wing way:

T
The IGBT must
m
be turn
ned on at tthe highest DC-link volttages, collecctor current and junctio
on
te
emperature (e.g.
(
using th
he double pu
ulse techniqu
ue).

Iff no fault is generated, the
t sensitivitty of the dessaturation prrotection funnction can be
e increased by
b
re
educing the capacitance
c
value of Cax and/or reducing the driv
ver supply vooltage VDC. This
T
allows th
he
design margin
n to be check
ked.
www.IGBT-Driver.com
Page
e 18
AN-1101
Application Note

Alternatively, the turn-on speed on the IGBT module can be artificially reduced by increasing the
turn-on gate resistance to check the design margin.
If the design margin is insufficient, it is recommended to increase the response time. Note, however, that the
maximum allowed short-circuit time of the IGBT module must not be exceeded under the conditions stated in
the data sheet of the IGBT module (if in doubt, please consult the supplier of the IGBT module).
Note that no desaturation protection circuit with sense diodes is recommended for driver cores of voltage
classes higher or equal to 3300V.
Disable VCEsat detection by SCALE-2 (excluding 2SC0106T and 2SC0108T)
To disable the VCEsat measurement of gate driver cores, a resistor with a minimum value of 1kΩ needs to be
placed between VCEx and COMx.
The reference resistor Rthx (if available) may be chosen between 33kΩ and infinity, i.e. the REFx pin may be
left open.
4.7k
29
28
Channel 2
27
26
25
24
23
22
Rg,off2
GL2
GH2
Rg,on2
VISO2
VE2
COM2
REF2
Gate 2
D52
C12
Emitter 2
C22
D32
Rth2
VCE2
Collector 2
ACL2
20
Driver
Racl2
2SC0435T
D12
D22
Cacl2
4.7k
18
17
Channel 1
D42
1k
16
15
14
13
12
11
Rg,off1
GL1
GH1
Rg,on1
VISO1
VE1
COM1
REF1
Gate 1
D51
C11
Emitter 1
C21
D31
Rth1
D41
1k
VCE1
Collector 1
ACL1
20
Racl1
D11
D21
Cacl1
Fig. 19 Disabling the VCEsat detection by SCALE-2 driver cores (example with 2SC0435T)
www.IGBT-Driver.com
Page 19
AN-1101
Application Note
Disabling the Advanced Active Clamping
To disable the active clamping function, the ACLx input needs to be left open. Refer to the corresponding
application manual /1/.
4.7k
29
28
27
Channel 2
26
25
24
23
22
Rg,off2
GL2
GH2
Rg,on2
VISO2
D52
C12
VE2
Emitter 2
C22
COM2
REF2
Gate 2
Rth2
D62
Ca2
VCE2
120k
Rvce2
Collector 2
ACL2 N.C.
Driver
2SC0435T
4.7k
18
17
16
Channel 1
15
14
13
12
11
Rg,off1
GL1
GH1
Rg,on1
VISO1
D51
C11
VE1
Emitter 1
C21
COM1
REF1
Gate 1
Rth1
VCE1
D61
Ca1
120k
Rvce1
Collector 1
ACL1 N.C.
Fig. 20 Disabling Advanced Active Clamping by SCALE-2 (example with 2SC0435T)
Rail-to-rail output and gate voltage clamping
CONCEPT SCALE-2 gate drivers use an N-channel output stage like that shown in Fig. 21. After charging the
power semiconductor gate input, the voltage drop over the N-channel MOSFET is nearly zero. SCALE-2 drivers
therefore feature rail-to-rail gate outputs.
A rail-to-rail output has several advantages in driving power semiconductors. The first one is that the VISOx
voltage can be regulated to 15V. By using a Schottky diode (D5 in Fig. 21), the gate voltage is clamped to the
regulated 15V. This avoids an increase of the external gate-emitter voltage and consequently lowers the IGBT
short-circuit current ISC and energy, as the former is highly dependent on the gate-emitter voltage VGE:
I SC  f (VGE )
Eq. 11
The gate clamping described here is much more efficient than gate-emitter clamping with transient voltage
suppressors. The latter does not allow the gate-emitter voltage to be limited in the short-circuit condition to
15V, as some clamping voltage reserve must be applied in view of the component tolerances and temperature
dependence in order to avoid static conduction and therefore overload at VGE=15V.
A second advantage is that parasitic power semiconductor turn-on can be prevented when the gate driver
power is off. In that case, the gate-emitter voltage on the power semiconductor is zero. If the collector-emitter
voltage VCE increases at a given dVCE/dt, a current Ig will flow in the gate loop via the Miller capacitance CMiller:
I g  C Miller 
dVCE
dt
www.IGBT-Driver.com
Eq. 12
Page 20
AN-1101
Application Note
With the use of D5 in Fig. 21 the current Ig will charge the blocking capacitors C12 and C22. The voltage over
C12 and C22 will generally remain low. A parasitic turn-on of the power semiconductors is therefore not
possible. This function can be also used for STO (Safe Torque Operation).
Driver
2SC0435T
Channel 2
VISO
Power Supply
Monitoring
Vce Monitoring
Advanced
Active Clamping
COM
IN
24
VCE
23
22
ACL
27
VISO
Transformer
Interface
Predriver
VE Control
VCE2
ACL2
VISO2
Turn-on
N-channel
MOSFET
AUX
Bootstrap
Charge Pump
REF2
D5
GH
28
GL
29
Predriver
GH2
GL2
Rg(on)
Rg(off)
Turn-off
N-channel
MOSFET
AUX
COM
25
C22
C12
VE
26
COM2
VE2
SCALE-2 IGD
Fig. 21 Rail-to-Rail output and gate clamping (example with 2SC0435T)
Note that the gate clamping described here is not possible on 2SC0108T drivers since VISOx is not available
externally. Gate-emitter clamping with transient voltage suppressors should be used instead.
MOSFET mode (not available on 2SC0106T and 2SC0108T)
In IGBT mode, the positive turn-on gate voltage is regulated to 15V and the turn-off gate voltage is negative;
typically about -10V for SCALE-2 gate driver cores.
With the MOSFET mode, it is possible to set the turn-off gate voltage to 0V.
It is recommended to proceed in the following way to activate the MOSFET mode on SCALE-2 driver cores:
1) Connect the secondary-side terminals COMx and VEx together. This must be performed with the driver
power supply turned off. Otherwise the secondary ASIC IGD may be damaged. The blocking capacitor
C12 on Fig. 21 may be used if required. The blocking capacitors C22 of Fig. 21 are no longer required as
they are short-circuited.
2) Select the required gate-emitter voltage at turn-on. The primary-side supply voltage VCC still needs to
be 15V. The secondary-side supply voltage VISOx to COMx can be adjusted from 10V to 20V with VDC
(exceptions: 2SC0535T and 2SC0635T, see the corresponding application manual /1/). This
corresponds to the gate turn-on voltage. The transfer ratio from VDC to VISOx-COMx is typically 1.67.
The under-voltage lock-out on the secondary side changes from 12.6V in IGBT mode to 8.75V in
MOSFET mode (typical value). A VDC voltage lower than about 5.2V typically produces an undervoltage fault in MOSFET mode. As an example, VDC=6V typically leads to a positive gate turn-on
voltage of 10V. Note, however, that this value is dependent on the driver output power and the
temperature.
3) The reference voltage Vth for VCE monitoring (to be programmed with Rthx) must be set at values
higher than or equal to 4V referred to COMx.
www.IGBT-Driver.com
Page 21
AN-1101
Application Note
+6V...+12V
4.7k
+15V
R1
VDC
SO1
Fault
SO2
MOD
TB
RB
VCC
GND
INA
PWM
INB
GND
GND
29
1
Channel 2
28
2
27
3
26
4
25
5
6
Driver 2SC0650P
7
Driver
2SC0650P
24
23
22
Rg,off2
GL2
GH2
Rg,on2
VISO2
VE2
Gate 1
D52
C21
Source 1
D62
COM2
REF2
Rth2
VCE2
Ca2
120k
Rvce2 Drain 1
ACL2
8
9
10
Fig. 22 MOSFET mode (example with 2SC0650P)
Note that the MOSFET mode has been designed for ultra-fast MOSFET switching. The switching delays can
thus be reduced to a minimum. A single positive turn-on voltage is then necessary.
MOSFETs have low gate-source threshold voltages. The use of MOSFET mode is consequently not always
recommended and depends on the application. The IGBT mode can be used to drive MOSFETs and avoid their
parasitic turn-on thanks to the negative gate-source voltage in the off-state.
Paralleling a dual-channel driver to a single output (not available on 2SC0106T)
Dual-channel driver cores can be configured to a single driver core with the double output power and gate
current (exception 2SC0106T).
It is recommended to proceed in the following way and as shown in Fig. 23 to merge both driver channels to
one logical channel (excluding 2SC0108T):

Direct mode must be selected (MOD pin pulled to GND).

Both input signals INA and INB must be connected together.

Both secondary-side emitter potentials VE1 and VE2 must be connected together.

It is recommended to disable the desaturation protection for one channel while it is enabled on the
other channel.

If available, the reference value Vth2 is set up to 10V with Rth2=68kΩ.

Both channels need gate resistors to decouple the driver output stages. The driver channels are
connected together on the IGBT gate side of the gate resistors. The turn-on and turn-off gate
resistors need to be the same for both channels with a tolerance value of ≤5% (1% recommended).

The active clamping controls the turn-off driver stages in the driver core at turn-off. Each of the
Advanced Active Clamping pins ACLx of both channels must therefore be connected to a 20Ω resistor
according to Fig. 23 (The 20 resistors as well as D3x must be omitted on 2SC0635T, as these
components are already available on the driver core).

Both fault signals SO1 and SO2 can be connected to a single fault signal SO.

As soon as a fault is detected at SO, the PWM input signal must be pulled to GND in order to turn-off
any driver channel that may not already be turned off. Omitting this point could lead to thermal
damage to the driver, as one driver channel is turned off in the fault condition and the other remains
turned on, leading to high power losses in the driver. The PWM input should not be activated before
the SO fault signal is high again, i.e. no fault signal is available. This is important in order to avoid only
one channel switching, as the blocking time of both driver channels is not exactly the same. Additional
restrictions may apply when using 2SC0635T if the CSHDx pin is used (see the corresponding
application manual /1/).
www.IGBT-Driver.com
Page 22
AN-1101
1
Applicatiion Note
4.7k
29
28
Chann
nel 2
+15V
R1
SO2
MOD
TB
RB
VCC
GND
INA
PWM
INB
GND
GND
26
25
VDC
SO1
SO
27
1
24
2
23
22
3
4
5
Rg,off2
GL2
GH2
C12
VE2
C22
COM2
REF2
2
D52
Rg,on2
O2
VISO
D62
D32
68k
Ca2
2
VCE2
120k
Rvce2
Collector 1
ACL2
2
20
Racl2
Driver
2SC0435T
4.7k
7
18
9
10
17
Chann
nel 1
D2
22
Cacl2
6
8
D12
16
15
14
13
12
11
GL1
Rg,off1
GH1
Rg,on1
O1
VISO
Gate 1
D51
C11
VE1
Emitter 1
C21
COM1
REF1
1
D42
Rth1
D
D31
1k
1
VCE1
ACL1
1
20
Fig. 23 Paaralleling a du
ual-channel driver
d
to a sin
ingle output (example
(
wit
ith 2SC0435TT)
Paralleling tthe two gate
e driver chan
nnels on 2SC
C0108T is similar to the procedure ffor all other SCALE-2 ga
ate
driver coress. The main difference
d
is that no Advaanced Active
e Clamping iss available. Iff (basic) active clamping is
used, the trransient volta
age suppresssor chain is cconnected dirrectly to the gate (see Figg. 24).
Fig. 24 Paaralleling both
h driver chan
nnels of 2SC0
C0108T
Note that th
he two gate driver
d
channels of 2SC01
106T cannot be run in parallel.
Disabling
g one cha
annel for chopper
c
a
applicatio
ons
In some casses, a single
e gate driver is required, such as for chopper ope
eration, e.g. a break cho
opper in a DClink bus. A single gate driver is no
ot always avvailable or commercially
c
ations. A dua
alviable for ssuch applica
e can therefo
ore be used w
where one ch
hannel has to
o be disabledd.
channel gatte driver core
It is recomm
mended to prroceed in the
e following w
way to disable
e one driver channel:

The
e corresponding signal input INx musst be pulled to GND.

The
e fault feedba
ack SOx can be left open
n.

Dire
ect mode (if available) must be selectted (MOD pin
n pulled to GND).
G

The
e secondary side
s
of the channel can b
be left open (not connectted).
www.IGBT-Driver.com
Page
e 23
AN-1101
Application Note
Position of the Gate Driver in the Converter
The temperature as well as both magnetic and electric fields can influence the functionality of the signal
electronics. Choosing the right position for the gate driver in the power electronics system helps to prevent
system dysfunction and EMI effects.
CONCEPT SCALE-2 gate drivers are generally designed for ambient temperatures of up to 85°C. Excessive
temperatures mainly limit the DC/DC power. In the worst case, the DC/DC transformer core goes into
saturation and the gate driver core is destroyed. In converters where the gate driver is placed close to the
heat sink or the power semiconductors, it is important to check that the maximum permissible temperature
around the driver is not exceeded.
Furthermore, high currents generate high magnetic fields and high voltages generate high electric fields.
Combined with high switching speeds, these fields represent a harsh environment for the signal electronics
available on the gate drivers. This point is further detailed below.
Driver placement on top of 17mm IGBT modules or close to high magnetic
fields
17mm IGBT modules are becoming increasingly popular in power electronics applications. Manufacturers like
Danfoss Silicon Power, Fuji, Infineon, IXYS, Mitsubishi and Semikron offer a range of 17mm packages on the
market.
It is not recommended to use most of the SCALE-2 driver cores (exceptions see below) directly on top of IGBT
modules, and especially not on top of 17mm IGBT modules. Magnetic field coupling during turn-on and turnoff events and especially during IGBT short circuit can lead to malfunction of the driver.
Some SCALE-2 driver cores have been optimized to work in environments with high magnetic fields. They can
be used directly on top of IGBT modules without problems. These drivers are:

2SC0106T – the entire driver family

2SC0108T2D0-07 and 2SC0108T2D0-12

2SC0435T2F0-17

2SC0650P – the entire driver family

1SC2060P – the entire driver family

1SC0450V – the entire driver family
AC and DC bus bar
Laminated DC bus bars generally produce low external magnetic and electric fields due to their laminated
structure. A gate driver can therefore be located on top or underneath the DC bus as long the insulation or the
clearances are sufficient.
However, the situation concerning the AC or phase leg bus bar is different. The output current generates a
magnetic field around the bus bar and the rate of change of the electric field is generally high. If the gate
driver is placed directly underneath or above the AC bus bar, shielding may be necessary. This can be an iron
plate (shielding for low frequencies) or a thick aluminum or copper plate (shielding for high frequencies). The
eddy current flowing in the shield will partially compensate for the magnetic field generated near the gate
driver.
However, it is usually recommended to maintain a minimum distance (several cm are generally sufficient)
between the AC bus bar and the gate driver core to reduce the effect of the magnetic field on the driver.
www.IGBT-Driver.com
Page 24
AN-1101
Application Note
Generally speaking, the closer the conducting current and the signal electronics are to each other, the higher
is the risk of electromagnetic influences.
PCB Layout
SCALE-2 driver cores are sophisticated products that require properly designed PCB layouts in order to work
efficiently and to deliver full performance. Stripboards (“Veroboards”) must therefore not be used together
with SCALE-2 driver cores. It is usually recommended to use 4-layer PCBs. Two-layer PCBs may also be used,
but the performance and/or flexibility are then reduced.
PCB thickness
CONCEPT recommends using a PCB thickness of 1.55mm or higher. The typical pin length of 2.54mm of many
of the SCALE-2 driver cores has been optimized for the use of 1.55mm PCB thickness.
It is recommended to use drivers with longer pins when using PCB thicknesses of 2mm or higher to avoid
soldering problems during production. The following drivers have long pins (5.84mm):

2SC0108T2C0-17, 2SC0108T2F0-17

2SC0435T2C0-17, 2SC0435T2E0-17, 2SC0435T2F0-17

2SC0650P2C0-17

1SC2060P2A0-17

2SC0535T2A0-33

2SC0635T2A0-45

1SC0450V2A0-45, 1SC0450V2A0-65
Separation of areas with different high-voltage potentials
One important rule for PCBs designed for power electronics applications is that layers relating to different
high-voltage potentials must never overlap as shown in Fig. 25. If this is omitted, large coupling capacitances
between the different high-voltage potentials will result, leading to excessive common-mode current Icom on
the PCB during switching operation. Moreover, the long-term isolation reliability may become problematic.
GND Plain
Bottom Layer
Driver Core
VE1 Plain
Bottom Layer
VE2 Plain
Bottom Layer
GND Plain
Bottom Layer
GND Plain
Bottom Layer
Driver Core
VE1 Plain
Bottom Layer
VE2 Plain
Top Layer
Driver Core
VE1 Plain
Top Layer
VE2 Plain
Bottom Layer
Fig. 25 PCB layout of SCALE-2 driver adapter boards
www.IGBT-Driver.com
Page 25
AN-1101
Application Note
Equations 13 and 14 describe how to calculate common-mode currents Icom relating to overlapping plains in
different PCB layers during IGBT commutation with a rate of change of the collector-emitter voltage of
dVCE/dt:
C PCB   0   r 
A
l
Eq. 13
A is the area where high-voltage potentials overlap, l is the distance between both PCB layers, εr=5, and
ε0=8.85pF/m.
I com  C PCB 
dVce
dt
Eq. 14
Not only planes (e.g. ground or emitter potentials) are affected by these rules. All other signal lines with large
switching potential differences must also satisfy this rule. A high-side collector potential must therefore – as an
example – never cross a low-side gate signal on the PCB layout.
It is mandatory to implement sufficient clearance and creepage distances as required by the corresponding
standards (see also section “Clearance and creepage distances for PCBs ”).
Use of planes
It is highly recommended to use planes to distribute constant potentials (especially power supplies and
ground) efficiently over the corresponding PCB areas. Additionally, the planes act as magnetic shielding and
strongly reduce the influence of external magnetic fields if they are properly designed.
The layers can be used in the following way (example):
Driver primary side

Top Layer:
Components, cooling surface and traces

Mid Layer 1:
VCC

Mid Layer 2:
VDC

Bottom Layer: GND, cooling surface and test points
Driver secondary side(s)

Top Layer:
Components, cooling surface and traces

Mid Layer 1:
Emitter or VISO

Mid Layer 2:
VISO or emitter

Bottom Layer: COM, cooling surface and test points
Several planes with different potentials (example emitter and COM) may naturally also be located on the same
layer, if required. Additional planes with other stable potentials, if available (5V, -15V, …), may also be
established.
On the other hand, it is impermissible to build planes with changing potentials, as such planes will generate
coupling capacitances leading to corresponding current flows when potentials are changing. It is also
impermissible to locate planes over areas with changing high-voltage potentials: the complete resistor chain of
the desaturation protection function as well as all TVS for Advanced Active Clamping must always remain free
from planes.
www.IGBT-Driver.com
Page 26
AN-1101
Application Note
Clearance and creepage distances for PCBs
Tab. 1 gives an overview of the required clearance and creepage distances for several IGBT voltage classes.
Several widely used standards are considered. The listed data assumes Pollution Degree 2 (PD2), Overvoltage
Category II (OV II) and standard FR4 PCB material of material category IIIa.
Note that the working voltages given in Tab. 1 do not necessarily correspond those used to design the
corresponding driver cores. Please check the creepage distances given in the specific data sheets /2/.
Voltage
class of
power
module
(VCES)
Standard
System
voltage
Working
voltage
Max.
altitude
of
operation
Impulse
voltage for
functional
insulation
Impulse
voltage for
reinforced
insulation
Min.
clearance
distance
for
functional
insulation
Min.
clearance
distance
for
reinforced
insulation
Min.
creepage
distance for
functional
insulation1)
Min.
creepage
distance for
reinforced
insulation1)
600V
EN 50178
1997-07
424VRMS
400VDC
2000m
460VRMS
400VDC
3121V
4994V
2.1mm
4.2mm
2.1mm
4.2mm
3298V
5277V
2.3mm
4.6mm
2.3mm
1200V
849VRMS
800VDC
4.6mm
5243V
8388V
4.6mm
8.7mm
4.6mm
1700V
1202VRMS
8.7mm
1200VDC
6808V
10893V
6.5mm
12.3mm
6.5mm
3300V
12.3mm
2333VRMS
2500VDC
11334V
18134V
13.0mm
22.8mm
13.0mm
25.0mm
4500V
3182VRMS
3400VDC
14667V
23468V
18.0mm
30.9mm
18.0mm
34.0mm
6500V
4596VRMS
4500VDC
19853V
31764V
25.5mm
45.5mm
25.5mm
45.5mm
424VRMS
400VDC
4000V
6400V
3.0mm
8.0mm
4.0mm
8.0mm2)
650V
600V
IEC 60077-1
Ed. 1
1999-10
1400m
460VRMS
400VDC
4000V
6400V
3.0mm
8.0mm
4.0mm
8.0mm2)
849VRMS
800VDC
5000V
8000V
4.0mm
8.0mm
8.0mm
8.0mm2)
1700V
1202VRMS
1000VDC
8000V
12800V
8.0mm
18.0mm
10.0mm
18.0mm2)
3300V
N.a.3)
4500V
N.a.3)
650V
1200V
N.a.3)
6500V
600V
424VRMS
400VDC
4000V
6000V
3.0mm
5.5mm
3.0mm
5.5mm
460VRMS
400VDC
4000V
6000V
3.0mm
5.5mm
3.0mm
5.5mm
849VRMS
800VDC
6000V
8000V
5.5mm
8.0mm
5.5mm
8.0mm
1700V
1000VRMS
1000VDC
6000V
8000V
5.5mm
8.0mm
5.5mm
10.0mm
3300V
N.a.3)
4500V
N.a.3)
650V
1200V
IEC 60664-1
Ed. 2
2007-04
N.a.3)
6500V
600V
2000m
424VRMS
400VDC
4000V
6000V
3.0mm
5.5mm
3.0mm
5.5mm
460VRMS
400VDC
4000V
6000V
3.0mm
5.5mm
3.0mm
5.5mm
849VRMS
800VDC
6000V
8000V
5.5mm
8.0mm
5.5mm
8.0mm
1700V
1202VRMS
1200VDC
6777V
10844V
6.5mm
12.3mm
6.5mm
12.3mm
3300V
2333VRMS
2500VDC
11129V
17806V
12.7mm
22.0mm
25.0mm
50.0mm
4500V
3182VRMS
3400VDC
14392V
23028V
17.3mm
30.3mm
34.0mm
68.0mm
6500V
4596VRMS
4500VDC
19597V
31356V
24.5mm
44.9mm
45.0mm
90.0mm
650V
1200V
IEC 61800-5-1
Ed. 2
2007-07
2000m
1) If the determined creepage distance is smaller than the respective clearance distance for functional or reinforced insulation, the clearance distance will be chosen for this
particular creepage distance for safety reasons.
2) IEC 60077-1 does not distinguish between functional and reinforced insulation with respect to the creepage distances. The value of the functional insulation is therefore used for
reinforced insulation as long as the respective clearance distance for reinforced insulation is not higher (see also previous footnote).
3) N.a.: Not applicable
Tab. 1 Summary of required creepage and clearance distances according to several standards
Gate driver cores in applications at higher altitudes
The creepage and clearance distances of CONCEPT gate driver cores are determined according to specific
standards (see product documentation /1/, /2/), which indicate a maximum altitude of operation (see also
Tab. 1).
For use of the drivers at higher altitudes, correction factors for the clearances are usually given in the
standards and must be considered.
For example, for an IGBT power module in a voltage class of 1700V, the maximum altitude for a 2SC0108T
driver is 2000m. If the application operates at higher altitudes and the corresponding standards must be
satisfied, the maximum permissible system voltage must be reduced, or else the next larger CONCEPT IGBT
www.IGBT-Driver.com
Page 27
AN-1101
1
Applicatiion Note
gate driver is required. Thus, 2SC0435T driverss can operatte according to the standdards up to an altitude of
2900m.
eglect of the
ese requireme
ents can lead
d to destructtion of the IG
GBT drivers aand IGBT mo
odules.
Note that ne
CONCEPT
T base bo
oards
CONCEPT h
has develope
ed the follow
wing base bo
oards to show
w how corre
ect layouts foor the driverr cores can be
b
realized:
T (see www.igbt-driver.co
om/go/2BB0
0108T)
2BB0108T ffor 2SC0108T
2BB0435T ffor 2SC0435T
T (see www.igbt-driver.co
om/go/2BB0
0435T)
2BB0535T ffor 2SC0535T
T (see www.igbt-driver.co
om/go/2BB0
0535T)
Schematics,, BOM and evven the Gerb
ber files of th
he layouts arre available on
o the specifified Internet pages.
Fig. 26 and Fig. 27 show
w examples of
o base board
d layouts.
Fig. 26 PC
CB layout of CONCEPT
C
ba
ase board 2BB
BB0108T
Fig. 27 PC
CB layout of CONCEPT
C
ba
ase board 2BB
BB0435T
www.IGBT-Driver.com
Page
e 28
AN-1101
Application Note
Typical Application Failures
Impact on the
driver
Effect
Primary-side
DC/DC MOSFET
destroyed or LDI
ASIC destroyed
(2SC0108T)
DC/DC overload
Cause
 Excessive switching frequency
 High noise on INA or INB
 Partial discharge
 Short circuit in gate, emitter,
VEx, VISOx or COMx
 Use of oversized gate/emitter
capacitor CGE
 Excessive gate charge Qg
 LC gate oscillation
 Excessively high ambient
temperature
 Defective ceramic capacitor
 VDD>16V
 Pull-up resistor value at SOx
too small
 ESD handling
 Max. isolation voltage of
1700V exceeded
LDI ASIC
destroyed
IGD ASIC
destroyed
IGD ASIC
destroyed
Short circuit with
destruction of LDI,
IGD or DC/DC
MOSFET
Delay divergence
of gate signals
between parallel
connected IGBTs
(>25ns) or jitter
>5ns
Excessive
Advanced
Active Clamping
feedback
(>3µs)
 Excessive DC-link voltage
 Excessive stray inductances
 VISOx > 30V
Crack of
ceramic
capacitors
Increased initial
propagation
delay
www.IGBT-Driver.com
Corrective Action
 Select next powerful gate driver
or reduce switching frequency
 EMI protection e.g. minimum
pulse suppression
 Mostly PCB layout failure; check
all clearance and creepage
distances
 Assembly or layout failure
 Calculate the power losses for
CGE
 Calculate the power losses for
Qg
 Remove excessive inductance
in the gate loop
 Reduce the ambient
temperature below 85°C
 Avoid mechanical damage by
handling process or bending of
PCB
 Limit VDD to 16V
 Increase the resistor value
 Improve ESD handling
 Reduce VCE overvoltage e.g.
with active clamping or change
to a higher IGBT blocking
voltage
 Overall design failure, change
to higher IGBT blocking voltage
 Improve the DC bus bar
(reduced stray inductance); do
not apply current >40mA
(mean value) to the ACLx pin
 Limit VDC to 16V
 Handling process, mechanical  Careful mechanical handling
destruction; can also happen
and assembly process
in final mechanical assembly
process
 Use of half-bridge mode
 Use of direct mode
 Slow rise and fall times applied  Insert Schmitt-trigger gates to
to driver inputs
INA/INB
Page 29
AN-1101
Application Note
Bibliography
/1/
Description and Application Manual of SCALE™-2 driver cores, CONCEPT
/2/
Data sheets of SCALE™-2 driver cores, CONCEPT
/3/
Application Note AN-0901: Methodology for Controlling Multi-Level Converter Topologies with
SCALE™-2 IGBT Drivers, CONCEPT
/4/
Application Note AN-0904: Direct Paralleling of SCALE™-2 Gate Driver Cores, CONCEPT
/5/
Paper: Safe Driving of Multi-Level Converters Using Sophisticated Gate Driver Technology, PCIM Asia,
June 2013
Note: The Application Notes are available on the Internet at www.igbt-driver.com/go/app-note and the
papers at www.IGBT-Driver.com/go/paper
Legal Disclaimer
The statements, technical information and recommendations contained herein are believed to be accurate as
of the date hereof. All parameters, numbers, values and other technical data included in the technical
information were calculated and determined to our best knowledge in accordance with the relevant technical
norms (if any). They may base on assumptions or operational conditions that do not necessarily apply in
general. We exclude any representation or warranty, express or implied, in relation to the accuracy or
completeness of the statements, technical information and recommendations contained herein. No
responsibility is accepted for the accuracy or sufficiency of any of the statements, technical information,
recommendations or opinions communicated and any liability for any direct, indirect or consequential loss or
damage suffered by any person arising therefrom is expressly disclaimed.
Manufacturer
CT-Concept Technologie GmbH
A Power Integrations Company
Johann-Renfer-Strasse 15
2504 Biel-Bienne
Switzerland
Phone
Fax
+41 - 32 - 344 47 47
+41 - 32 - 344 47 40
E-mail
Internet
[email protected]
www.IGBT-Driver.com
 2011…2013 CT-Concept Technologie GmbH - Switzerland.
We reserve the right to make any technical modifications without prior notice.
www.IGBT-Driver.com
All rights reserved.
Version 2.0 from 2013-09-20
Page 30
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