isl71830seh see test report

Test Report 016
Single Event Effects (SEE) Testing of the ISL71830SEH
5V 16:1 Multiplexer
Introduction
SEE Test Objectives
The intense proton and heavy ion environment encountered in
space applications can cause a variety of Single Event Effects
(SEE) in electronic circuitry, including Single Event Upset (SEU),
Single Event Transient (SET), Single Event Functional Interrupt
(SEFI), Single Event Burnout (SEB) and Single Event Gate
Rupture (SEGR). SEE can lead to system-level performance
issues including disruption, degradation, and destruction. For
predictable and reliable space system operation, individual
electronic components should be characterized to determine
their SEE response. This report discusses the results of SEE
testing performed on the ISL71830SEH 16:1 analog
multiplexer product for space applications.
The ISL71830SEH was tested to determine its susceptibility to
single event burnout and gate rupture (SEB as used here refers
to either destructive ion effect) and to characterize its single
event transient (SET) behavior. The SEB testing looked
operating voltages at an LET of 60MeV*cm2/mg that bounded
a safe operating region. The SET testing looked for LET that
have sufficient energy to generate an SET of a small size
(±20mV) on the output of the multiplexer. Testing was
performed on samples from the lot J69526.1 manufactured in
Intersil’s proprietary P6SOI process.
Product Description
Testing was performed at the Texas A&M University (TAMU)
Cyclotron Institute heavy ion facility. This facility is coupled to a
K500 super-conducting cyclotron, which is capable of
generating a wide range of test particles with the various
energy, flux and fluence levels needed for advanced radiation
testing. Details on the test facility can be found on the TAMU
Cyclotron website (http://cyclotron.tamu.edu/). Testing was
carried out on December 15th and 16th of 2014 and March
20th of 2015.
The ISL71830SEH discussed here is a 5V, 16:1 analog
multiplexer fabricated in Intersil’s proprietary P6SOI process.
This product was designed with both Total Ionizing Dose (TID)
and SEE in mind and has unique design provisions for
mitigating effects of both radiation sources. The ISL71831SEH
is a 32:1 multiplexer built of the same circuit blocks as the
ISL71830SEH and is considered a circuit extension of the
ISL71830SEH but is reported on separately.
Product Documentation
ISL71830SEH datasheet
Standard Microcircuit Drawing (SMD): 5962-15247
September 21, 2015
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SEE Test Facility
SEE Test Set-up
SEE testing was carried out with the sample in an active
configuration. A schematic of the ISL7830SEH SEE test fixture
is shown in Figure 1. The test circuit configuration was set to
address input 13 which, was consequently routed to the
output. Switch 1 (SW1) allowed addressing to be selected
between rail biasing (SW1 open) or logic threshold biasing
(SW1 closed). The inputs were broken into three groupings
(inputs 1 to 8 were tied to GND, input 13, and inputs 9 to 12
combined with inputs 14 to 16 and were tied to supply V+). The
splitting of the inputs into GND and V+ allowed for bidirectional
biasing of the unselected inputs
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Test Report 016
V+
IS
V+
1
28
OUT
NC
2
27
NC
NC
3
26
IN 8
IN 16
4
25
IN 7
IN 15
5
24
IN 6
IN 14
6
23
IN 5
IN 13
7
22
IN 4
IN 12
8
21
IN 3
IN 11
9
20
IN 2
IN 10
10
19
IN 1
IN 9
11
18
ENABLE
GND
12
17
ADDR A0
VREF
13
16
ADDR A1
ADDR A3
14
15
ADDR A2
VOUT
10k
VIN13
IIN13
10k
VREF
IREF
1k
SW1
1.33k
70% VREF with SW1 closed, VREF when open
30% VREF with SW1 closed, GND when open
1k
With SW1 closed the address lines are set to 30% and 70% of VREF, the logic thresholds for minimum noise
margin. With SW1 OPEN the address lines are set to VREF and GND for maximum noise margin. VOUT is set
to be ½ VIN13 by the two series 10kΩ resistors.
FIGURE 1. SCHEMATIC OF THE ISL71830SEH SEE TEST CIRCUIT
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Test Report 016
SEB Testing of the ISL71830SEH
The first set of SEB (destructive SEE) testing was carried out as
summarized in Table 1. The output voltage along with the supply
and reference currents were monitored for changes indicative of
damage to the part. Four parts were tested in pairs through the
condition sequence of increasing supply and input voltages. This
SEB testing was done with Pr at 10° incidence for an effective
surface LET = 60MeV*cm2/mg. The Pr ions have a range into
silicon of 110µm with a Bragg range of 37µm. This puts the LET
Bragg peak well below the active device region and into the
handle wafer of the SOI. Each irradiation was to an effective
fluence of 5x106 ions/cm2 with a case temperature of +125°C
±10°.
Significant changes in readings over the irradiations are
indicated by shaded entry cells in Table 1. The SEB data indicates
that ISL71830SEH at an LET = 60MeV*cm2/mg did not suffer
damage at supply and input voltage of 6.5V. DUT 4 did see a 12%
increase in supply current at 6.5V, but this was not considered
indicative a damage as the other increases noted constituted
much larger increases. Catastrophic damage was noted on DUT2
at 6.75V but not on the other units at 6.75V and 7.0V. Safe
operating range is so limited to 6.5V at an
LET = 60MeV*cm2/mg.
TABLE 1. ISL71830SEH SEB MONITOR PARAMETER TEST RESULTS (Note 1)
SEB TESTS AT LET = 60MeV*cm2/mg
VOUT (1%)
IS (10%)
IVREF (10%)
V+
(V)
VREF
(V)
VIN13
(V)
APPROX.
VOUT (V)
PRE
(V)
POST
(V)
PRE
(nA)
POST
(nA)
PRE
(nA)
POST
(nA)
6.50
6.50
6.50
3.250
3.243
3.241
1323
1316
25
25
DUT 2
3.238
3.238
94.9
99
22
23
DUT 3
3.239
3.238
1708
1731
28
29
DUT 4
3.238
3.238
1995
2240
34
34
3.366
3.366
1463
1457
26
26
DUT 2
3.364
3.366
97
124µA
24
24
DUT 3
3.364
3.364
1918
1898
30
31
DUT 4
3.364
3.364
2490
2450
36
36
3.491
3.491
1603
1590
28
38
DUT 2
3.490
3.490
212µA
199µA
25
25
DUT 3
3.489
3.488
2100
2111
32
33
DUT 4
3.488
3.488
2700
2730
37
38
DUT 1
DUT 1
DUT 1
6.75
7.00
6.75
7.00
6.75
7.00
3.375
3.500
NOTE:
1. Samples were tested in pairs (DUT 1 and DUT 2 and DUT 3 and DUT 4) in the indicated sequence of conditions. Irradiation was with Pr at 10º incidence
for effective LET = 60MeV*cm2/mg with the case temperature at +125ºC ±10ºC and to a fluence of 5x106 ions/cm2 for each test. Shaded entries
indicate changes in excess of the change criteria at the column heads.
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Test Report 016
SET Testing of the ISL71830SEH
The objective of this SET testing was to look for SET disruptions
on the output (pin 28, VOUT) of the operating ISL71830SEH. The
biasing was arranged to provide addressing at the input logic
thresholds of 70% and 30% of the VREF (2.1V and 0.9V at
VREF = 3V). These settings provide minimal noise margin against
SET events. The unselected inputs (1-12, and 14-16) were
connected to one of the supply rail voltages while input 13 was
connected to the positive supply through a 10kΩ resistor with
another 10kΩ resistor from VOUT to GND. This ensured a
significant change in VOUT should an address change be induced
or instantaneous connection to a rail be induced by an ion
impact. A ±20mV trigger on VOUT was used to indicate and
capture an SET. Testing began at LET = 86MeV*cm2/mg and
continued at LET = 43 and LET = 20MeV*cm2/mg.
The results in Table 2 indicate that no SET of greater than 20mV
deviation were generated for the testing run with
LET = 20MeV*cm2/mg and significantly fewer SET greater than
20mV were generated at LET = 43MeV*cm2/mg as compared to
LET = 86MeV*cm2/mg.
The SET data was post processed to select out the twenty largest
deviations (for both positive and negative extreme deviations)
and the twenty longest durations (for both positive and negative
extreme deviations) for plotting as in Figure 2 for the case of
LET = 86MeV*cm2/mg. Of the 80 possible SET not all are unique
as the largest deviations are often also the longest durations.
From Figure 2 it can be seen that the SET observed at V+ = 3V
and LET = 86MeV*cm2/mg were uniformly less than 75mV peak
excursion and had decay time constants on the order of 5µs so
that the SET essentially disappeared in 15µs from the SET
initiation. The RC decay magnitudes appear to peak at about
-50mV and +25mV. The RC decay time is dominated by the
700pF of the monitor cable and the 5kΩ of equivalent resistance
driving VOUT to its nominal level.
Figure 3 displays the composite plots for the case of V+ = 5.5V
and LET = 86MeV*cm2/mg. In these cases the peak excursions
just exceed 100mV with slightly larger RC decay magnitudes
than seen at V+ = 3V. The slightly larger SET magnitudes are in
line with the increase in V+ from 3V to 5.5V so that the SET
magnitudes seem linked to the supply rails as anticipated. Again
the RC decay back to nominal VOUT is within 15µs.
Figure 4 displays the composite plots for the case of V+ = 3V and
LET = 43MeV*cm2/mg. In these cases the peak excursions are
under 50mV with RC decay magnitudes less than 25mV. In
Figure 5 the trend toward larger SET with the higher V+ of 5.5V is
seen again, but the magnitudes are significantly less than seen
at LET = 86MeV*cm2/mg.
The trend toward smaller SET is completed at
LET = 20MeV*cm2/mg where no SET of greater than the ±20mV
trigger criteria were captured. This does not imply a lack of SET
but rather a limitation on the size of SET.
TABLE 2. TABLE FOR SET EXCEEDING ±20mV AT MINIMAL ADDRESSING CONDITIONS (Note 2)
TEST CONDITIONS:
LET in MeV*cm2/mg
SET COUNTS
FOR ±20mV TRIGGER
V+, VIN13
(V)
VREF
(V)
APPROX. VOUT
(V)
DUT 1
DUT 2
DUT 3
DUT 4
CROSS SECTION
(cm2)
CLOSED
3.0
3.0
1.50
296
410
--
288
8.28x10-5
CLOSED
5.5
3.0
2.75
226
234
216
219
5.59x10-5
CLOSED
3.0
3.0
1.50
29
19
11
8
4.19x10-6
CLOSED
5.5
3.0
2.75
89
83
59
92
2.02x10-5
CLOSED
3.0
3.0
1.50
0
0
--
--
<1.25x10-7
CLOSED
5.5
3.0
2.75
0
0
--
--
<1.25x10-7
SW1
Au LET0º = 86
Ag LET0º = 43
Cu LET0º = 20
NOTE:
2. SW1 = closed is logic thresholds. Each indicated irradiation was done to a fluence 4x106 ion/cm2.
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FIGURE 2A.
FIGURE 2B.
FIGURE 2C.
FIGURE 2. Composite plot of 20 largest and longest SET for both positive and negative deviations. DUT 1, 2 and 4 at LET = 86MeV*cm2/mg and
V+ = 3V. DUT 3 had AC noise obliterating the SET indicative of a poor contact, so it was omitted.
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Test Report 016
FIGURE 3A.
FIGURE 3B.
FIGURE 3C.
FIGURE 3D.
FIGURE 3. Composite plot of 20 largest and longest SET for both positive and negative deviations. DUT 1-4 AT LET = 86MeV*cm2/mg and
V+ = 5.5V.
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Test Report 016
FIGURE 4A.
FIGURE 4B.
FIGURE 4C.
FIGURE 4D.
FIGURE 4. Composite plot of 20 largest and longest SET for both positive and negative deviations. DUT 1-4 at LET = 43MeV*cm2/mg and V+ = 3V.
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Test Report 016
FIGURE 5A.
FIGURE 5B.
FIGURE 5C.
FIGURE 5D.
FIGURE 5. Composite plot of 20 largest and longest SET for both positive and negative deviations. DUT 1-4 at LET = 43MeV*cm2/mg and V+ = 5.5V.
Conclusions
No SEE damage (within 12% increase in supply current) was
observed on the four units tested at 6.5V supply and inputs with
ions of effective LET = 60MeV*cm2/mg. The testing was done at
+125°C case temperature. A unit registered catastrophic
damage at 6.75V. Three units survived at 7.0V with no apparent
changes due to irradiation there. It must be concluded that safe
operation at effective LET = 60MeV*cm2/mg is limited to 6.5V.
Further testing is planned to look at the 6V to 6.8V range for
better resolution on the limits of damaging SEE.
SET testing of the ISL71830SEH demonstrated only small SET
(just over 100mV peak) at LET = 86MeV*cm2/mg. At the 20mV
trigger, the SET cross section was less than 1x10-4 cm2 for
LET = 86MeV*cm2/mg. At LET = 43MeV*cm2/mg the cross
section for ±20mV events dropped to about 2x10-5 cm2 with the
maximum peak deviations under 50mV. At
LET = 20MeV*cm2/mg no SET reached the ±20mV trigger
threshold corresponding to a nominal cross section of
<1.25x10-7 cm2 for ±20mV events. In all cases the RC decay
dominated by the 700pF of cable load on VOUT and the 10kΩ
resistors to VIN13 and GND allowed the SET to die out in 15µs.
Extrapolating from the test conditions, the SET magnitudes
toward the farthest rail could roughly double for signals
nominally near either of the two rails, V+ or GND. It is also
reasonable to assume different recovery times for different VOUT
loading and source resistance from the selected VINxx. For
example, a 100pF load on VOUT and a 1kΩ source resistance
should result in a SET recover in under 1µs.
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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