Data Sheet

Freescale Semiconductor
Advance Information
Document Number: MC34SB0410
Rev. 3.0, 5/2015
Fully Integrated Quad Valve
Controller System on Chip
SB0410
The SB0410 device is a SMARTMOS valve and motor controller system
designed for use in harsh industrial environments.
INDUSTRIAL CONTROLLER CHIP
It has four high-current low-side drivers for use with solenoid valves, and highside gate pre-driver to control a DC motor through an inexpensive external Nchannel MOSFETs. Alongside this, the SB0410 has three analog to digital
converters, plus two low-side driver allowing to drive resistive charges. The digital
I/O pins can be configured for both 5.0 V and 3.3 V levels for easy connection to
any microprocessor. The SB0410 uses standard SPI protocol communication.
The SB0410 is a perfect solution for hydraulic and pneumatic applications.
Features
• Operating voltage 6.0 V to 36 V
• Four valves control
• Four current regulated valves up to 2.25 A (5.0 kHz)
• Pump motor pre-driver up to 16 kHz PWM
• 16-bit SPI interface
• Three 10-bit ADC channels
• Two low-side driver for resistive charge (RDS(on) 14.0 )
• Die temperature warning
• Supervision
AE SUFFIX (PB-FREE)
98ASA00173D
48-PIN LQFP-EP
Applications
Industrial Controller
• Spot Welding
• Dialysis machines
• Temperature Control
• Blood pressure
• Brake Pressure
• Soda dispensers
• Laser Cutting
• Bottle Moulding
• Heavy equipment and
construction machinery
• Filling Pressure
• Fork lifts
• 3D Printer
• Oxygen Concentrator
• Medical test equipment
• Water control system for
irrigation (connected to
farm tractor)
• Food control in animal
farm
MC34SB0410
VBAT
External 5.0 V
Regulator
VCC
DOSV
VINT_A
VCC5
VINT_D
VCC5
5.0V
VCC5
VBAT
RSTB
VPWR
SO
SI
CSB
SCLK
VBAT
Solenoid
Coil
4
LSDx
MCU
PDI
VBAT
PD_D
PD_G
PD_S
ADINx
VBOOT
M
NC
LDx
GND_D
3
GND_A
2
GND_P0,1...12
VBAT
Figure 1. SB0410 Simplified 5.0 V Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice
© Freescale Semiconductor, Inc., 2014-2015. All rights reserved.
Table of Contents
1
2
3
4
5
6
7
8
9
Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 Thermal Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Logical Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Pump Motor Pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 Low-side Driver for Resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5 Analog to Digital Converter (x3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.6 Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7 SPI and Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.1 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
1
Orderable Parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided
on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for
the following device numbers.
Table 1. Orderable Part Variations
Part Number
MC34SB0410AE
Temperature (TA)
Package
Notes
-40 °C to 125 °C
7.0 mm x 7.0 mm, 48 LQFP-EP
(1)
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
SB0410
3
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
Internal Block Diagram
VCC5
VPWR
Internal Power Supply
DOSV
VINT_A
VINT_D
RSTB
Charge Pump
CP
PD_D
PD_G
Supervision
Pump Motor Pre-driver
PD_S
PDI
VBOOT
LSD1
LSD2
LSD3
LSD4
LD1
LD2
Current Regulation
Or
PWM
LSDx
(x4 ch)
16-Bit SPI
Decoding / Encoding
Registers
Low-side Driver
(x2)
ADC
(x3 ch)
GND_A GND_D
GND_Px
CSB
SCLK
SO
SI
ADINx
EP
Figure 2. SB0410 Simplified Internal Block Diagram
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
RSTB
GND_P11
VINT_A
GND_A
VCC5
ADIN3
ADIN2
ADIN1
GND_P10
SO
46
45
44
43
42
41
40
39
38
37
Transparent Top View
GND_P0
Pinout Diagram
LSD1
3.1
47
Pin Connections
48
3
LSD1
1
36
NC
GND_P1
2
35
NC
GND_P2
3
34
NC
LSD2
4
33
DOSV
LSD2
24
NC
NC
SCLK
25
23
26
12
NC
11
LSD4
PD_S
GND_P6
22
SI
21
27
PD_G
10
20
GND_P5
VBOOT
CSB
19
PDI
28
PD_D
29
9
18
8
LSD3
GND_P8
LSD3
17
GND_P9
VPWR
30
16
7
LD2
GND_P4
15
VINT_D
LD1
31
14
6
13
GDN_D
LSD4
32
GND_P7
5
GND_P3
Figure 3. SB0410 48-Pin LQFP-EP Pinout Diagram
SB0410
5
Analog Integrated Circuit Device Data
Freescale Semiconductor
3.2
Pin Definitions
Table 2. SB0410 Pin Definitions
Pin
Number
Pin Name
DOSV =
5.0 V
DOSV =
3.3 V
Notes
1, 48
LSD1
Low-side driver for current regulated or
Open drain output for low-side driver 1
PWMed valves
no
no
(2)
2
GND_P1
Supply
Power ground 1
no
no
(4)
3
GND_P2
Supply
power ground 2
no
no
(4)
4, 5
LSD2
Low-side driver for current regulated or
Open drain output for low-side driver 2
PWMed valves
no
no
(2)
6
GND_P3
Supply
Power ground 3
no
no
(4)
7
GND_P4
Supply
Power ground 4
no
no
(4)
8, 9
LSD3
Low-side driver for current regulated or
Open drain output for low-side driver 3
PWMed valves
no
no
(2)
10
GND_P5
Supply
Power ground 5
no
no
(4)
11
GND_P6
Supply
Power ground 6
no
no
(4)
12,13
LSD4
Low-side driver for current regulated or
Open drain output for low-side driver 4
PWMed valves
no
no
(2)
14
GND_P7
Supply
Power ground 7
no
no
(4)
15
LD1
Low-side driver 1 for general purpose
Open drain output for low-side driver 1
no
no
16
LD2
Low-side driver 2 for general purpose
Open drain output for low-side driver 2
no
no
17
VPWR
Supply
Supply pin connect to battery through reverse
diode
no
no
18
GND_P8
Supply
Power ground 8
no
no
19
PD_D
Motor pump driver
Drain feedback pump motor FET. Connect to
drain of external pump motor FET
no
no
20
VBOOT
Motor pump driver
Bootstrap
no
no
21
PD_G
Motor pump driver
Gate output to control pump motor FET.
Connect to gate of external pump motor FET
no
no
22
PD_S
Motor pump driver
Source feedback pump motor FET
Connect to source of external pump motor FET
no
no
26
SCLK
SPI
SPI interface clock input
no
no
27
SI
SPI
SPI interface digital input
no
no
28
CSB
SPI
SPI interface chip interface
no
no
29
PDI
Motor pump driver
Pump driver input for MCU control
no
no
30
GND_P9
Supply
Power Ground 9
no
no
(4)
31
VINT_D
Internal function
2.5 V internal supply for digital
no
no
(3)
32
GND_D
Supply
Digital ground
no
no
33
DOSV
Supply
Digital output voltage supply, DOSV
undervoltage reset
5.0 V
3.3 V
37
SO
SPI
SPI interface digital output
38
Pin Function
GND_P10 Supply
Definition
(4)
DOSV bias
Power Ground 10
no
no
39
ADIN1
ADC
Analog to digital input 1
no
no
40
ADIN2
ADC
Analog to digital input 2
no
no
(4)
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
Table 2. SB0410 Pin Definitions (continued)
Pin
Number
Pin Name
41
ADIN3
ADC
42
VCC5
43
44
45
DOSV =
5.0 V
DOSV =
3.3 V
Analog to digital input 3
no
no
Supply
5.0 V supply pin
5V
5V
GND_A
Supply
Analog ground
no
no
VINT_A
Internal function
2.5 V internal supply for analog
no
no
(3)
Power ground 11
no
no
(4)
Pin Function
GND_P11 Supply
Definition
46
RSTB
Reset
Reset
no
no
47
GND_P0
Supply
Power ground 0
no
no
23, 24, 25,
34, 35, 36
NC
Not connected
Pin used for production tests and must be
grounded
no
no
Power ground 12
no
no
Exposed
pad
GND_P12 Supply
Notes
(4)
(4)
Notes
2. Pins with the same name must be shorted together
3. 220 nF/10 V capacitor needed
4. All GND_Px pins must be shorted together at the PCB level.
SB0410
7
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
General Product Characteristics
4.1
Maximum Ratings
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (Rating)
Min.
Max.
Unit
Notes
Supply
VVPWR
Analog Power Supply Voltage
-0.3
40
V
VDOSV
Digital Output Supply Voltage
-0.3
7.0
V
VVCC5
Digital Power Supply Voltage
-0.3
7.0
V
VGND_A
Ground Analog
-0.3
0.3
V
VGND_D
Ground Digital
-0.3
0.3
V
VGND_P
Ground Exposed Pad
-0.3
0.3
V
VVINT_A
Internal Regulator Analog Power Supply
-0.3
3.0
V
VVINT_D
Internal Regulator Digital Power Supply
-0.3
3.0
V
-0.3 or
VPWR -0.3
VPWR +15
V
-0.3
40 or VPWR
+0.3
V
Internal Function
Charge Pump
VCP
Internal Charge Pump
High-side Driver for General Purpose
VHS
High-side Driver
High-side Driver for Valve’s Fail-safe FET
VHD_G
Gate of the High-side Pre-driver
-20
55
V
VHD_S
Source of the High-side Pre-driver
-0.3
40
V
VHD_D
Drain of the High-side Pre-driver
-0.3
40
V
-0.3 or
PD_S-0.3
VBOOT + 0.3
V
Motor Pump Driver
VPD_G
Gate of the Motor Pump Pre-driver
VPD_S
Source of the Motor Pump Pre-driver
-20
40
V
VPD_D
Drain of the Motor Pump Pre-driver
-20
40
V
VBOOT
Bootstrap Voltage
-10
VBOOT+0.3
V
Motor Control Input Voltage
-0.3
7.0
V
Reset Pin
-0.3
7.0
V
Input Analog to Digital
-0.3
7.0
V
VPDI
Reset
VRSTB
A to D Converter
VADINx
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
Table 3. Maximum Ratings (continued)
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Description (Rating)
Min.
Max.
Unit
Notes
SPI
VSO
Serial Peripheral Interface Slave Output
-0.3
DOSV +0.3
V
VSI
Serial Peripheral Interface Slave Input
-0.3
7.0
V
VCSB
Serial Peripheral Interface Chip Select
-0.3
7.0
V
VSCLK
Serial Peripheral Interface Clock
-0.3
7.0
V
—
active
clamp
V
-100 mA
40
V
Energy Capability (EAR) at 125 °C
• LSD1—4, with 20 mH load
—
30
mJ
ILSDX(POS)
Drain Continuous Current; during on state
• LSDx
—
5.0
A
ILSDX(NEG)
Maximum Negative Current for 5.0 ms Without Being Destroyed
• LSDx
-6.0
—
A
Input Current
• SI, CSB, SCLK, RSTB, PDI
-20
20
mA
Low-side Driver for Valves (LSD1-4)
VLSDx
Low-side Driver for Valves
Low-side Driver
VLSD
Low-side Driver
Energy Capability
ELSD1—4
Currents
IDIG
4.2
Operating Conditions
This section describes the operating conditions and the current consumptions. Conditions apply to all the following data, unless otherwise
noted.
Table 4. Operating Conditions
Voltage parameters are absolute voltages referenced to GND. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
VPWR
Functional Operating Supply Voltage. Device is fully functional.
• All features are operating
6.0
—
36
V
VCC5
Functional Operating Supply Voltage. Device is fully functional.
• All features are operating.
4.75
—
5.25
V
VDOSV
Functional Operating Supply Voltage. Device is fully functional.
• All features are operating.
3.13
—
5.25
V
Notes
SB0410
9
Analog Integrated Circuit Device Data
Freescale Semiconductor
4.3
Supply Currents
This section describes the operating conditions and the current consumptions. Conditions apply to all the following data, unless otherwise
noted.
Table 5. Supply Currents
Characteristics noted under conditions 6.0 V  VPWR  36 V, 4.75 V  VCC5  5.25 V, 3.13 V  VDOSV  5.25 V, - 40 C  TJ  125 C,
GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal
conditions, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Quiescent Current of VPWR Measured at 36 V, VCC5 = 0 V
—
—
30
A
Current of VPWR in Operating Mode
—
—
20
mA
—
10
—
mA
—
10
—
mA
Notes
VPWR Current Consumptions
IQVPWR
IVPWR
VCC5 Current Consumptions
IVCC5
Current of VCC5 Pin in Operating Mode (SPI frequency at 10 MHz)
DOSV Current Consumptions
IDOSV
4.4
Current of DOSV Pin in Operating Mode (SPI frequency at 10 MHz)
Thermal Ratings
Table 6. Thermal Data
Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol
Min.
Typ.
Max.
Unit
Operational Junction Temperature
-40
—
150
°C
TSTG
Storage Temperature
-65
—
150
°C
RθJC
RθJC, Thermal Resistance, Junction to Case (Package exposed pad)
- Steady state
—
—
1.5
°C/W
(5)
Peak Package Reflow Temperature During Reflow
—
—
Note 6
°C
(6)
TJ
TPPRT
Parameter
Notes
Notes
5. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance.
6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature
and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to
view all orderable parts. (i.e. MC34xxxD enter 34xxx), and review parametrics.
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
4.5
Logical Inputs and Outputs
Table 7. Logical Inputs/Outputs
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to 125 °C, unless otherwise specified.
Symbol
Description (Rating)
Min.
Max.
Unit
Notes
Logical Inputs
VIH_X
Input High-voltage
• RSTB, SI, CSB, SCLK, PDI
—
2.0
V
VIL_X
Input Low-voltage
• RSTB, SI, CSB, SCLK, PDI
0.8
—
V
Logical Outputs
VOH_X
Input High-voltage, with 1.0 mA
• SO
0.8 x DOSV
—
V
VOL_X
Input Low-voltage, with 1.0 mA
• SO
—
0.4
V
VOL_RSTB
RSTB Low-voltage, with 1.0 mA
• RSTB
—
0.4
V
SB0410
11
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
General Description
5.1
Block Diagram
Four Valves
Low-side
(Regulated and PWM)
Motor Pump
Two Low-side Drivers
Pre-driver (16 kHz)
for General Purpose
Supervision
SPI Registers (16-Bit)
Three Analog to
Digital Converters
Figure 4. SB0410 Functional Block Diagram
5.2
Functional Description
The SB0410 device is a valves and DC motor controller, designed for use in harsh industrial environments, requiring few external
components.
The SB0410 has four high-current low-side drivers to use with solenoid valves, and one high-side pre-drivers to controlling an external Nchannel MOSFETs to use with a DC motor at high frequency thanks to the integrated bootstrap. In conjunction with this primary
functionality, the SB0410 has two low-side drivers to control a resistive load. The digital I/O pins can be used for both 5.0 V and 3.3 V
levels for easy connection to any microprocessor. The device includes three Analog to Digital converters. The SB0410 uses standard SPI
protocol for communication.
5.3
Features
This section presents the detailed features of SB0410.
Table 8. Device Features Set
Function
Low-side Solenoid Driver (x4)
Pump Pre-driver
Description
•
Solenoid driver (300 m max. RDS(on) at 125 °C) works either as current regulator or as PWM
•
Current regulation deviation: 2.0%
•
Configurable PWM frequency from 3.0 kHz to 5.0 kHz
•
10-bit resolution on the current value targeted (Regulated mode).
•
8-bit resolution on the duty cycle. (PWM mode)
•
Open load detection
•
VDS state monitoring
•
Overcurrent shutdown
•
Overtemperature shutdown
•
Send current regulation error flag
•
Motor pump pre-driver up to 16 kHz. PWM frequency controllable through SPI command or a digital signal (PDI pin).
•
Overcurrent shutdown between external FET drain and source
•
Overtemperature shutdown
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
Table 8. Device Features Set (continued)
Function
Description
•
Low-side Driver for Resistive
Charge (x2)
Analog to Digital Converter
Supervision
Low-side driver (20 mA max, RDS(on) 8.0 )
•
Open load detection
•
VDS state monitoring
•
Overcurrent shutdown
•
Overtemperature shutdown
•
10-bit ADC
•
External ADINx pins (x3)
•
Internal voltages and temperature information
•
Duty cycle to current converter for low-side (LSDx).
•
VINT_x undervoltage (internal regulator)
•
VCC5 & DOSV undervoltage (supply voltage from external)
•
External reset fault
•
VPWR undervoltage and overvoltage detections
•
Mismatch MAIN-AUX OSC CLK
•
Temperature warning
•
SPI failure
•
Bootstrap issue
•
GND supervision
SB0410
13
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
Functional Block Description
6.1
Error Handling
Table 9. Error Handling
Type of Error
Detection
condition
Action
Clear SPI flag
Restart condition
Pump Motor PWM Driver
Overcurrent between external
FET Drain and Source
ON
PD_G Off+ SPI fault flag (PD_oc)
Write 1 to PD_clr_flt
Write 1 to PD_clr_flt and then turn on
PDI
Overtemperature
ON
PD_G Off+ SPI fault flag (PD_ot)
Write 1 to PD_clr_flt
Write 1 to PD_clr_flt and then turn on
PDI
SPI flag (LSDx_op)
Read diagnosis
No
Read VDS state by SPI (vds_LSDx)
Update with min filter time
(T1) rise and fall edge
No
LSDx
Open load
VDS state monitoring
OFF
ON/OFF
Overcurrent
ON
OFF fault FET only+ SPI fault flag
(LSDx_oc)
Write 1 to LSD_clr_flt
Write 1 to LSD_clr_flt and turn on by
SPI command (LSDx duty cycle or
current set point)
Overtemperature
ON
OFF fault FET + SPI fault flag
(LSDx_ot)
Write 1 to LSD_clr_flt
Write 1 to LSD_clr_flt and turn on by
SPI command (LSDx duty cycle or
current set point)
Current regulation error
ON
SPI flag (LSDx_crer)
Read diagnosis
No
OFF
SPI flag (LDx_op)
Read diagnosis
No
VDS state by SPI (VDS_LDx)
Update with min filter time
(T1) rise and fall edge
No
LDx
OpenLoad
VDS state monitoring
ON/OFF
Overcurrent
ON
OFF fault FET + SPI fault flag
(LDx_oc)
Write 1 to LDx_clr_flt
Write 1 to LDx_clr_flt and turn on by
SPI command (LDx_on)
Overtemperature
ON
OFF fault FET + SPI fault flag
(LDx_ot)
Write 1 to LDx_clr_flt
Write 1 to LDx_clr_flt and turn on by
SPI command (LDx_on)
No
Supervision
VINT_x undervoltage
All except SPI registers reset & Vint_uv go to
Sleep mode High (See Table 19)
Read Vint_uv bit (See
Table 19)
VCC5 & DOSV undervoltage
All except SPI registers reset except some bit.
Sleep mode (See Table 19)
Wait undervoltage reset filter
time T1
See Table 19,
(see Table 19)
External reset fault
No internal
SPI registers reset except some bit.
RSTB
(See Table 19)
pulldown
Read the corresponding
message of the SPI register
(see Table 19)
VPWR undervoltage
RSTB is
high state
VPWR overvoltage
All LSDx Off (Clear all LSDx duty
1. Normal condition 
RSTB is in
1. Normal condition 
cycle registers or current set point) +
2. Turn on by SPI command (LSDx
high state
2. Read diagnosis (VPWR_OV)
SPI fault flag (VPWR_OV)
duty cycle or current set point)
Mismatch SB0410 MAIN-AUX
OSC CLK
RSTB is in SPI registers goes to initial state low
high state except (see Table 19,)
Read RST_clk bit
No
Temperature warning
RSTB is in
SPI flag
high state
1. Normal condition
2. Read diagnosis
No
See Table 19,
1. Normal condition 
All LSDx Off (Clear all LSDx duty
1. Normal condition
2. Turn on by SPI command (LSDx
cycle registers or current set point) +
2. Read diagnosis (VPWR_UV) duty cycle or current set point)
SPI fault flag (VPWR_UV)
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
Table 9. Error Handling (continued)
Type of Error
Detection
condition
Action
Clear SPI flag
Restart condition
Supervision (Continued)
SPI failure
RSTB is in
SPI flag (Fmsg)
high state
Read diagnosis
No
VPRE 1x monitoring (8)
RSTB is in
Send by SPI (ADC)
high state
No
No
VINT_x monitoring (8)
RSTB is in
Send by SPI (ADC)
high state
No
No
VGS_PD monitoring
RSTB is in
Send by SPI (ADC)
high state
No
No
Temperature monitoring (8)
RSTB is in
Send by SPI (ADC)
high state
No
No
GND_D supervision
RSTB is in
SPI flag only (FGND)
high state
No
No
GND_A supervision; indirect
detection by VCC5 or DOSV
RSTB is in SPI flag only (VCC5_UV or
high state DOSV_UV)
No
No
Notes
7. To clear an error flag, SW engineer has to read the register concerned and then write a “1” on the xxx_clr_flt flag.
8. SW engineering can monitor internal supply voltage in real time with ADC SPI reading, and can use fail-safe function. If these ADC results are not
in a certain range, uC can reset the SB0410 (see ADC section).
6.2
Low-side Driver
6.2.1
Introduction
The SB0410 is designed to drive in current regulated or in digital mode inductive loads in low-side configuration. All four channels are
managed by logic and faults are individually reported through the SPI. The device is self-protected against short-circuit, overtemperature,
can detects an open-load and finally allows to monitor in real-time the VDS state.
When Channels 1 to 4 work as a current regulator, a freewheeling diodes must be connected. Each channel comprises an output
transistor, a pre-driver circuit, a diagnostic circuitry, and a current regulator. The SPI registers (10 to 13) defines the current output
targeted. This output is controlled through the output PWM of the power stage. The LSD1-4 current slopes are controlled by a SPI
command to reduce switching loss.
6.2.2
Digital mode
LSD1 to 4 can be used in digital mode (also called “PWM”). This function integrates a current recirculation thanks to the gate-drain clamp
circuitry embedded. The output transistor is equipped with an active clamp limiting LSDx voltage to vcl_lsd. During turn-off, the inductive
load forces the increasing output voltage until the active voltage clamps, such as when the power FET turns on again.
SB0410
15
Analog Integrated Circuit Device Data
Freescale Semiconductor
Open
Duty-cycle (SPI)
VDS Monitoring
VPWR
Overcurrent
Logic
Soleinoide
Overtemperature
Status / Fault
(Trough SPI)
LSDx
Gate Driver
PGND
Figure 5. PWM Low-side Driver
The duty cycle of PWM low-side drivers is programmed via an 8-bit SPI message. The duty cycle between 0% and 100% can be selected
and the LSB of the 8 bits is weighted with an 0.39% duty. Each channel has an 8-bit SPI register of PWM duty cycle.
The PWM low-side driver uses each channel as a digital low-side switch.
PWMx duty cycle = 0xFF - Digital low-side switch ON (conducting)
PWMx duty cycle = 0x00 - Digital low-side switch OFF
6.2.3
Interleave Function
The SB0410 provides interleaved phase shift switching to minimize switching noise of the solenoid coil. Each LSDx is shift to 1/4 of the
period from the previous one. this interleave function started with the LSD1.
200 µs (5.0 kHz PWM Frequency)
CH1
CH2
CH3
CH4
SPI
4 SPI access
Figure 6. PWM Valve Control Interleave
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
Table 10. Low-side Driver Electrical Characteristics
VPWR = 6.0 V to 36 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to 125 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Power Output
RON_LSD14
On Resistance Channel 1 to 4: CR
• TJ = 125 °C; 9.0 V VPWR 36 V; ILOAD = 2.0 A
—
—
0.225

RON_LSD14_E
On Resistance Channel 1 to 4: CR (extended mode)
• TJ = 125 °C; 5.5 V VPWR 9.0 V; ILOAD = 2.0 A
—
—
0.330

I LEAK_LSD
Drain Leakage Current
• LSD = 36 V
—
—
10
A
VCL_LSD
Active Clamp Voltage
—
38
45
V
1.0
0.1
1.7
1.35
3.0
3.0
s
tF_CR1
Rise Time/Fall Time
• 10% to 90%, ILOAD = 1.0 A, VPWR = 36 V; no capacitor didt = 0
(SPI bit)
tR_CR2
tF_CR2
Rise Time/Fall Time
• 10% to 90%, ILOAD = 1.0 A, VPWR = 36 V; no capacitor didt = 1
(SPI bit)
0.05
0.1
0.5
1.0
1.0
3.0
s
0.0
—
3.0
µs
20%
kHz
Timings
tR_CR1
tD on CR
tD off CR
Lf_PWM
0x00
0x01
…
0xFE
0xFF
Turn on/off Delay Time
• Digital 1 to 10% or 90%, ILOAD = 1.0 A, VPWR = 36 V, no capacitor
Output PWM frequency for LSD1-4
• LF_PWM xx = 111
• LF_PWM xx = 110
• LF_PWM xx = 101
• LF_PWM xx = 100
• LF_PWM xx = 000 (default)
• LF_PWM xx = 011
• LF_PWM xx = 001
• LF_PWM xx = 010
-20%
PWM Duty Cycle Programming (8-bits)
—
—
—
—
—
3.0
3.2
3.4
3.6
3.9
4.2
4.5
5.0
OFF
0.39
—
99.61
ON
—
—
—
—
—
(9)
%
Notes
9. Digital: internal digital signal delivered by interleave synchronization block. See Figure 6.
SB0410
17
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.2.4
Current Regulation Mode
When the external fly-back diode is connected, the current re-circulation executes via the diode to the battery.When Channels 1 to 4 work
as a current regulator, freewheeling diodes must be connected.
Figure 7. PWM Low-side Driver (Current Regulated)
The load current is sensed by an internal low-side sense FET and digitized by an internal A/D converter. The target value of the current
is given SPI messages. A digital current regulation circuitry compares the actual load current with the target current value and steers the
duty cycle of the low-side power switch. The PI regulator characteristic can be adjusted via the SPI.
6.2.4.1
Target Current
Each current regulator channel has its own 10-bit target current register. The LSB of the 10 bits is weighted with 2.2 mA. A zero value
disables the power stage of the respective channel. A new target current is instantaneously passed to the settling time, which is the settling
of the new current value.
PWMx target current value = 00 0000 0000 → 0 mA
PWMx target current value = 00 0000 0001 → 2.2 mA
…
PWMx target current value = 11 1111 1110 → 2.248 A
PWMx target current value = 11 1111 1111 → 2.250 A
CR_DIS12/34
CR_fb
Mode
LSD1-4 Duty Cycle (8-bit) or Current Read (10-bit)
0
0
current regulation
Read current target (to check SPI write)
0
1
current regulation
Read output duty cycle value for gate driver.
1
0
PWM
Read programmed PWM duty cycle (to check SPI write)
1
1
PWM
Read hardware ADC current value
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
6.2.4.2
Current Measurement
The output current is measured during the “ON’ phase of the low-side driver. A fraction of the output current is diverted and (using a
“current mirror” circuit) generates across an internal resistance a voltage relative to ground, this being proportional to the output current.
6.2.4.3
PI Characteristics
Digital PI-regulator with the Transfer function is programmed via the SPI register.
KI
------------ + KP
z–1
Transfer function:
The integrator feedback register I charac bits define the regulation behavior of all channels. The default value is 1/8. Both current
regulators remain idle until a non-zero value in I charac was programmed. A high proportional feedback value accelerates the regulator
feedback and provides a faster settling of the regulated current after disturbances like battery voltage surge.
Table 11. Duty Cycle Descriptions
The duty cycle of the PWM output in clamped minimum by options and maximum 100% (see 6.7, “SPI and Data Register").
Option
LLC<1>
LLC<0>
0
0
0
Minimum Duty Cycle
10%
• the measurement is done at tON/2 by consequence
• the regulation current will be set at tON/2
1
2
3
0
1
1
1
3.12%
• for a duty cycle > 10%, the measurement is done at tON/2
• for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at
tON for 3.2% of duty cycle
0
3.12% + forced min duty cycle to 1.56% every two cycles
• for a duty cycle > 10%, the measurement is done at tON/2
• for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at
tON for 3.2% of duty cycle
• for a duty cycle set at 1.56%, no measurement is done
1
3.12% + skip min duty cycle every two cycles
• for a duty cycle > 10%, the measurement is done at tON/2 by consequence the regulation current
will be set at tON/2
• for a duty cycle 3.2% < DC < 10%, the measurement is done at tON/2 for 10% of duty cycle up at
tON for 3.2% of duty cycle
• no measurement is done during the skipping mode
If the target current value is not reached within the regulation error delay time of tCR_ERR, the flag of the SPI register “LSDx_crer” is set
to high. The current regulation loop is still running and tries to regulate at the target. Because it is not at the target, the duty cycle is either
100%, or minimum duty cycle by option. LSDx_crer error detection has no effect on the driver, only SPI fault reporting. The microcontroller
can detect the fault through the SPI (LSDx_crer bit + ADC current reading), and shutdown the driver by sending 0 target current. Set
Current – ADC result > “error threshold” during tCR_ERR then LSDx_crer is set to 1.
This flag is latched & can be reset by the SPI read (LSDx_crer). Each of the four current regulation low-side drivers can be used as a
PWM low-side switch. CR_disxx flag is enabled HIGH. The 8 MSB bits of the target current message are the PWM duty cycle. The first
duty is controlled by the SPI bit FDCL (See SPI and Data Register).
SB0410
19
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 12. LSD1 to LSD4 Current Regulation Driver Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
—
—
—
—
OFF
2.2
...
2.25
—
—
—
—
mA
—
—
—
—
—
—
—
—
—
—
65
50
25
±10
2.0
mA
mA
mA
%
%
Notes
Current Regulation
00 0000 0000
00 0000 0001 Target current programming (10-bits)
...
11 1111 1111
Maximum regulation deviation
• 0 mA ITARGET < 50 mA, includes ADC error
ICR_DEV
• 50 mA ITARGET < 100 mA, includes ADC error
• 100 mA ITARGET < 250 mA, includes ADC error
• 250 mA ITARGET < 400 mA, includes ADC error
• 400 mA ITARGET < 2.25 A, includes ADC error
A
(10)
(11)
Notes
10. Maximum regulation deviation performances noted in the table depend on external conditions (VPWR, load (R,L)).
11.
The error can be decrease significantly by a calibration of the LSDx and using a current regulation loop done by software.
6.2.5
Fault Detection (LSD1 to LSD4)
6.2.5.1
Open Load
An open condition is detected when the LSDx output is below the threshold for the defined filter time; the fault bit is set (SPI error flag
only). This function only operates during the off state.
6.2.5.2
VDS State Monitoring
The VDS state monitoring gives real time state of LSD drain voltage vs OP_lSD voltage. This signal is filtered and sent through the SPI. If
the LSDx voltage is higher than the OP_lSD with a filter time (T1), vds_lsd is set to “1”.
6.2.5.3
Overcurrent
When the current is above the overcurrent threshold for the defined filter time, the driver is switched off, a SPI fault bit is set, and the
driver can be turned back to the “normal state” by a SPI write “1” to “LSDx_clr_flt “, followed by a send target current command.
6.2.5.4
Overtemperature
When the temperature is above the overtemperature threshold for the defined filter time, the driver is switched off, a SPI fault bit is set,
and the turn-on SPI command is cleared. The driver can be turned back to the “normal state” when the temperature returns to a normal
state, then SPI write “1” to “LSDx clr flt”, followed by a send target current command.
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
Table 13. Detection Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
—
8.5
—
A
Open Load Detection Threshold (also used for VDS monitoring)
—
2.0
—
V
VDS State Filter Time
—
T1
—
s
-15%
1.0
+15%
V
180
195
210
°C
—
25
—
LSB
Notes
PD_G
OCLSD
Overcurrent Detection Threshold Current
Open load detection
OPLSDSRC
VDS Monitoring
tVDS_LSDX
Overtemperature Shutdown
VPD_OC
Overcurrent detection threshold - VPD_D - VPD_src
Overtemperature Shutdown
OTLSD
Overtemperature Detection Threshold
Current Regulation Error (Regulation mode only)
ICRDELTA
Current Regulation Error - ADC Result (measurement data) - (target
programming current) • 1LSB = 2.25 A/1024 = 2.197 mA
6.3
Pump Motor Pre-driver
6.3.1
Function Description
This module is designed for DC motor pump, a maximum of 16 kHz PWM is possible. The pre-driver is made with a bootstrap as well as
small charge pump structure to operate to 100% duty cycle.
.
Figure 8. Pump Motor Pre-driver
A duty cycle comprised between 0% to 10% and between 90% to 100% is not possible due to the structure.
SB0410
21
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.3.2
Fault Detection
6.3.2.1
Overcurrent
The pump driver protects the external N-channel power FET on the PD_G pin in overcurrent conditions. The drain-source voltage of the
FET on PD_G is checked if the pump driver is switched on. If the measured drain-source voltage exceeds the overcurrent voltage
threshold, the output PD_G is switched off. Overcurrent detection logic has a masking time from PDI turn-on against malfunction on
transient time. After switching off the power FET by an overcurrent condition, the power FET can be turned back to “normal state” by only
SPI write 1 to “PD_clr_flt” register, and then turn on with PDI.
After pump driver is switched on and it stays on during minimum time period T1/2 (masking period), a cumulate/decumulate process of
overcurrent fault detection logic is enabled. After the masking period is over, if both events are present (PDI = 1 and overcurrent condition),
there is a cumulate (increment) process taking place measuring the maximum time period T1 to qualify an overcurrent fault event. If both
events are present longer than T1, this activates an overcurrent fault (and consequently sets corresponding flag). If PDI = 0, the cumulate
process is halted but not reset. If during PDI = 1 the event of the overcurrent condition is not present, this resets a previously cumulated
value.
Figure 9. Block Diagram of Cumulate/De-Cumulate Process of Overcurrent Fault Detection Logic
Function of T1 counter:
a) Increment
b) Hold
c) Reset
d) Overcurrent fault detected
6.3.2.2
Overtemperature
When the temperature is above the overtemperature threshold for the defined filter time, the driver is switched off and a SPI fault bit is
set. The driver can be turned back to the “normal state” by writing a 1 to PD_clr_flt, then turn PDI on.
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
6.3.2.3
External Components of Pump Pre-driver
An external 15 V Zener clamping (1 direction) is necessary between VBOOT and PD_S to protect the gate of the external Power MOSFET.
An internal diode between VBOOT and PD_G ensures that PD_G cannot go higher than VBOOT (1 VBE higher). Optional 15 V Zener
clamping can be added between PD_G & PD_S (not necessary). The zener chains are used for avalanche clamping and protection
against transients.
A typical external MOSFET is IPB80N04S2, which is 4.0 m(for indication only). An external resistor of 500 kis connected between
PD_G & PD_S to turn the MOSFET OFF, in case of an open soldering contact. An external resistor (RG) in series with PD_G is added to
decrease the slew rate and optimize EMC. The value of the CBOOT capacitor between VBOOT & PD_S can be 330 nF (for 5.0 kHz &
20 kHz).
Table 14. Pump Motor Pre-driver Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
• 5.5 V VPWR < 6.0 V
• 6.0 V VPWR < 7.0V
VPWR+ 4
VPWR+5
VPWR+ 15
VPWR+15
• 7.0 V VPWR < 10 V
• 10 V VPWR < 36 V
VPWR+7
VPWR+10
—
—
—
—
• 5.5 V VPWR < 7.0 V
VPWR+ 4.5
2xVPWR-2.0
VPWR+10
—
—
—
Unit
Notes
PD_G
VPD_ON_5K
VPD_ON_20K
• 7.0 V VPWR < 12.0V
• 12.V VPWR < 36 V
V
(12)
VPWR+ 15
VPWR+15
VPWR+15
V
(13)
VPWR+15
VPWR+15
VGS_OFF
PD_G switch-off voltage
—
—
0.1
V
IPDG_OFF
Turn-off current
—
300
—
A
Leakage Current - VCC5 = DOSV = 0.0 V, VPWR = 36 V, PD_S = 36 V
—
—
1.0
mA
Leakage current - VCC5 = DOSV = 0.0 V, PD_D = VPWR = 36 V
—
—
15
A
-15%
1.0
+15%
V
PD_S
lLEAK_PD_SRC
PD_D
ILEAK_PD_DRN
Overcurrent Detection
VPD_OC
Overcurrent detection threshold - VPD_D - VPD_src
tPD_OC
Overcurrent Detection Filter Time - Cumulate counter during on phase
after masking time, reset counter if no OC event during 1 cycle
—
T1
—
s
DutyAlo
10% to 90% duty cycle is allowed (also 0% and 100% is allowed)
10
—
90
%
Overtemperature Shutdown
OTPMD
Overtemperature Detection Threshold
180
195
210
°C
tOTPMD
Overtemperature Detection Filter Time
—
T1
—
s
Bootstrap Start Time - Time to charge CBOOT after wake-up of part
(VCC5 = 5.0 V). Allow Pump driver to turn on after this timing. (This
timing is smaller than reset recovery time (45 ms), so has no effect on
the application)
—
30
—
ms
VBOOT Charge
tBOOT_DELAY
Notes:
12. Frequency = 5.0 kHz , duty cycle = 10~90% and 100%, voltage measured 20 µs after turn on.
13. Frequency = 20.0 kHz , duty cycle = 10~90% and 100%, voltage measured 5.0 µs after turn on.
SB0410
23
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.4
Low-side Driver for Resistive load
6.4.1
Power Output Stages
Open
Controlled by SPI
Vbat
VDS Monitoring
Logic
Overcurrent
Overtemperature
Status / Fault
(Through SPI)
LD
No Sink
Current
Gate Driver
GND
Figure 10. Low-side Driver for Resistive Load Diagram Block
The low-side driver consists of DMOS power transistors with open drain output. The low-side driver can be driven by SPI commands. The
low-side driver is composed of an output transistor, a pre-driver circuit, and diagnostic circuitry. The pre-driver applies the necessary
voltage on the output transistor gate to minimize the On resistance of the output switch. To avoid leakage current path, LD has no sink
current.
Table 15. Low-side Driver Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to 125 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
On Resistance for LD
• TJ == 125 °C, 6.0 V VPWR 36 V
—
8.0
14

DC Current Capability
—
—
20
mA
Drain Leakage Current
• VPWR = 0, VCC5 = 0, LD = 36 V, no sink current
—
—
10
A
BVDSS Voltage
40
—
—
V
Maximum Negative Current for 5.0 ms Without Destroying the device
100
—
—
mA
Notes
Power Output LD
RON_LD
ILEAK_LD
VBVDSS_LD
INEG_LD
Timings
tD_ON_LD
Turn On Delay Time for LD
—
—
2.0
s
(14)
tD_OFF_LD
Turn Off Delay Time for LD
—
—
2.0
s
(14)
Notes
14. From Digital Signal to 50% (turn ON) or 50% (turn OFF). RL = 1.0 k, VPWR = 36 V, no capacitor
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
6.4.2
Fault Detection
6.4.2.1
Open Load
An open condition is detected when the LD output is below the threshold OPLD for the defined filter time tOP_LD, the fault bit is set ld_OP
(SPI error flag only). This function only operates during the Off state.
6.4.2.2
VDS State Monitoring
The VDS state monitoring gives real time state of LD drain voltage vs OPLD voltage. This signal is filtered and sent through the SPI vds_ld
bit. If the VDS voltage is higher than OPLD with a filter time (T1), vds_ld is set to “1”.
6.4.2.3
Overcurrent
When the current is above the overcurrent threshold OCLD for the defined filter time tOC_LD, the driver is switched off, a SPI fault bit ld_OC
is set, and the turn-on SPI command is cleared. The driver can be returned to the “normal state” by a SPI write “1” to “LD_clr_flt”, then
turned on by a SPI command (LD_on).
6.4.2.4
Overtemperature
When the temperature is above the overtemperature threshold OTLD for the defined filter time tOT_LD, the driver is switched off, a SPI fault
bit ld_OT is set, and the turn-on SPI command is cleared. The driver can be returned to the “normal state” when the temperature returns
to the normal state, a SPI write “1” to “LD_clr_flt”, then turning on a SPI command (LD_on).
Table 16. Low-side Driver Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to 125 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
Overcurrent Shutdown
IOCLD
Overcurrent Shutdown Threshold Current for LD
—
100
—
mA
tOC_LD
Overcurrent Shutdown Filter Time
—
T1
—
s
Open Load Detection
VOPLD
OpenLoad Detection Threshold (also used for VDS monitoring)
—
2.0
—
V
tOP_LD
OpenLoad Detection Filter Time
—
T2
—
s
VDS State Filter Time (rise & fall edge filter time)
—
T1
—
s
VDS Monitoring
tVDS_LD
Overtemperature Shutdown
TOTLD
Overtemperature Detection Threshold
180
195
210
°C
tOT_LD
Overtemperature Detection Filter Time
—
T1
—
s
6.5
Analog to Digital Converter (x3ch)
ADC is referenced to VCC5 voltage and converts the voltage on 10 bits. It is used to read the following voltages:
• Three analog input pins: ADINx
• Internal voltage supplies (VINT_A, VINT_D, VPRE10, VPRE12, VGS_PD)
• Average temperature of die, which is used by the temperature warning detection circuit (TEMP). Refer to the SPI Message Structure,
Message #9.
• Current to voltage converter for current regulation of LSD1-4
SB0410
25
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 17. ADC Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to 125 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
-6.0
—
6.0
LSB
(15)
Conversion Time
—
—
10
s
Refresh Time - min ADC update time; shorter than 1.0 ms
—
100
—
s
Input Leakage Current - 0 < ADINx < VCC5
-2.0
—
2.0
A
AD_VINT_A
VINT_A
440
512
590
LSB
AD_VINT_D
VINT_D
440
512
590
LSB
AD_VPRE10
VPRE10 - ADC ratio =VPRE10/3.3, 9.0 < VPWR < 16 V
400
600
800
LSB
AD_VPRE12
VPRE12 - ADC ratio = VPRE12/3.0, 9.0 < VPWR < 16 V
590
790
980
LSB
VCP-VPRWR - ADC ratio = VCP - VPWR/4.0, 9.0 < VPWR < 16 V
330
—
810
LSB
Voltage at 25 °C
—
717
—
LSB
Deviation with 1.0 °C increments
—
-2.0
—
LSB/°C
ADC
ADC_ERR
Total Error - 0 < ADINx < VCC5
tCONV
tRFT
ADINx
IADI_LK
Internal Voltage
AD_VCP
Temperature Reading
AD_TEMP25
AD_DEV_
TEMP
Notes
15. If ADINx voltage is between VCC5 to max_rating, the ADC value does not change. Also between VCC5 min and GND, the ADC value does not
change.
16. SW engineer can monitor internal supply voltage in real time with ADC, SPI reading, and can use fail-safe function.
6.6
Supervision
Event
RSTB
Normal mode: After RSTB
rising edge, No fault
High
LSDx
PDI
LD
Normal Normal Normal
SPI
Notes
Normal
VINT_x undervoltage
Low
(output)
OFF
OFF
OFF
SPI register go to initial state Low except for Vint_uv which is reset to 1.
After first read of Vint_uv, it is set back to 0.
(17)
Clock fail reset
Low
(output)
OFF
OFF
OFF
SPI registers go to initial state Low except for Vint_uv unchanged &
RST_clk which is set to 1. After first read of RST_clk, it is set back to 0.
(17)
DOSV undervoltage
Low
(output)
OFF
OFF
OFF
SPI register go to initial state except reset flag (Vint_uv, VCC5_uv,
DOSV_uv, RST_ext, RST_CLK).
(17)
VCC5 undervoltage
Low
(output)
OFF
OFF
OFF
SPI register go to initial state except reset flag (Vint_uv, VCC5_uv,
DOSV_uv, RST_ext, RST_CLK).
(17)
Low
(input)
OFF
OFF
OFF
SPI register go to initial state except reset flag (Vint_uv, VCC5_uv,
DOSV_uv, RST_ext, RST_CLK).
External Reset
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
Event
RSTB
LSDx
PDI
LD
SPI
Notes
VPWR overvoltage
No effect
OFF
ON
No
effect
Following SPI registers go to initial state Low:
A. LSDx Duty cycle or current set point.
B. PDI is ON.
VPWR undervoltage
No effect
OFF
ON
No
effect
Following SPI registers go to initial state Low:
A. LSDx Duty cycle or current set point.
B. PDI is ON.
Notes
17. State defines for the duration of the fault and the following reset recovery time period.
Restart conditions:
SPI write message #0 has first to be executed to clear any reset or fault flags. Then new SPI command can be sent.
Table 18. Start Point of Reset Recovery Time
Fault Mode
Start Point of tRST_REC
VINT_A or VINT_D_uv or VCC_uv or DOSV_uv
Come back normal voltage of all voltages
6.6.1
Additional Safety Functions
6.6.1.1
VINT_A or VINT_D Undervoltage Supervision
The 900718 uses an internal supply for analog functions (VINT_A) and digital functions (VINT_D). The supply voltage VINT_A and VINT_D
are supervised for undervoltage. When the voltage becomes lower than each threshold, VINT_A_UV and VINT_D_UV, the RSTB pin is
asserted low, after the detection filter time (tVINT). This reset state continues until the voltage at the VINT pin rises again. If VINT becomes
higher than each threshold, VINT_A_UV and VINT_D_UV, for same filter time (tVINT), the RSTB pin goes high after reset recovery time
(tRST_REC) and the related flag of the SPI register is set to a high.
For stabilization, the VINT_A & VINT_D internal supply requires external capacitors. Two bandgaps are included in the 900718. One is for
the voltage reference and the other is for the diagnostic. The ADC data for VINT_A and VINT_D are sent through the SPI.
6.6.1.2
VCC5 Supervision
See Table 19 Reset condition and reaction.
6.6.1.3
DOSV Supervision
The supply voltage DOSV is supervised for undervoltage. When the voltage at pin DOSV becomes lower than DOSV_uv, the RSTB pin
is asserted low after detection filter time (tVDUV). This reset state continues until the voltage at pin DOSV raises again. If DOSV becomes
higher than (DOSV_uv) for same filter time (tVDUV), the RSTB Pin goes high after reset recovery time (tRST_REC) and the related flag of
the SPI register is set high.
SB0410
27
Analog Integrated Circuit Device Data
Freescale Semiconductor
Figure 11. DOSV Supervision Application
6.6.1.4
Internal Clock Supervision (Mismatch MAIN-AUX CLK)
The SB0410 has two independent clock modules, one is the main supply clock to all SB0410 systems. The other monitors the main clock
fault and if a fault is detected, the SB0410 resets with the RST_CLK function (Table 19). This function starts when RSTB is in a high state.
Mutual Supervision of Both Main and Auxiliary Clock:
Clock monitoring continues to perform comparisons between the two clocks sources, CLK1 and CLK2. When everything is working
correctly, both clocks are present and both have the same frequency of 14 MHz. If one of the clocks stops or if clocks are misaligned in
frequency more than 25% of 14 MHz (Table 19), an RSTB reset is generated (Table 19) and a SPI flag is reported (RST_CLK). The reset
flag RST_CLK (same as other reset flags) is cleared in “clear on read” fashion, or in other words, the flag is cleared by a SPI Read
command which reads the flag. In the case of a clock monitoring fault, the clock monitoring process restarts only after the clock monitoring
flag (RST_CLK) is cleared on the first SPI message.
If either CLK1or CLK2 disappears indefinitely, the clock monitoring fault shows anywhere from T1 to 2*T2. If clock frequencies are
misaligned more than 25% of 14 MHz, the clock monitoring fault shows after a time delay of T2, as measured by the reference clock
CLK1. The misaligned frequency detection error is measured in the time window of T2 and the measurement is based on CLK1 clock as
reference, therefore if the CLK1 frequency changes, the time window T2 cannot be guaranteed.
The SB0410 internal clock monitoring function can be disabled by the SPI command (StopCLK2), with no effect of functionality except the
clock monitoring function, because CLK1 is activated, but CLK2 is deactivated. Frequency modulation can be controlled by the FM_amp
and FM_EM bits (See SPI and Data Register). The SPI command (FM_EN) enables the frequency modulated oscillator by two deviation
frequency to spread the oscillator’s energy over a wide frequency band. There are two kinds of deviation frequencies (350 kHz and
700 kHz), which are decided by the SPI command (FM_amp). This spreading decreases the peak electromagnetic radiation level and
improves electromagnetic compatibility (EMC) performance.
If preferred, the sequence following by SPI command (StopCLK2), and later on if decided to reactivate the CLK2 (clock monitoring reactivated), a reset clk can be generated due to the fact the clk2 re-start, and can have a settling time > 2*T2, 1.0 ms max. In this case,
reset is detected during reset recovery time and the CLK_RST (reading message #0) flag should read in a normal condition.
6.6.1.5
Die Temperature Warning
The SB0410 has one temperature warning sensor in the cool place of the die. The threshold of temperature warning is 20 °C below
overtemperature. In case of a temperature warning, outputs are not shutdown and the SPI-Bit shows the actual status at accessing time.
6.6.1.6
VPRE10, VPRE12 Undervoltage Supervision
VPRE10 and Vpre12 are internal regulator supplying power FET. These two voltage can be monitored through the SPI (Message 6 and 7).
This voltage monitoring can be used as a additional fail safe function.
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
6.6.1.7
Ground Supervision
GND-loss monitors the voltage between PGND (global reference GND) and GND_D. In case of a disconnection of GND_D vs. all other
grounds (pin 2, 3, 6, 7, 10, 11, 14, 18, 30, 38, 43, 45, 47), and back side ground are soldered to ground), a detection GND_D disconnect
as soon as the GND_D is higher than the threshold (V_GL) vs. others grounds, is reported through the flag FGND via the SPI register and
set high after a filter time (tGL).
1. Connection degraded (resistive path)
A. GND_D vs other grounds > V_GL but by having Vint_D –GND_D > min voltage required
B. SPI communication still possible, and the flag FGND will be at 1
2. Disconnection (open physically) during a sequence (in Normal mode), the logic embedded is frozen, because the voltage Vint_D
–GND_D < min voltage required
A. No SPI communication is possible
B. If GND_D is reconnected normally, SPI communication recovers and the flag FGND is at 1
Table 19. Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
-20%
45
20%
ms
External Reset Detection Filter time - Filter on falling of RSTB pin.
Mask shorter glitch.
—
2.0
—
s
Minimum External Reset Time (only for application)
—
10
—
ms
Undervoltage Reset Threshold at Shutdown (falling edge of DOSV)
—
2.9
—
V
Undervoltage Reset Filter Time
—
T1
—
s
Notes
Reset Output SB0410 to MCU
tRSTB_REC
Reset Recovery Time
Reset Input MCU to SB0410
tRSTB_EXT
tRST_MIN
DOSV Undervoltage
DOSVUV_ 3P3
tDVUV
VCC5 Undervoltage
VCC5_UV
Undervoltage Threshold
—
4.5
—
V
tVCUV
Undervoltage Filter Time
—
T1
—
s
Consumption Current
• VCC5 = 5.0 V; HD,PD = on; RSTB = high
• During SPI communication
—
—
20
10
—
—
mA
VCC5 Supply
I_VCC5
I_DOSV
Internal Logic Supply
Vint_A
Internal Analog Voltage - ILOAD = -10 mA
2.30
2.5
2.8
V
Vint_D
Internal Digital Voltage - ILOAD = -10 mA
2.30
2.5
2.8
V
C_Vint
Stabilization Capacitor at V_INT - Low-voltage capacitor (<4.0 V)
—
220
—
nF
Internal Logic Supply Undervoltage
Vint_A_UV
Vint_D_UV
Undervoltage Reset threshold
—
2.1
—
V
tVINT
Undervoltage Reset Filter time
—
1.0
—
ms
Consumption current - VPWR = 36 V, HD, PD = on, RSTB = high
—
5.0
—
mA
Consumption current at sleep mode - VCC5 = DOSV = 0 V,
HD_D = PD_D = VPWR = 36 V
—
2.0
20
A
VPWR Supply
I_VPWR
I_STBY_VPWR
SB0410
29
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 19. Electrical Characteristics (continued)
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VPWR & HD Overvoltage
VPWR_OV
VPWR Overvoltage Threshold (rising edge)
—
38
—
V
VPWR_OV_
Overvoltage Detection Hysteresis VPWR_OV(ON) = VPWR_OV(SHUTDOWN) -VPWR_OV_HYS
—
0.6
1.0
V
Overvoltage Detection Filter Time - Both directions
—
T2
—
s
HYS
tVPWR_OV
VPWR Undervoltage
VPWR_UV
Undervoltage Shutdown Threshold (falling edge)
—
5.1
—
V
VPWR_UV_
Undervoltage Detection Hysteresis VPWR_OV(ON) = VPWR_OV(SHUTDOWN) -VPWR_OV_HYS
30
100
200
mV
Undervoltage Detection Filter Time
—
T2
—
s
HYS
tVPUV
Ground-loss Detection
V_GL
GND_d-loss detection threshold - Reference GND_Px
—
0.5
—
V
tGL
GND_d-loss detection filter time - Reference GND_Px
—
T2
—
s
-7.0%
14
7.0%
MHz
Oscillator
f_OSC
Main Oscillator Frequency
eCLK
Mismatch MAIN-AUX OSC CLK - enable VINT_X is normal voltage
digital comparison between the two clocks.
-35
25
35
%
tCLK
Mismatch OSC Filter Time
T1
T2
2*T2
s
Frequency Modulation Band 1 - FM_amp = 0
-30%
350
30%
kHz
Frequency Modulation Band 2 - FM_amp = 1
-30%
700
30%
kHz
Frequency Modulation Speed
-30%
110
30%
kHz
(18)
Overtemperature/Temperature Warning
TW
Temperature Warning Detection Threshold
150
165
180
°C
tTW
Temperature Warning Detection Filter Time
—
T2
—
s
T1
Logic time base T1
14.4
18.2
22
s
T2
Logic time base T2
232
293
360
s
Timing
Notes
18. The tCLK parameter is decided by a frequency checker and comparing two clocks. If either main clock or AUX clock frequency disappears longer
than T1, the SB0410 goes to reset by the clock frequency checker and the CLK_RST flag will be detected. Meanwhile, comparing the main clock
and AUX clock is done during T2 and the SB0410 is possible to go to reset every T2. Because measurement and reset activation are
asynchronous, tCLK can reach 2*T2 in the worst case by comparing two clocks.
Write 1 to any xxx_clr_flt register will create a reset of the fault flag during 1 clock period after the SPI message. xxx_clr_flt automatically
goes to “0” after 1 clock from fault flag reset.
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
XXX Output State
ON
OFF
Normal State
XXX_Fault Internal Signal
SPI XXX_Fault_Flag
SPI Read
Fault Flag
SPI Transaction
SPI Write
XXX_cir_flt
XXX_cir_flt Internal Signal
Figure 12. Timing Diagram of xxx_clr_flt
6.7
SPI and Data Register
6.7.1
Function Description
The SPI serial interface has the following features:
• Full duplex, four-wire synchronous communication
• Slave mode operation only
• Fixed SCLK polarity and phase requirements
• Fixed 16-bit command word
• SCLK operation up to 10.0 MHz
The Serial Peripheral Interface (SPI) is used to transmit and receive data synchronously with the MCU. Communication occurs over a fullduplex, four-wire SPI bus. The SB0410 device operates only as a slave device to the master, and requires four external pins; SI, SO,
SCLK, and CSB. All words are 16 bits long and MSB is sent first.
The SPI simultaneously turns on the serial output SO and returns the MISO return bits. When receiving, valid data is latched on the rising
edge of each SCLK pulse. The serial output data is available on the rising edge of SCLK, and transitions on the falling edge of SCLK. The
number of clock cycles occurring on the pin SCLK while the CSB pin is asserted low must be 16. If the number of clock pulses is not 16
or a parity fault, the SPI MOSI data is ignored. The SB0410 takes even parity. On next data read SO message, “Fmsg” bit sets to 1, and
other data bits sets to 0. The parity bit sets to 1. On the first SPI communication after reset, the read SO message sets to
1010101010101010.
The fault registers are double buffered. The first buffer layer latches a fault at the time the fault is detected. This inner layer buffer clears
when the fault condition is no longer present and the fault bit communicates to the MCU by a MISO response. The second layer buffer
latches the output of the inner layer buffer whenever the CSB pin transitions from low to high. The output of the second layer buffer is
transferred to the shift register after the corresponding MOSI command is received from the MCU.
SB0410
31
Analog Integrated Circuit Device Data
Freescale Semiconductor
Figure 13. SPI Timing Diagram
Table 20. SPI Timing Electrical Characteristics
VPWR = 6.0 V to 36 V, VCC5 = 4.75 V to 5.25 V, DOSV = 3.13 V to 5.25 V, TJ = -40 °C to 125 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Recommended Frequency of SPI Operation - tSPI = 1/fSPI
—
—
10
MHz
tLEAD
Falling Edge of CSB to the Rising Edge of SCLK (required setup time)
30
tSPI/2
50
ns
tLAG
Falling Edge of SCLK to the Rising Edge of CSB (required setup time)
30
tSPI/2
50
ns
No Data Time Between SPI Commands
300
—
—
ns
tWH
High Time of SCLK
45
tSPI/2
—
ns
tWL
Low Time of SCLK
45
tSPI/2
—
ns
tSU1
SI to Rising Edge of SCLK (required setup time)
15
—
—
ns
tSO(EN)
Time from Falling Edge of CSB to SO Low-impedance
—
—
30
ns
tSO(DIS)
Time from Rising Edge of CSB to SO High-impedance
—
—
30
ns
Time from Falling Edge of SCLK to SO Data_valid - 0.2xDOSV
.8xDOSV, CL = 50 pF
0.0
—
30
ns
Notes
SPI Interface Timing (19)
fSPI
tXFER_DELAY
tVALID
Notes
19. The inputs of the SPI module (SCLK, CSB, SI) are driven between 0 V and DOSV voltage.
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
6.7.2
SPI Message Structure
Table 21. SPI Message Structure
addr #
Write
Read
DEC
BIN
9
8
7
6
5
4
3
2
1
0
0
00000
0
0
0
0
0
0
0
OCM
_pd
0
0
Version
1
00001
lsd_s
in
k_dis
1
0
Manufacturing data
2
00010
3
00011
0
0
0
0
FM_
amp
FM_
EN
Stop
CL
K2
4
00100
0
0
Iclam
p
didt
FDC
L
LLC
<1>
LLC
<0>
5
00101
0
0
0
0
0
0
0
6
00110
0
0
0
0
0
0
7
00111
0
0
0
0
0
0
0
0
0
0
8
01000
0
0
0
0
0
0
0
0
0
0
X
X
X
X
Vgs_pd<9:0>
9
01001
0
0
0
0
0
0
0
X
X
X
X
TEMP<9:0>
10
01010
LSD1 duty cycle (8-bit) or current set point (10-bit)
lsd1 lsd1_ lsd1_ vds_L
_oc
op
ot
SD1
LSD1 duty cycle (8bit) or current read (10 bit)
11
01011
LSD2 duty cycle (8-bit) or current set point (10-bit)
lsd2_ lsd2_ lsd2_ vds_L
oc
op
ot
SD2
LSD2 duty cycle (8bit) or current read (10 bit)
12
01100
LSD3 duty cycle (8-bit) or current set point (10-bit)
lsd3_ lsd3_ lsd3_ vds_L
oc
op
ot
SD3
LSD3 duty cycle (8bit) or current read (10 bit)
13
01101
LSD4 duty cycle (8-bit) or current set point (10-bit)
lsd4_ lsd4_ lsd4_ vds_L
oc
op
ot
SD4
LSD4 duty cycle (8bit) or current read (10 bit)
14
01110
0
0
0
0
0
0
0
0
0
0
X
X
X
X
AD_RST1<9:0>
15
01111
0
0
0
0
0
0
0
0
0
0
X
X
X
X
AD_RST2<9:0>
16
10000
0
0
0
0
0
0
0
0
0
0
X
X
X
X
AD_RST3<9:0>
P charac
I charac
13
12
11
10
9
8
7
6
5
dosv Vcc_ Vint_ RST_ RST
_uv
uv
uv
cl k _ext
P charac
4
3
2
1
0
X
X
X
X
X
lsd_s
in
k_dis
X
X
I charac
Reserved
0
0
0
SB0410_CLK_CNT<7:0>
Vpwr
_ ov
X
CR_d CR_d
is|
is
12
34
VINT_A<9:0>
LD2_ LD_o lsd1_ lsd2_ lsd3_ lsd4_
on
n
cr er crer crer crer
VINT_D<9:0>
LD2_ LD_c PD_c LSD_
vds_l
ld_oc ld_op ld_ot
clr_flt l r_flt lr_flt clr_flt
d
vpre10<9:0>
ld2_o ld2_o ld2_o vds_l
c
p
t
d2
vpre12<9:0>
LF_PWM_14
CR_ CR_d CR_ PD_o CR_f
fb
is12 dis34
c
b
0
PD_
Vpwr FGN
OTW
_ uv
D
ot
MSB(B15) of both write and read messages is parity bit, whereas only B14 of read message is Fmsg, which show previous write message fault.
The ‘X’ bit is used for tests manufacturing.
SB0410
33
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.7.3
SPI Message Description
6.7.3.1
Message #0
Table 22. Write message
B15
B14
B13
B12
P
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
OCM_pd
02
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
0
0
0
0
0
0
0
OCM_p
d
0
0
B05
B04
B03
B02
B01
B00
RST_
ext
X
X
X
X
X
Description
Parity bit
Message Identifier: 00000
Over current Masking time of Pump pre-driver selection
Table 23. Read message
B15
B14
P
Fmsg
B13
B12
B11
B10
Bits
P
15
Fmsg
14
Version #
13: 10
dosv_uv
09
Vcc5 uv
08
Vint uv
07
RST_clk
06
RST_ext
05
B08
B07
B06
dosv_u
RST_cl
Vcc_uv Vint_uv
k
v
Version #
Field
B09
Description
Parity bit
Bit = 0
Previous transfer was valid
Bit = 1
Parity bit is not correct. Error detected during previous transfer
Version number is xxxx pass
Bit = 0
DOSV continues normal voltage
Bit = 1
DOSV was less than DOSV undervoltage threshold longer than tDVUV
Bit = 0
VCC5 continues normal voltage
Bit = 1
VCC5 was less than VCC5_uv longer tVCUV
Bit = 0
Vint_D and Vint_A continues normal voltage
Bit = 1
Vint_D or Vint_A voltage was low
Bit = 0
SB0410 internal clock is okay
Bit = 1
SB0410 internal clock fault was detected.
Bit = 0
Normal
Bit = 1
Reset from external (RSTB pin)
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
6.7.3.2
Message #1
Table 24. Write message
B15
B14
P
B13
B12
B11
B10
B09
B08
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
P charac
I charac
lsd_sink_dis
09: 06
05: 03
02
B07
B06
B05
P charac
B04
I charac
B03
B02
B01
B00
lsd_sink
_dis
1
X
Description
Parity bit
Message Identifier: 00001
BIT
P character
0111
Factor of P-characteristic = 1.2188
0110
Factor of P-characteristic = 1.1875
0101
Factor of P-characteristic = 1.1562
0100
Factor of P-characteristic = 1.125
0011
Factor of P-characteristic = 1.0938
0010
Factor of P-characteristic = 1.0625
0001
Factor of P-characteristic = 1.0312
1000
Factor of P-characteristic = 1
0000
Factor of P-characteristic = 1
1001
Factor of P-characteristic = 0.9688
1010
Factor of P-characteristic = 0.9375
1011
Factor of P-characteristic = 0.9062
1100
Factor of P-characteristic = 0.875
1101
Factor of P-characteristic = 0.8438
1110
Factor of P-characteristic = 0.8125
1111
Factor of P-characteristic = 0.7812
001
Factor of I-characteristic = 0.25
010
Factor of I-characteristic = 0.1875
011
Factor of I-characteristic = 0.1562
100
Factor of I-characteristic = 0.3125 (Imax)
000
Factor of I-characteristic = 0.125 (default)
101
Factor of I-characteristic = 0.0938
110
Factor of I-characteristic = 0.0625
111
Factor of I-characteristic = 0.0312
Bit = 0
LSD sink current for open detection is enabled (default mode)
Bit = 1
LSD sink current for open detection is disabled
SB0410
35
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 25. Read message
B15
B14
P
Fmsg
B13
B12
B11
B10
B09
B08
Manufacturing data
B07
B06
B05
P charac
B04
B02
B01
B00
lsd_sink
_dis
X
X
B03
B02
B01
B00
Stop
CLK
2
0
0
0
I charac
Field
Bits
P
15
Fmsg
14
Manufacturing data
13: 10
Could be used for traceability (same as version #)
P charac
09: 06
Feedback of P charac
I charac
05: 03
Feedback of I charac
lsd_sink_dis
02
6.7.3.3
B03
Description
Parity bit
Bit = 0
Previous transfer was valid.
Bit = 1
Parity bit is not correct.
Error detected during previous transfer.
Feedback of lsd_sink_dis
Message #2
Reserved
6.7.3.4
Message #3
Table 26. Write message
B15
B14
B13
P
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14:10
FM_amp
05
FM_EN
04
StopCLK2
03
B09
B08
B07
B06
0
0
0
0
B05
B04
FM_am
FM_EN
p
Description
Parity bit
Message Identifier: 00011
Bit = 0
Frequency modulation band 1
Bit = 1
Frequency modulation band 2
Bit = 0
Frequency of Main/Aux oscillator clocks is fixed
Bit = 1
Frequency of Main/Aux oscillator clocks is modulated by the frequency defined by
FM_amp
Bit = 0
SB0410 internal clock monitoring function is enabled
Bit = 1
SB0410 internal clock monitoring function is disabled
Table 27. Read message
B15
B14
P
Fmsg
B13
B12
B11
B10
B09
B08
SB0410_CLK_CNT<7:0>
B07
B06
B05
B04
Vpwr ov
X
B03
B02
Vpwr uv FGND
B01
B00
OTW
PD_ot
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
Field
Bits
P
15
Fmsg
14
SB0410_CLK_CNT<7:0>
13: 06
Vpwr_ov
05
Vpwr_uv
03
FGND
02
OTW
01
PD_ot
00
6.7.3.5
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Monitoring result from SB0410 internal clock(?)
Bit = 0
Normal
Bit = 1
VPWR overvoltage
Bit = 0
Normal
Bit = 1
VPWR undervoltage
Bit = 0
Normal
Bit = 1
GND _D loss detection
Bit = 0
Normal
Bit = 1
Overtemperature warning
Bit = 0
Normal
Bit = 1
Overtemperature warning on the motor pump pre-driver
Message #4
Table 28. Write message
B15
B14
P
B13
B12
B11
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
Iclamp
didt
07
06
B10
B09
B08
B07
B06
B05
B04
B03
B02
0
0
Iclamp
didt
FDCL
LLC
<1>
LLC
<0>
CR_fb
B01
B00
CR_dis CR_dis
12
34
Description
Parity bit
Message Identifier: 00100
Bit = 0
Integrator limit is 0x03FF
Bit = 1
Integrator limit is 0x07FF
Bit = 0
Rise / Fall time of LSD is long (tr/tf_CR1)
Bit = 1
Rise / Fall time of LSD is short (tr/tf_CR2)
Bit = 0
The first duty cycle is controlled by current
FDCL
05
Bit = 1
First duty cycle from off state to a target value is limited to a fixed duty cycle.
(Fixed value is the duty cycle which a target current is transformed in duty cycle, lowest value
is 10%)
SB0410
37
Analog Integrated Circuit Device Data
Freescale Semiconductor
LLC
04:03
CR_fb
02
Bit = 00
Minimum duty cycle (DC) is 10%
The measurement is done at Ton/2
Bit = 01
Minimum duty cycle (DC) is 3.12%
For DC > 10%, the measurement is done at Ton/2.
For 3.12% < DC < 10%, the measurement is done at the maximum value
between Ton/2 and 3.12%
Bit = 10
Bit = 10
Minimum duty cycle (DC) is: 3.12% + 1.56% every two cycles
For DC > 10%, the measurement is done at Ton/2.
For 3.12% < DC < 10% the regulation current approach up to 3.12% of DC
and the measurement is done at the maximum value between Ton/2 and
3.12%
For 1.56% < DC < 3.12%, 3.12% of DC and 1.56%.
DC are forced every two cycles and no measurement is done during 1.56%
of DC.
Bit = 11
Minimum duty cycle (DC) is: 3.12% + skipping DC every two cycles
For DC > 10%, the measurement is done at Ton/2.
For 3.12% < DC < 10% the regulation current approach up to 3.12% of DC
and the measurement is done at the maximum value between Ton/2 of DC
and 3.12%
For DC < 3.12%, the regulation current forces 3.12% and skipping every
two cycles and no measurement is done during the skipping mode.
Bit = 0
LSDx Feedback = SPI written value
Bit = 1
LSDx Feedback = output
CR_fb = 0
CR_dis12
01
CR_dis34
00
CR_fb = 1
CR_dis12 = 0
LSD1,2 Current regulation
LSD1,2 Current regulation
CR_dis12 = 1
LSD1,2 PWM
LSD1,2 PWM
CR_dis34 = 0
LSD3,4 Current regulation
LSD3,4 Current regulation
CR_dis34 = 1
LSD3,4 PWM
LSD3,4 PWM
Table 29. Read message
B15
B14
B13
B12
P
Fmsg
PD_oc
CR_fb
B11
B10
B09
B08
B07
B06
CR_dis CR_dis
12
34
B05
B04
B03
B02
B01
B00
VINT_A<9:0>
Field
Bits
Description
P
15
Fmsg
14
PD_oc
13
CR_fb
12
Feedback of CR_fb
CR_dis12
11
Feedback of CR_dis12
CR_dis34
10
Feedback of CR_dis34
VINT_A<9:0>
09:00
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Bit = 0
Normal
Bit = 1
Over current detected on the motor pump pre-driver
10-bit ADC of Analog internal supply
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
38
6.7.3.6
Message #5
Table 30. Write message
B15
B14
B13
P
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
LD2_on
01
LD_on
00
B09
B08
B07
B06
B05
B04
B03
B02
0
0
0
0
0
0
0
0
B04
B03
B02
B01
B00
LD2_on LD_on
Description
Parity bit
Message Identifier: 00101
Bits = 0
Low-side is off
Bits = 1
Low-side turn on
Bits = 0
Low-side is off
Bits = 1
Low-side turn on
Table 31. Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
lsd1_
crer
lsd2_
crer
lsd3_
crer
lsd4_
crer
Field
Bits
P
15
Fmsg
14
lsd1_crer
13
lsd2_crer
12
lsd3_crer
11
lsd4_crer
10
VINT_D<9:0>
09:00
6.7.3.7
B09
B08
B07
B06
B05
B01
B00
VINT_D<9:0>
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Bit = 0
Normal
Bit = 1
Current regulation error detection of LSD1
Bit = 0
Normal
Bit = 1
Current regulation error detection of LSD2
Bit = 0
Normal
Bit = 1
Current regulation error detection of LSD3
Bit = 0
Normal
Bit = 1
Current regulation error detection of LSD4
10-bit ADC internal supply
Message #6
Table 32. Write message
B15
P
B14
B13
B12
MSG_ID
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
0
0
0
0
0
0
0
LD_
clr_flt
PD_
clr_flt
LSD_
clr_flt
SB0410
39
Analog Integrated Circuit Device Data
Freescale Semiconductor
Field
Bits
P
15
MSG_ID
14: 10
LD2_clr_flt
03
LD_clr_flt
02
PD_clr_flt
01
LSD_clr_flt
00
Description
Parity bit
Message Identifier: 00110
Bit = 0
LD_oc and LD_ot are conserved (default mode)
Bit = 1
Clear LD_oc and LD_ot
Bit = 0
LD_oc and LD_ot are conserved (default mode)
Bit = 1
Clear LD_oc and LD_ot
Bit = 0
PD_oc is conserved (default mode)
Bit = 1
Clear PD_oc
Bit = 0
All LSDx_oc and LSDx_ot are conserved (default mode)
Bit = 1
Clear All LSDx_oc and LSDx_ot
Table 33. Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
ld_oc
ld_op
ld_ot
vds_ld
Field
Bits
P
15
Fmsg
14
ld_oc
13
ld_op
12
ld_ot
11
vds_ld
10
vpre10<9:0>
09:00
6.7.3.8
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
vpre10<9:0>
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Bit = 0
Normal
Bit = 1
Overcurrent shut down of low-side
Bit = 0
Normal
Bit = 1
Open load detection of low-side
Bit = 0
Normal
Bit = 1
Overtemperature shut down of low-side
Bit = 0
Normal
Bit = 1
Vds detection of low-side (information only)
10-bit ADC of vpre10
Message #7
Table 34. Write message
B15
B14
P
B13
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
0
0
0
0
0
0
0
0
0
0
Description
Parity bit
Message Identifier: 00111
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
40
Table 35. Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
ld2_oc
ld2_op
ld2_ot
vds_ld2
Field
Bits
P
15
Fmsg
14
ld2_oc
13
ld2_op
12
ld2_ot
11
vds_ld
10
vpre12<9:0>
09:00
6.7.3.9
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
vpre12<9:0>
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Bit = 0
Normal
Bit = 1
Overcurrent shut down of low-side
Bit = 0
Normal
Bit = 1
Open load detection of low-side
Bit = 0
Normal
Bit = 1
Overtemperature shut down of low-side
Bit = 0
Normal
Bit = 1
Vds detection of low-side (information only)
10-bit ADC of vpre12
Message #8
Table 36. Write message
B15
B14
B13
P
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
0
0
0
0
0
0
0
0
0
0
B03
B02
B01
B00
Description
Parity bit
Message Identifier: 01000
Table 37. Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
X
X
X
X
Field
Bits
P
15
Fmsg
14
vgs_pd<9:0>
09:00
B09
B08
B07
B06
B05
B04
vgs_pd<9:0>
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
10-bit ADC of vgs_pd
SB0410
41
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.7.3.10
Message #9
Table 38. Write message
B15
B14
B13
P
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
LF_PWM_14
B09
B08
B07
B06
0
0
0
0
B05
B04
B03
LF_PWM_14
B02
B01
B00
0
0
0
B02
B01
B00
B02
B01
B00
Description
Parity bit
Message Identifier: 01001
05:03
Bit = 000
Output PWM frequency of LSD(1~4)= 3.9 kHz
Bit = 001
Output PWM frequency of LSD(1~4)= 4.5 kHz
Bit = 010
Output PWM frequency of LSD(1~4)= 5.0 kHz
Bit = 011
Output PWM frequency of LSD(1~4)= 4.2 kHz
Bit = 100
Output PWM frequency of LSD(1~4)= 3.6 kHz
Bit = 101
Output PWM frequency of LSD(1~4)= 3.4 kHz
Bit = 110
Output PWM frequency of LSD(1~4)= 3.2 kHz
Bit = 111
Output PWM frequency of LSD(1~4)= 3.0 kHz
Table 39. Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
X
X
X
X
Field
Bits
P
15
Fmsg
14
TEMP<9:0>
09:00
6.7.3.11
B09
B08
B07
B06
B05
B04
B03
TEMP<9:0>
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
10-bit ADC of average die temperature
Message #10
Table 40. Write message
B15
P
B14
B13
B12
B11
MSG_ID
B10
B09
B08
B07
B06
B05
B04
B03
LSD1 duty cycle (8-bit) or current set point (10-bit)
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
Field
Bits
P
15
MSG_ID
14: 10
LSD1 duty cycle (8-bit) or
current set point(10-bit)
Description
Parity bit
Message Identifier: 01010
CR_fb=0
CR_fb=1
CR_dis12= 0
LSD1, 2 current regulation
Write current target
(10 bits, 0 to 2.25 A)
LSD1,2 current regulation
Write current target
(10 bits, 0 to 2.25 A)
CR_dis12= 1
LSD1, 2 PWM
Write programmed duty cycle
(8 bits at 0%, 100% and 10% to 90%)
LSD1[1:0]=XX
LSD1,2 PWM
Write programmed duty cycle
(8 bits at 0%, 100% and 10% to 90%)
LSD1[1:0]=XX
09:00
Table 41. Read message
B15
B14
P
Fmsg
B13
B12
B11
B10
lsd1_ oc lsd1_op lsd1_ot
Field
Bits
P
15
Fmsg
14
lsd1_ oc
13
lsd1_op
12
lsd1_ot
11
vds_LSD1
10
LSD1 duty cycle (8-bit) or
current read (10-bit)
B09
B08
vds_
LSD1
B07
B06
B05
B04
B03
B02
B01
B00
LSD1 duty cycle (8-bit) or current read (10-bit)
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Bit = 0
Normal
Bit = 1
Overcurrent shutdown of LSD1
Bit = 0
Normal
Bit = 1
Open Load detection of LSD1
Bit = 0
Normal
Bit = 1
Overtemperature shutdown of LSD1
Bit = 0
Normal
Bit = 1
VDS detection of LSD1 (information only)
CR_fb=0
CR_fb=1
CR_dis12= 0
LSD1,2 current regulation
Read current target
(to check SPI write)
(10 bits, 0 to 2.25 A)
LSD1,2 current regulation
Output duty cycle value for gate driver
(8 bits, for the range to 100%)
CR_dis12= 1
LSD1,2 PWM
Read programmed PWM duty cycle (to
check SPI write)
(8 bits at 0%, 100% and 10% to 90%)
LSD(1~2)[1:0]=00
LSD1,2 PWM
Read hardware ADC current value
(10 bits for the range to 4.5A)
09:00
SB0410
43
Analog Integrated Circuit Device Data
Freescale Semiconductor
6.7.3.12
Message #11
Table 42. Write message
B15
B14
B13
P
B12
B11
B10
B09
B08
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
LSD2 duty cycle (8-bit) or
current set point(10-bit)
B07
B06
B05
B04
B03
B02
B01
B00
LSD2 duty cycle (8bit) or current set point (10-bit)
Description
Parity bit
Message Identifier: 01011
CR_fb=0
CR_fb=1
CR_dis12= 0
LSD1,2 current regulation
Write current target
(10 bits, 0 to 2.25 A)
LSD1,2 current regulation
Write current target
(10 bits, 0 to 2.25 A)
CR_dis12= 1
LSD1,2 PWM
Write programmed duty cycle
(8 bits at 0%, 100% and 10% to 90%)
LSD2[1:0]=XX
LSD1,2 PWM
Write programmed duty cycle
(8 bits at 0%, 100% and 10% to 90%)
LSD2[1:0]=XX
09:00
Table 43. Read message
B15
B14
P
Fmsg
B13
B12
B11
B10
lsd2_ oc lsd2_op lsd2_ot
Field
Bits
P
15
Fmsg
14
lsd2_ oc
13
lsd2_op
12
lsd2_ot
11
vds_LSD2
10
LSD2 duty cycle (8-bit) or
current read (10-bit)
B09
B08
vds_LS
D2
B07
B06
B05
B04
B03
B02
B01
B00
LSD2 duty cycle (8-bit) or current read (10-bit)
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Bit = 0
Normal
Bit = 1
Overcurrent shutdown of LSD2
Bit = 0
Normal
Bit = 1
OpenLoad detection of LSD2
Bit = 0
Normal
Bit = 1
Overtemperature shutdown of LSD2
Bit = 0
Normal
Bit = 1
VDS detection of LSD2 (information only)
CR_fb = 0
CR_fb=1
CR_dis12= 0
LSD1,2 current regulation
Read current target
(to check SPI write)
(10 bits, 0 to 2.25 A)
LSD1,2 current regulation
Output duty cycle value for gate driver
(8 bits, for the range to 100%)
CR_dis12= 1
LSD1,2 PWM
Read programmed PWM duty cycle (to
check SPI write)
(8 bits at 0%, 100% and 10% to 90%)
LSD(1~2)[1:0]=00
LSD1,2 PWM
Read hardware ADC current value
(10 bits for the range to 4.5 A)
09:00
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
44
6.7.3.13
Message #12
Table 44. Write message
B15
B14
B13
P
B12
B11
B10
B09
B08
MSG_ID
Field
B07
B05
B04
B03
B02
B01
B00
LSD3 duty cycle (8-bit) or current set point (10-bit)
Bits
Description
P
15
Parity bit
MSG_ID
14: 10
Message Identifier: 01100
LSD3 duty cycle (8-bit) or
current set point(10-bit)
B06
CR_fb=0
CR_fb=1
CR_dis34= 0
LSD3,4 current regulation
Write current target
(10 bits, 0 to 2.25 A)
LSD3,4 current regulation
Write current target
(10 bits, 0 to 2.25 A)
CR_dis34= 1
LSD3,4 PWM
Write programmed duty cycle
(8 bits at 0%, 100% and 10% to
90%)
LSD3[1:0]=XX
LSD3,4 PWM
Write programmed duty cycle
(8 bits at 0%, 100% and 10% to 90%)
LSD3[1:0]=XX
09:00
Table 45. Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
lsd3_ oc
lsd3_
op
lsd3_ot
vds_
LSD3
6.7.3.14
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
B01
B00
LSD3 duty cycle (8-bit) or current read (10-bit)
Message #13
Table 46. Write message
B15
B14
B13
P
B12
B11
B10
B09
B08
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
LSD4 duty cycle (8-bit) or
current set point (10-bit)
B07
B06
B05
B04
B03
B02
LSD4 duty cycle (8-bit) or current set point (10-bit)
Description
Parity bit
Message Identifier: 01101
CR_fb=0
CR_fb=1
CR_dis34= 0
LSD3, 4 current regulation
Write current target
(10 bits for the range to 2.25 A)
LSD3, 4 current regulation
Write current target
(10 bits for the range to 2.25 A)
CR_dis34= 1
LSD3,4 PWM
Write programmed duty cycle
(8 bits for the range to 100%)
LSD4[1:0]=XX
LSD3, 4 PWM
Write programmed duty cycle
(8 bits for the range to 100%)
LSD4[1:0]=XX
09:00
SB0410
45
Analog Integrated Circuit Device Data
Freescale Semiconductor
Read message
B15
B14
P
Fmsg
B13
B12
B11
lsd4_ oc lsd4_op lsd4_ot
Field
Bits
P
15
Fmsg
14
lsd4_ oc
13
lsd4_op
12
lsd4_ot
11
vds_LSD4
10
LSD4 duty cycle (8-bit) or
current read (10-bit)
6.7.3.15
B10
B09
B08
B07
vds_LS
D4
B06
B05
B04
B03
B02
B01
B00
LSD4 duty cycle (8-bit) or current read (10-bit)
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
Bit = 0
Normal
Bit = 1
Overcurrent shutdown of LSD4
Bit = 0
Normal
Bit = 1
OpenLoad detection of LSD4
Bit = 0
Normal
Bit = 1
Overtemperature shutdown of LSD4
Bit = 0
Normal
Bit = 1
VDS detection of LSD4 (information only)
CR_fb=0
CR_fb=1
CR_dis34= 0
LSD3,4 current regulation
Read current target
(to check SPI write)
(10 bits, 0 to 2.25 A)
LSD3,4 current regulation
Output duty cycle value for gate driver
(8 bits, for the range to 100%)
CR_dis34= 1
LSD3,4 PWM
Read programmed PWM duty cycle (to
check SPI write)
(8 bits at 0%, 100% and 10% to 90%)
LSD(3~4)[1:0]=00
LSD3,4 PWM
Read hardware ADC current value
(10 bits for the range to 4.5 A)
09:00
Message #14
Table 47. Write message
B15
B14
B13
P
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
0
0
0
0
0
0
0
0
0
0
B04
B03
B02
B01
B00
Description
Parity bit
Message Identifier: 01110
Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
x
x
x
x
B09
B08
B07
B06
B05
AD_RST1<9:0>
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
46
Field
Bits
P
15
Fmsg
14
AD_RST1<9:0>
09:00
6.7.3.16
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
10-bit ADC of
ADIN1
AD_RST1<9:0>
Message #15
Table 48. Write message
B15
B14
B13
P
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
0
0
0
0
0
0
0
0
0
0
B04
B03
B02
B01
B00
Description
Parity bit
Message Identifier: 01111
Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
x
x
x
x
Field
Bits
P
15
Fmsg
14
AD_RST2<9:0>
09:00
6.7.3.17
B09
B08
B07
B06
B05
AD_RST2<9:0>
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
10-bit ADC of
ADIN2
AD_RST2<9:0>
Message #16
Table 49. Write message
B15
B14
P
B13
B12
B11
B10
MSG_ID
Field
Bits
P
15
MSG_ID
14: 10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
0
0
0
0
0
0
0
0
0
0
Description
Parity bit
Message Identifier: 10000
SB0410
47
Analog Integrated Circuit Device Data
Freescale Semiconductor
Read message
B15
B14
B13
B12
B11
B10
P
Fmsg
x
x
x
x
Field
Bits
P
15
Fmsg
14
AD_RST3<9:0>
09:00
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
AD_RST3<9:0>
Description
Parity bit
Bit = 0
Parity bit is correct. Previous transfer was valid.
Bit = 1
Parity bit is not correct. Error detected during previous transfer.
10-bit ADC of
ADIN3
AD_RST3<9:0>
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
48
7
Typical Applications
7.1
Application Diagrams
This section presents a typical Industrial applications schematic using SB0410, as shown in Figure 14.
Up to 36 V
DC
10µ
5.0 V Voltage
Regulator
Vpwr
Faults
Management
&
State
Machine
3.3 V Voltage
Regulator
Vcc3.3
Vcc5
DOSV
SI, SO, SLK, CSB
4
Boostrap
Low-side Driver
with protection and
diagnostic
On/Off
16-bit SPI
MCU
RSTB
Charge
Pump
Logic
Rds(on) 14ohms @ 150°C
Valve Low-side Drivers
with protection
Solenoid and
Solenoid
Low-Side
Drivers with
diagnostic
Solenoid
Low-Side
Drivers
with
protection
and
diagnostic
Current
Low-Side
Drivers with
protection
regulation
up and diagnostic
protection and diagnostic
to 2.25 A
RDS(on) 225m at 150°C
PDI
ADIN1
ADIN2
ADIN3
10 bit
Analog to
Digital
Converter
with Mux
Up to 36 V
DC
Half Bridge Pre-driver
up to 16 kHz
with protection and
diagnostic
M
MC34SB0410
Figure 14. Industrial Valves and Pump Control Unit Simplified Diagram
SB0410
49
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
Packaging
8.1
Package Mechanical Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and
perform a keyword search for the drawing’s document number.
Package
Suffix
7 x 7, 48-Pin LQFP Exposed Pad, with 0.5 mm
pitch, and a 4.5 x 4.5 exposed pad
AE
Package Outline Drawing Number
98ASA00173D
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
50
SB0410
51
Analog Integrated Circuit Device Data
Freescale Semiconductor
SB0410
Analog Integrated Circuit Device Data
Freescale Semiconductor
52
9
Revision History
Revision
Date
1.0
11/2014
• Initial release
4/2015
• Changed document status to Advance Information.
• Changed MC to PC in Orderable Part Variations
5/2015
• Updated document title
5/2015
• Updated Table 21, Table 30, Table 32, and Table 33
2.0
3.0
Description of Changes
SB0410
53
Analog Integrated Circuit Device Data
Freescale Semiconductor
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Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by
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property of their respective owners.
© 2015 Freescale Semiconductor, Inc.
Document Number: MC34SB0410
Rev. 3.0
5/2015
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