Data Sheet

NXP Semiconductors
Technical Data
Document Number: MC33660
Rev 6.0, 1/2016
ISO K Line Serial Link Interface
The 33660 is a serial link bus interface device designed to provide bi-directional
half-duplex communication interfacing in automotive diagnostic applications. It
is designed to interface between the vehicle’s on-board microcontroller, and
systems off-board the vehicle via the special ISO K line. The 33660 is designed
to meet the Diagnostic Systems ISO9141 specification. The device’s K line bus
driver’s output is fully protected against bus shorts and over-temperature
conditions.
The 33660 derives its robustness to temperature and voltage extremes by being
built on a SMARTMOS process, incorporating CMOS logic, bipolar/MOS analog
circuitry, and DMOS power FETs. Although the 33660 was principally designed
for automotive applications, it is suited for other serial communication
applications. It is parametrically specified over an ambient temperature range of
-40 ºC ≤ TA ≤ 125 ºC and 8.0 V ≤ VBB ≤ 18 V supply. The economical SO-8
surface-mount plastic package makes the 33660 very cost effective.
Features
• Operates over a wide supply voltage of 8.0 V to 18 V
• Operating temperature of -40 °C to 125 °C
• Interfaces directly to standard CMOS microprocessors
• ISO K line pin protected against shorts to battery
• Thermal shutdown with hysteresis
• ISO K line pin capable of high currents
• ISO K line can be driven with up to 10 nF of parasitic capacitance
• 8.0 kV ESD protection attainable with few additional components
• Standby mode: no VBAT current drain with VDD at 5.0 V
• Low current drain during operation with VDD at 5.0 V
33660
ISO9141 PHYSICAL INTERFACE
EF SUFFIX (PB-FREE)
98ASB42564B
8-PIN SOICN
Applications
• Farm Equipment
• Automotive Systems
• Industrial Equipment
• Robotic Equipment
• Applications where Module-to-Module
Communications are required
• Marine and Aircraft Networks
+VBAT
VDD
33660
VDD
VDD
VBB
CEN
RX
TX
ISO
MCU
Dx
SCIRxD
SCITxD
ISO K-LINE
TXD
GND
Figure 1. 33660 Simplified Application Diagram
© NXP Semiconductors, N.V, 2016. All rights reserved.
RXD
1
Orderable Parts
Table 1. Orderable Part Variations
Part Number (1)
Temperature
(TA)
Package
Parameter
Symbol
Condition
33660
33660B (2)
VBB(5a)
Pulse 5a
470 ohm series resistor and
100 nF capacitor to GND on VBB
Pulse 5b
470 ohm series resistor and
100 nF capacitor to GND on VBB
–
82 V
8-SOICN
VBB Load Dump
Peak Voltage (in
accordance with
ISO 7637-2 & ISO
7637-3)
45 V
45 V
–
±25000 V
MC33660EF
-40 °C to
125 °C
MC33660BEF
Module Level ESD
(Air Discharge,
Powered)
VBB(5b)
VESD4
33 V zener diode and 470 pF
capacitor to GND on ISO
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
2. Recommended for all new designs
33660
2
Analog Integrated Circuit Device Data
NXP Semiconductors
2
Internal Block Diagram
VBB
3.0 kΩ
60 V
600 kΩ
20 V
* Only applies to 33660B
CEN
10 V
125 kΩ
RX
RHYS
10 V
55 kΩ
550 kΩ
ISO
45 V
Master
Bias
110 kΩ
55 V
Thermal
Shutdown
VDD
2.0 kΩ
10 V
125 kΩ
TX
10 V
GND
Figure 2. 33660 Simplified Internal Block Diagram
33660
Analog Integrated Circuit Device Data
NXP Semiconductors
3
3
Pin Connections
3.1
Pinout Diagram
VBB
11
88
NC
22
77
VDD
GND
33
66
RX
ISO
44
55
TX
CEN
Figure 3. 33660 Pin Connections
3.2
Pin Definitions
Table 2. 33660 Pin Definitions
Pin Number
Pin Name
1
VBB
Battery power through external resistor and diode.
Definition
2
NC
Not to be connected. (3)
3
GND
4
ISO
Bus connection.
5
TX
Logic level input for data to be transmitted on the bus.
6
RX
Logic output of data received on the bus.
7
VDD
Logic power source input.
8
CEN
Chip enable. Logic “1” for active state. Logic “0” for sleep state.
Common signal and power return.
Notes
3. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.
33660
4
Analog Integrated Circuit Device Data
NXP Semiconductors
4
Electrical Characteristics
4.1
Maximum Ratings
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol
VDD
VBB(5a)
VBB(5b)
VISO
VESD1
VESD2
Rating
VDD DC Supply Voltage
Unit
-0.3 to 7.0
V
VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO
7637-3)
• Pulse 5a - 33660B only
• Pulse 5b
82
45
ISO Pin Load Dump Peak Voltage
40
ESD Voltage
• Human Body Model
• Machine Model
33660
33660B
VESD3-1
VESD3-2
Value
• Charge Device Model
Corner Pins
Notes
V
V
(4)
(5)
(6)
±2000
(6)
±150
±200
±750
±500
V
(6)
All other Pins
VESD4
• Module Level ESD (Air Discharge, Powered)
33660B only
(7)
±25000
ISO pin with 33 V zener diode and 470 pF capacitor to GND ECLAMP
10
mJ
Storage Temperature
-55 to +150
°C
TC
Operating Case Temperature
-40 to +125
°C
TJ
Operating Junction Temperature
-40 to +150
°C
PD
Power Dissipation TA = 25 °C
TSTG
TPPRT
RθJA
ISO Clamp Energy
Peak Package Reflow Temperature During Reflow
Thermal Resistance: Junction-to-Ambient
100
mW
Note 10.
°C
150
°C/W
(8)
(9), (10)
Notes
4. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain within
specified parametric limits during this duration.
5. ESD data available upon request.
6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance
with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), ESD3 testing is performed in accordance with the Charge Device Model (CZAP = 4.0 pF).
7.
8.
9.
10.
ESD4 testing is performed in accordance with ISO 10605 ESD model (C = 330 pF, R = 2.0 kΩ). ESD discharges start at ±5.0 kV and go up to
±25 kV in increments of 5.0 kV. There are two positions for discharges: 8.0 cm cable from ISO connector, 85 cm cable from ISO connector. There
are 10 ESD discharges per voltage at each cable position at a minimum of 1.0 s intervals. Remaining charge is not bled off after every discharge.
Nonrepetitive clamping capability at 25 °C.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature
and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to
view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33660
Analog Integrated Circuit Device Data
NXP Semiconductors
5
4.2
Static Electrical Characteristics
Table 4. Static Electrical Characteristics
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
Notes
POWER AND CONTROL
IDD(SS)
VDD Sleep State Current
• Tx = 0.8 VDD, CEN = 0.3 VDD
–
–
0.1
mA
IDD(Q)
VDD Quiescent Operating Current
• Tx = 0.2 VDD, CEN = 0.7 VDD
–
–
1.0
mA
IBB(SS)
VBB Sleep State Current
• VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD
–
–
50
µA
IBB(Q)
VBB Quiescent Operating Current
• TX = 0.2 VDD, CEN = 0.7 VDD
–
–
1.0
mA
0.7 VDD
–
–
–
–
0.3 VDD
V
(11)
VIH(CEN)
VIL(CEN)
Chip Enable
• Input High Voltage Threshold
• Input Low Voltage Threshold
IPD(CEN)
Chip Enable Pull-down Current
2.0
–
40
µA
(13)
VIL(TX)
TX Input Low Voltage Threshold
• RISO = 510 Ω
–
–
0.3 x VDD
V
(14)
VIH(TX)
TX Input High Voltage Threshold
• RISO = 510 Ω
0.7 x VDD
–
–
V
(15)
IPU(TX)
TX Pull-up Current
-40
–
-2.0
µA
(16)
VOL(RX)
RX Output Low Voltage Threshold
• RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA
–
–
0.2 VDD
V
VOH(RX)
RX Output High Voltage Threshold
• RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA
0.8 VDD
–
–
V
150
170
–
°C
TLIM
Thermal Shutdown
(12)
(17)
ISO I/O
VIL(ISO)
Input Low Voltage Threshold
• RISO = 510 Ω, TX = 0.8 VDD
–
–
0.4 x VBB
V
VIH(ISO)
Input High Voltage Threshold
• RISO = 510 Ω, TX = 0.8 VDD
0.7 x VBB
–
–
V
Input Voltage Hysteresis
0.05 x VBB
–
0.1 x VBB
V
-5.0
–
-140
µA
50
–
200
mA
VHYS(ISO)
IPU(ISO)
Internal Pull-up Current
• RISO = ∞ Ω, TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V
ISC(ISO)
Short-circuit Current Limit
• RISO = 0 Ω, TX = 0.4 VDD, VISO = VBB
Notes
11. When IBB transitions to >100 µA.
12.
When IBB transitions to <100 µA.
13.
Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD.
14.
Measured by ramping TX down from 0.8 VDD and noting TX value at which ISO falls below 0.2 VBB.
15.
Measured by ramping TX up from 0.2 VDD and noting the value at which ISO rises above 0.9 VBB.
16.
Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD.
17.
Thermal Shutdown performance (TLIM) is guaranteed by design, but not production tested.
33660
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Analog Integrated Circuit Device Data
NXP Semiconductors
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
–
–
0.1 x VBB
V
0.95 x VBB
–
–
V
Notes
ISO I/O (CONTINUED)
VOL(ISO)
Output Low Voltage
• RISO = 510 Ω, TX = 0.2 VDD
VOH(ISO)
Output High Voltage
• RISO = ∞ Ω, TX = 0.8 VDD
4.3
Dynamic Electrical Characteristics
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted.
Symbol
tFALL(ISO)
tPD(ISO)
Characteristic
Fall Time
• RISO = 510 Ω to VBB, CISO = 10 nF to Ground
ISO Propagation Delay
• High to Low: RISO = 510 Ω, CISO = 500 pF
• Low to High: RISO = 510 Ω, CISO = 500 pF
Min.
Typ.
Max.
Unit
–
–
2.0
µs
–
–
–
–
2.0
2.0
µs
(18)
(19)
(20)
(21)
Notes
18. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB.
19.
Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay.
20.
Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIH(Tx) until VISO reaches 0.3 VBB.
21.
Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIL(Tx) until VISO reaches 0.7 VBB.
Electrical Performance Curves
VIL and VIH, INPUT THRESHOLD (RATIO)
4.4
0.6
0.575
0.55
VIH; VDD = 5.25 V, VBB =
18 V
VIH; VDD = 4.75 V, VBB =
8.0 V
0.525
0.5
0.475
-50
VIL; VDD = 5.25 V, VBB =
18 V
VIL; VDD = 4.75 V, VBB =
8.0 V
0
50
100
150
TA, AMBIENT TEMPERATURE (°C)
Figure 4. ISO Input Threshold/VBB vs. Temperature
33660
Analog Integrated Circuit Device Data
NXP Semiconductors
7
tfall(ISO), ISO FALL TIME (µs)
0.95
0.9
VDD = 5.25 V, VBB = 18 V
0.85
0.8
0.75
VDD = 4.75 V, VBB = 8.0 V
0.7
0.65
-50
0
50
100
150
TA, AMBIENT TEMPERATURE (°C)
VOL and VOH, ISO OUTPUT (RATIO)
Figure 5. ISO Output/VBB vs. Temperature
1.2
VOH
1.0
0.8
VDD = 4.75 V, VBB = 8.0 V
and
VDD = 5.25 V, VBB = 18 V
0.6
0.4
0.2
VOL
0
-50
0
50
100
150
TA, AMBIENT TEMPERATURE (°C)
tPD(ISO), PROPAGATION DELAY (µs)
Figure 6. ISO Fall Time vs. Temperature
0.7
VDD = 5.25 V, VBB = 18 V
PdH-L
0.6
VDD = 4.75 V, VBB = 8.0 V
0.5
0.4
0.3
VDD = 5.25 V, VBB = 18 V
0.2
-50
PdL-H
VDD = 4.75 V, VBB = 8.0 V
0
50
100
150
TA, AMBIENT TEMPERATURE (°C)
Figure 7. ISO Propagation Delay vs. Temperature
33660
8
Analog Integrated Circuit Device Data
NXP Semiconductors
5
Typical Applications
5.1
Introduction
The 33660 is a serial link bus interface device conforming to the ISO 9141 physical bus specification. The device is designed for
automotive environment usage, compliant with On-board Diagnostics (OBD) requirements set forth by the California Air Resources Board
(CARB) using the ISO K line. The device does not incorporate an ISO L line. It provides bi-directional half-duplex communications
interfacing from a microcontroller to the communication bus. The 33660 incorporates circuitry to interface the digital translations from 5.0 V
microcontroller logic levels to battery level logic, and from battery level logic to 5.0 V logic levels. The 33660 is built using Freescale
Semiconductor’s SMARTMOS process and is packaged in an 8-pin plastic SOIC.
5.2
Functional Description
The 33660 transforms 5.0 V microcontroller logic signals to battery level logic signals and vice versa. The maximum data rate is set by
the rise and fall time. The fall time is set by the output driver. The rise time is set by the bus capacitance and the pull-up resistors on the
bus. The fall time of the 33660 allows data rates up to 150 kbps using a 30 percent maximum bit time transition value. The serial link
interface remains fully functional over a battery voltage range of 6.0 V to 18 V. The device is parametrically specified over a dynamic VBB
voltage range of 8.0 V to 18 V.
Required input levels from the microcontroller are ratio-metric with the VDD voltage normally used to power the microcontroller. This
enhances the 33660’s ability to remain in harmony with the RX and TX control input signals of the microcontroller. The RX and TX control
inputs are compatible with standard 5.0 V CMOS circuitry. For fault tolerant purposes the TX input from the microcontroller has an internal
passive pull-up to VDD, while the CEN input has an internal passive pull-down to ground.
A pull-up to battery is internally provided as well as an active data pull-down. The internal active pull-down is current-limit protected against
shorts to battery, and further protected by thermal shutdown. Typical applications have reverse battery protection by the incorporation of
an external 510 Ω pull-up resistor and a diode to battery.
Reverse battery protection of the device is provided by the use of a reverse battery blocking diode (See “D” in the Typical Application
Diagram on page 9). Battery line transient protection of the device is provided for by using a 45 V zener and a 500 Ω resistor connected
to the VBB source, as shown in the same diagram. Device ESD protection from the communication lines exiting the module is through the
use of the capacitor connected to the VBB device pin, and the capacitor used in conjunction with the 27 V zener connected to the ISO pin.
+VBAT
On-Board Diagnostic Link
D(1)
+VDD = 5.0 V
MCU
33660
VBB
VCC
1.0 nF
Dx
VDD
45 V(2)
500 Ω(2)
10 nF(3)
510 Ω
CEN ISO
SCIRxD
RX
SCITxD
TX
Service Scan Tool
or
End of Production Line
Programming
or
System Checking
5.0 nF(3)
27 V(3)
ISO
K Line
TxD
RxD
GND
Components necessary for Reverse Battery (1), Overvoltage Transient (2), and 8.0 kV
ESD Protection (3) in a metal module case.
Figure 8. Typical Application Diagram
33660
Analog Integrated Circuit Device Data
NXP Semiconductors
9
6
Packaging
6.1
Package Mechanical Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.NXP.com and
perform a keyword search for the drawing’s document number.
Package
Suffix
8-Pin SOICN
EF
Package Outline Drawing Number
98ASB42564B
33660
10
Analog Integrated Circuit Device Data
NXP Semiconductors
33660
Analog Integrated Circuit Device Data
NXP Semiconductors
11
7
Revision History
Revision
Date
1.0
1/2011
• Initial release
2.0
9/2011
• Adjusted format to meet current compliance standards. No data was altered.
3.0
10/2011
• Updated the PC part number to MC.
2/2013
• Added PC33660BEF to the ordering information
• Redefined VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO 7637-3) for the 33660B
• Added Module Level ESD (Air Discharge, Powered) for the 33660B
4.0
Description of Changes
• Added note (7)
• Increased ESD structure voltage for 33660B, and added bleed-off circuit on VBB pin in Figure 2
5.0
10/2013
• Clarified machine model limits for MC33660 and MC33660B, page 5
6.0
1/2016
• Changed document classification to Technical Data
• Updated format and style
33660
12
Analog Integrated Circuit Device Data
NXP Semiconductors
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© NXP Semiconductors N.V. 2016. All rights reserved.
Document Number: MC33660
Rev 6.0
1/2016
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