Freescale Semiconductor Technical Data Document Number: MC33390 Rev 7.0, 11/2006 Class B Serial Transceiver The 33390 is a serial transceiver designed to provide bi-directional half-duplex communication meeting the automotive SAE Standard J1850 Class B Data Communication Network Interface specification. It is designed to interface directly to on-board vehicle microcontrollers and serves to transmit and receive data on a single-wire bus at data rates of 10.4 kbps using Variable Pulse Width Modulation (VPWM). The 33390 operates directly from a vehicle's 12 V battery system and functions in a logic fashion as an I/O interface between the microcontroller's 5.0 V CMOS logic level swings and the required 0 V to 7.0 V waveshaped signal swings of the bus. The bus output driver is short circuit current limited. Features • Designed for SAE J-1850 Class B Data Rates • Full Operational Bus Dynamics Over a Supply Voltage of 9.0 to 16 V • Ambient Operating Temperature of -40°C to 125°C • Interfaces Directly to Standard 5.0 V CMOS Microcontroller • BUS Pin Protected Against Shorts to Battery and Ground • Thermal Shutdown with Hysteresis • Voltage Waveshaping of Bus Output Driver • 40 V Max VBAT Capability • Pb-Free Packaging Designated by Suffix Code EF VPWR J-1850 SERIAL TRANSCEIVER D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-LEAD SOICN ORDERING INFORMATION Device MCZ33390EF/R2 BUS LOAD MCU SLEEP TX RX 4X/Loop GND Secondary Nodes Figure 1. 33390 Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. Temperature Range (TA) Package -40°C to 125°C 8 SOICN MC33390D/DR2 Primary Node 33390 +VBAT 33390 INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM 33390 Bus Driver VBAT SLEEP Thermal Shutdown 4.5 V Reference Waveshaping Filter TX RX 4X/LOOP BUS Voltage Regulator Digital Output Driver Loss of Ground Protection 4X Enable Loopback LOAD GND Note This device contains approximately 400 active transistors and 250 gates. Figure 2. 33390 Simplified Internal Block Diagram 33390 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS SLEEP 11 88 RX GND 22 77 TX LOAD 33 66 4X/LOOP BUS 44 55 VBAT Figure 3. 33390 Pin Connections Table 1. 33390 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9. Pin Number Pin Name Definition 1 SLEEP 2 GND Device ground pin. 3 LOAD Accommodates an external pull-down resistor to ground to provide loss of ground protection. 4 BUS Waveshaped SAE Standard J-1850 Class B transmitter output and receiver input. 5 VBAT Provides device operating input power. 6 4X/ LOOP 7 TX Serial data input (DI) from the microcontroller to be transmitted onto Bus. 8 RX Bus received serial data output (DO) sent to the microcontroller. Enables the transceiver when Logic 1 and disables the transceiver when Logic 0. Tristate input mode control; Logic 0 = normal waveshaping, Logic 1 = waveshaping disabled for 4X transmitting, high impedance = loopback mode. 33390 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit VBAT -0.3 to 40 V VI/O(CPU) -0.3 to 7.0 V VBUS -2.0 to 16 V Human Body Model VESD1 ±2000 Machine Model VESD2 ±200 Storage Temperature TSTG -65 to 150 °C TA -40 to 125 °C VBAT DC Supply Voltage Input I/O Pins (1) (2) BUS and LOAD Outputs ESD Voltage (3) Operating Ambient Temperature V TJ -40 to 150 °C Peak Package Reflow Temperature During Reflow (4), (5) TPPRT Note 5. °C Thermal Resistance (Junction-to-Ambient) RθJ-A 180 °C / W Operating Junction Temperature Notes 1. An external series diode must be used to provide reverse battery protection of the device. 2. SLEEP, TX, RX, and 4X / LOOP are normally connected to a microcontroller. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 4. 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33390 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted. Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25°C. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit POWER CONSUMPTION Operational Battery Current (RMS with Tx = 7.812 kHz Square Wave) BUS Load = 1380 Ω to GND, 3.6 nF to GND mA IBAT (OP1) – 3.0 11.5 IBAT (OP2) – 22.4 32 After SLEEP Toggle Low to High; Prior to Tx Toggling IBAT(BUS L1) – 1.1 3.0 After Tx Toggle High to Low IBAT(BUS L2) – 6.4 8.5 BUS Load = 257 Ω to GND, 20.2 nF to GND Battery Bus Low Input Current Sleep State Battery Current mA IBAT(SLEEP) VSLEEP = 0 V µA – 38.2 65 BUS BUS Input Receiver Threshold (6) Threshold High (Bus Increasing until Rx ≥ 3.0 V) Threshold Low (Bus Decreasing until Rx ≤ 3.0 V) Threshold in Sleep State (SLEEP = 0 V) Hysteresis (VBUS(IH) - VBUS(IL), SLEEP = 0 V) V VBUS(IH) 4.25 3.9 – VBUS(IL) – 3.7 3.5 BUSTH(SLEEP) 2.4 3.0 3.4 VBUS(HYST) 0.1 0.2 0.6 BUS-Out Voltage (257 Ω ≤ RBUS(L) to GND ≤ 1380 Ω) V 8.2 V ≤ VBAT ≤ 16 V, Tx = 5.0 V VBUS (OUT1) 6.25 6.9 8.0 4.25 V ≤ VBAT ≤ 8.2 V, Tx = 5.0 V VBUS (OUT2) VBAT - 1.6 – VBAT Tx = 0 V VBUS (OUT3) – 0.27 0.7 60 129 170 IBUS (LEAK1) -500 -55 – IBUS (LEAK2) – 189 500 150 170 190 10 12 15 BUS Short Circuit Output Current IBUS (SHORT) Tx = 5.0 V, -2.0 V ≤ VBUS ≤ 4.8 V mA BUS Leakage Current µA -2.0 V ≤ VBUS ≤ 0 V 0 V ≤ VBUS ≤ VBAT BUS Thermal Shutdown (7) (Tx = 5.0 V, IBUS = -0.1 mA) TBUS (LIM) Increase Temperature until VBUS ≤ 2.5 V BUS Thermal Shutdown Hysteresis (8) TBUS (LI MHYS) TBUS (LIM) - TBUS (REEN) BUS and LOAD Current with Loss of VBAT or GND (IBAT = 0 µA) (see Figure 4) -18 V ≤ VBUS ≤ 9.0 V -18 V ≤ VLOAD ≤ 9.0 V °C °C mA IBUS (LOSS) – 0.00 0.1 ILOAD (LOSS) – 0.00 0.1 Notes 6. Typical threshold value is the approximate actual occurring switch point value with VBAT = 13 V, TA = 25°C. 7. 8. Device characterized but not production tested for thermal shutdown. Device characterized but not production tested for thermal shutdown hysteresis. 33390 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted. Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25°C. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol Min Typ Max Unit BUS (CONTINUED) LOAD Output LON IL = 6.0 mA Unpowered LOAD Output V – 0.07 0.2 0.3 0.56 0.9 LDIO VBAT = 0 V, IL = 6.0 mA V TX Tx Input Voltage V Tx Input Logic Low Level VTx(IL) – – 0.8 Tx Input Logic High Level VTx(IH) 3.5 – – Tx Input Current µA VTx = 5.0 V ITx(IH) 50 106 200 VTx = 0 V ITx(IL) -2.0 0.23 2.0 V4X / LOOP = 0 V (Normal Mode) I4X / LOOP(IL) -200 -60 200 V4X / LOOP = 5.0 V (4X Mode) I4X / LOOP(IH) -200 110 200 Normal Mode to Loopback Mode V4X / LOOP(IL) 1.1 1.31 1.5 Loopback Mode to 4X Mode V4X / LOOP(IH) 3.2 3.43 3.6 0.01 0.18 0.4 4.25 4.58 4.75 LOOP 4X / LOOP Input Current µA 4X / LOOP Input Threshold (Tx = 4096 Hz Square Wave) V RX Rx Output Voltage Low VRx (LOW) VBUS = 0 V, IRx = 1.6 mA Rx Output Voltage High VRx(HIGH) VBUS = 7.0 V, IRx = -200 µA Rx Output Current V V IRx VRx = High; Short Circuit Protection Limits mA 2.0 3.67 8.0 SLEEP SLEEP Input Current µA VSLEEP = 0 V ISLEEP (IL) – -0.23 -2.0 VSLEEP = 5.0 V ISLEEP (IH) 1.0 6.21 20 33390 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions of 7.0 V ≤ VBAT ≤ 16 V, -40°C ≤ TA ≤ 125°C, SLEEP = 5.0 V unless otherwise noted. Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25°C. All positive currents are into the pin. All negative currents are out of the pin. Characteristic Symbol BUS Voltage Rise Time (9) (9.0 V ≤ VBAT ≤ 16 V, Tx = 7.812 kHz Square Wave) (see Figure 5) tRISE (BUS) Min Typ Max Unit BUS µs BUS Load = 3,300 pF and 1.38 kΩ to GND 9.0 11.15 15 BUS Load = 16,500 pF and 300 Ω to GND 9.0 11.86 15 BUS Voltage Fall Time (see Figure 5) (9) (9.0 V ≤ VBAT ≤ 16 V, Tx = 7.812 kHz Square Wave) tFALL (BUS) µs BUS Load = 3,300 pF and 1.38 kΩ to GND 9.0 10.50 15 BUS Load = 16,500 pF and 300 Ω to GND 9.0 11.17 15 Pulse Width Distortion Time (9.0 V ≤ VBAT ≤ 16 V, Tx = 7.812 kHz Square Wave) (see Figure 6) tPWD (BUS) BUS Load = 3,300 pF and 1.38 kΩ to GND µs 35 62 93 – 17.7 25 4X Mode – 2.6 4.0 Normal Mode 13 17.3 24 80 40 – Propagation Delay tPD (BUS) Tx Threshold to Rx Threshold µs TX Tx to BUS Delay Time (Tx = 2.5 V to VBUS = 3.875 V) (see Figure 7) SLEEP to Tx Setup Time (see Figure 7) tTXDELAY tSLEEPTXSU µs µs RX Rx Output Delay Time (Tx = 2.5 V to VBUS = 3.875 V) (see Figure 8) µs Low-to-Output High TRXDELAY / L–H – 0.11 2.0 High-to-Output Low TRXDELAY / H–L – 0.38 2.0 Rx Output Transition Time (CRx = 50 pF to GND, 10% and 90% Points) (see Figure 9) Low-to-Output High High-to-Output Low µs tRXTRANS / L–H – 0.34 1.0 tRXTRANS /H–L – 0.08 1.0 Rx Output Transition Time (10) (CRx = 50 pF to GND, SLEEP = 0 V, 10% and 90% Points) (see Figure 9) Low-to-Output High High-to-Output Low µs tRXTRANS / L–H – 0.32 5.0 tRXTRANS /H–L – 0.08 5.0 Notes 9. Typical is the parameter's approximate average value with VBAT = 13 V, TA = 25°C. 10. Rx Output Transition Time from a sleep state. 33390 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES TEST FIGURES 33390 SLEEP IBUS (LOSS) VBAT -18 V to 9.0 V BUS Tx GND 2.5 V tSLEEPTxSU -18 V to 9.0 V LOAD ILOAD (LOSS) tTxDelay BUS Figure 4. Loss of Ground or VBAT Test Circuit 2.5 V 3.875 V Figure 7. SLEEP to Tx Delay Times 3.5 V BUS 64 µs Tx 0.8 V 122 µs 3.875 V tRxDelay / lowto-output high tRxDelay /high-tooutput low 80% BUS Rx 20% 2.5 V t FALL t RISE Figure 8. BUS-to-Rx Delay Time Figure 5. BUS Rise and Fall Times 5.0 V Tx 64 µs tRXTRANS / L– 0V tRXTRANS / H–L 90% 90% tPWD(MIN) tPWD 1.5 V tPWD(MAX Rx 10% 10% ) Figure 6. Pulse Width Distortion Figure 9. Rx Rise and Fall Time 33390 8 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33390 is a serial transceiver device designed to meet the SAE Standard J-1850 Class B performance for bidirectional half-duplex communication. The device is packaged in an economical surface-mount SOIC plastic package. An internal block diagram of the device is shown in Figure 2. The 33390 derives its robustness to temperature and voltage extremes from being built on a SMARTMOS process, incorporating CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs. Though the 33390 was principally designed for automotive applications requiring SAE J-1850 Class B standards, it is suited for other serial communication applications. It is parametrically specified over an ambient temperature range of -40°C ≤ TA ≤ 125°C and 7.0 V ≤ VBAT ≤ 16 V supply. The economical 8-pin SOICN surface mount plastic package makes the device a cost-effective solution. FUNCTIONAL PIN DESCRIPTION Input Power (VBAT) This is the only required input power source necessary to operate the 33390. The internal voltage reference of the 33390 will remain fully operational with a minimum of 9.0 V on this pin. Bus transmissions can continue with battery voltages down to 5.0 V. The bus output voltage will follow the battery voltage down and, in doing so, track approximately 1.6 V below the battery voltage. The device will continue to receive and transmit bus data to the microcontroller with battery voltages as low as 4.25 V. The pin can withstand voltages from -0.3 V to 40 V. If reverse battery protection is required, an appropriate diode must be placed in series with this pin to protect the IC. Sleep Input (SLEEP) This input is used to enable and disable the Class B transmitter. The Class B receiver is always enabled so long as adequate VBAT pin voltage is applied. When the SLEEP pin voltage is 5.0 V, the Class B transmitter is enabled. If this input is 0 V, the Class B transmitter will be disabled and less than 65 µA of current will be drawn by the VBAT pin. The pin also provides a 5.0 V reference, internal to the device, used to establish the Rx output level and slew rate times. down resistor. No matter how many secondary nodes are on the Class B bus, the RC time constant of the Class B bus is maintained at approximately 5.0 µs. The minimum and maximum capacitance and resistance on the Class B bus is given by the expressions shown in Table 5, page 10. One Primary Node 470 pF 10.6 kΩ 1.5 kΩ 3300 pF Figure 10. Minimum Bus Load Primary Node 10.6 kΩ 470 pF 3300 pF 1.5 kΩ 24 Secondary Nodes Class B Functional Description The transmitter provides an analog waveshaped 0 V to 7.0 V waveform on the BUS output. It also receives waveforms and transmits a digital level signal back to a logic IC. The transmitter can drive up to 32 secondary Class B transceivers (see Figures 10 and 11). These secondary nodes may be at ground potentials that are ± 2.0 V relative to the control assembly. Waveshaping will only be maintained during 2 of the 4 corners when the 0 to ± 2.0 V ground potential difference condition exists. The 33390 is a secondary node on the Class B bus. Each secondary transceiver has a 470 ± 10% pF capacitor on its output for EMI suppression purposes, as well as a 10.6 kΩ ± 5% pulldown resistor to ground. The primary node has a 3300 ± 10% pF capacitor on its output for EMI suppression, as well as a 1.5 kΩ ± 5% pull-down resistor to ground. With more than 26 nodes, there is no primary node (see Figure 12). All nodes will have a 470 ± 10% pF capacitor and a 10.6 kΩ ± 5% pull- 442 Ω 11280 pF Figure 11. Maximum Number of Nodes 31 Secondary Nodes 10.6 kΩ 470 pF 342 Ω 14570 pF Figure 12. Maximum Bus Load 33390 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Table 5. Class B Bus Capacitance and Resistance Expressions Level Capacitance Resistance to Ground Minimum (3.3 x 0.9) + (0.47 x 0.9) = 3.39 nF (1.5 x 0.95) || (10.6 x 0.95) / 25 = 314 Ω Maximum (3.3 x 1.1) + 25 (0.47 x 1.1) = 16.55 nF (1.5 x 1.05) || (10.6 x 1.05) = 1.38 kΩ 33390 10 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS TYPICAL APPLICATIONS Class B Module Inputs Transmitter Data from the MCU (Tx) The Tx input is a push-pull (N-channel / P-channel FETs) buffer with hysteresis for noise immunity purposes. This pin is a 5.0 V CMOS logic level input from the MCU following a true logic protocol. A logic [0] input drives the BUS output to 0 V (via the external pull-down resistor to ground on each node), while a logic [1] input produces a high voltage at the BUS output. A logic [0] input level is guaranteed when the Tx input pin is open-circuited by virtue of an internal 40 kΩ pulldown resistor. No external resistor is required for its operation. Waveshaping and 4X / Loop This input is a tristateable input: 0 V = normal waveshaping, 5.0 V = waveshaping is disabled for 4X transmitting, and high impedance = loopback mode of operation. This is a logic level input used to select whether waveshaping for the Class B output is enabled or disabled. A logic [0] enables waveshaping, while a logic [1] disables waveshaping. In the 4X mode, the BUS output rise time is less than 2.0 µs and the fall time is less than 5.0 µs (owing to the external RC pull-down to ground). In the loopback condition, the Tx signal is fed back to the Rx output after waveshaping without being transmitted onto the BUS. This mode of operation is useful for system diagnostic purposes. Class B Module Outputs Transceiver Output (BUS) This is the output driver stage that sources current to the bus. Its output follows the waveshaped waveform input. Its output voltage is limited to 6.25 V to 8.0 V under normal battery level conditions. The limited level is controlled by an internal regulator/clamp circuit. Once the battery voltage drops below 9.0 V, the regulator / clamp circuit saturates, causing the bus voltage to track the battery voltage. A 1.5 kΩ ± 5% external resistor (as well as any 10.6 kΩ pull-down resistors of any secondary nodes) sinks the current to discharge the capacitors during high-to-low transitions. This sourcing output is short circuit-protected (60 mA to 170 mA) against a short to -2.0 V and sinks less than 1.0 mA when shorted to VBAT. If a short occurs, the overtemperature shutdown circuit protects the source driver of the device. In the event battery power is lost to the assembly, the bus transmitter's output stage will be disabled and the leakage current from the BUS output will not source or sink more than 100 µA of current. The transceiver will operate with a remote ground offset of ± 2.0 V, but the lower corners of transmission will not be rounded during this condition. Receiver Output to the Microcontroller (Rx) This is a 5.0 V CMOS compatible push-pull output used to send received data to the microcontroller. It does not require an external pull-up resistor to be used. The receiver is always enabled and draws less than 65 µA of current from VBAT. The receive threshold is dependent on the state of the SLEEP pin. The receiver circuitry is able to operate with VBAT voltages as low as 4.25 V and still remains capable of “waking up” the 33390 when remote Class B activity is detected. When the SLEEP pin is 0 V and message activity occurs on the bus, the receiver passes the bus message through to the microcontroller. The 33390 does not automatically “wake up” from a sleep state when bus activity occurs: the microcontroller must tell it to do so. In the Static Electrical Characteristics table, the maximum voltage for Rx is specified as 4.75 V over an operating range of -40°C to 125°C temperature and 7.0 V to 16 V VBAT. This maximum Rx voltage is compatible with the minimum VDD voltage of microcontrollers to prevent the 33390 from sourcing current to the microcontroller's output. Switched Ground Output (LOAD) Normally this output is a saturated switch to ground, which pulls down the external resistor between the BUS and LOAD outputs. In the event ground is lost to the assembly, the LOAD output will bias itself “off” and will not leak more than 100 µA of current out of this pin. Overtemperature Shutdown If the BUS output becomes shorted to ground for any duration, an overtemperature shutdown circuit “latches off” the output source transistor whenever the die temperature exceeds 150°C to 190°C. The output transistor remains latched off until the Tx input is toggled from a logic [0] to a logic [1]. The rising edge provides the clearing function, provided the locally sensed temperature is 10°C to 15°C below the latch-off temperature trip temperature. Waveshaping Waveshaping is incorporated into the 33390 to minimize radiated EMI emissions. Receiver Protocol The Class B communication scheme uses a variable pulse width (VPW) protocol. The microcontroller provides the VPW decoding function. Once the receiver detects a transition on Rx, it starts an internal counter. The initial “start of frame” bit is a logic [1] and lasts 200 µs. For subsequent bits, if there is a bus transition before 96 µs, one logic state is inferred. If there is a bus transition after 96 µs, the other logic state is inferred. The “end of data” bit is a logic [0] and lasts 200 µs. If there is no activity on the bus for 280 µs to 320 µs following a broadcast message, multiple unit nodes may arbitrate for control of the next message. During an arbitration, after the 33390 Analog Integrated Circuit Device Data Freescale Semiconductor 11 TYPICAL APPLICATIONS “start of frame” bit has been transmitted, the secondary node transmitting the most consecutive logic [0] bits will be granted sole transmission access to the bus for that message. Loss of Assembly Ground Connection The definition of a loss of assembly ground condition at the device level is that all pins of the 33390, with the exception of BUS and LOAD, see a very low impedance to VBAT. The LOAD pin of the device has an internal transistor switch connected to it that is normally saturated to ground. This pulls the LOAD-side of the external resistor (tied from BUS to LOAD) to ground under normal conditions. The LOAD pin switch is essentially that of an “upside down” FET, which is normally biased “on” so long as module ground is present and biased “off” when loss-of-ground occurs. When a loss of assembly ground occurs, the load transistor switch is selfbiased “off”, allowing no more than 100 µA of leakage current to flow in the LOAD pin. During such a loss of assembly ground condition, the BUS and LOAD pins exhibit a high impedance to VBAT; all other pins will exhibit a low impedance to VBAT. During this condition the BUS pin is prevented from sourcing any current or loading the bus, which would cause a corruption of any data being transmitted on the bus. While a particular assembly is experiencing a loss of ground, all other assembly nodes are permitted to function normally. It should be noted that with other nodes existing on the bus, the bus will always have some minimum / maximum impedance to ground as shown in Table 5, page 10. Loss of Assembly Battery Connection The definition of a loss of assembly battery condition at the device level is that the VBAT pin of the 33390 sees an infinite impedance to VBAT, but there is some undefined impedance between these pins and ground. 33390 12 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS PACKAGE DIMENSIONS PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below. EF SUFFIX (PB-FREE) 8-LEAD SOIC NARROW BODY PLASTIC PACKAGE 98ASB42564B ISSUE U 33390 Analog Integrated Circuit Device Data Freescale Semiconductor 13 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 5.0 4/2006 • • • Converted to Freescale format Implemented revision history page. Added Part Numbers MC33390EF/EFR2 to Ordering Information on Page 1. 6.0 10/2006 • • Updates document form and style Removed MC33390EF and replaced with MCZ33390EF in the number Ordering Information 7.0 11/2006 • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com. 33390 14 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. 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