A8447 Datasheet

A8447
High Voltage Step Down Regulator
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: December 1, 2015
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, refer to the A8498.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8447
High Voltage Step Down Regulator
Features and Benefits
Description
▪
▪
▪
▪
▪
▪
▪
The A8447 is a 3 A, high efficiency general-purpose buck
regulator designed for a wide variety of applications. The output
voltage is adjustable from 0.8 to 24 V, based on a resistor divider
and the 0.8 V ±2% reference. External components include an
external clamping diode, inductor, and filter capacitor. The offtime is determined by an external resistor to ground. It operates
in both continuous and discontinuous modes to maintain light
load regulation. An internal blanking circuit is used to filter
out transients due to the reverse recovery of the external clamp
diode. Typical blanking time is 200 ns.
Wide input voltage range: 8 to 50 V
Integrated low RDS(on) DMOS switch
3 A continuous output current
Adjustable fixed off-time
Highly efficient
Adjustable output: 0.8 to 24 V
Small package with exposed thermal pad
Package: 8 pin SOIC with exposed thermal
pad (suffix LJ)
This new device is ideal for various end products including
applications with 8 to 50 V input voltage range and require up
to 3 A output current, such as uninterruptible power supplies,
point of sale (POS) applications, and industrial applications
with 24 or 36 V bus.
Applications include:
▪ Printer power supplies
▪ Office automation equipment
▪ POS thermal, laser, photo, and inkjet printers
▪ Tape drives
▪ Industrial applications
Approximate Scale 1:1
Typical Application
+42 V
Efficiency vs. Output Current
CBOOT
0.01 µF
CIN2
BOOT
VIN
ENB
LX
D1
TSET
A8447
L1
VOUT
3.3 V
3A
VBIAS
RTSET
54 kΩ
R1
2.87 kΩ
GND
ESR
FB
R2
910 Ω
CBYP
0.22 µF
COUT
220 µF
25 V
Efficiency %
CIN1
0.22 µF
90.0
88.0
86.0
84.0
82.0
80.0
78.0
76.0
74.0
72.0
70.0
VOUT (V)
5
3.3
0
500
1000
1500
IOUT (mA)
Data is for reference only. Efficiency data from circuit shown in left panel.
A8447-DS, Rev. 4
2000
2500
3000
A8447
High Voltage Step Down Regulator
Absolute Maximum Ratings
Min.
Typ.
Max.
Units
VIN Supply Voltage
Characteristic
Symbol
VIN
–
–
50
V
VBIAS Input Voltage
VBIAS
–0.3
–
7
V
VS
–1
–
–
V
VENB
–0.3
–
7
V
TA –20
–
85
°C
SW Switching Voltage ENB Input Voltage Range
Operating Ambient Temperature Range
Conditions
Junction Temperature
TJ(max)
–
–
150
°C
Storage Temperature
Tstg
–55
–
150
°C
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed
the specified current ratings, or a junction temperature, TJ, of 150°C.
Package Thermal Characteristics*
Package
RθJA
(°C/W)
PCB
LJ
35
4-layer
* Additional information is available on the Allegro website.
Ordering Information
Use the following complete part numbers when ordering:
Part Number
Packing
Description
A8447SLJTR-T
13-in. reel, 3000 pieces/reel
LJ package, SOIC surface mount with
exposed thermal pad; leadframe plating
100% matte tin.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A8447
High Voltage Step Down Regulator
Functional Block Diagram
BOOT
VIN
Boot Charge
+
VIN
–
VOUT
LX
L1
D1
ESR
COUT
Switch PWM Control
Switch
Disable
CBYP
Clamp
+
TSET
I_Peak
–
I_Demand
Error
FB
–
+
µC
ENB
COMP
GND
VBB UVLO
TSD
Bias Supply
VBIAS
VBIAS is connected to VOUT
when VOUT target is between
3.3 and 5 V
Soft Start
Ramp Generation
0.8 V
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A8447
High Voltage Step Down Regulator
ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 50 V (unless noted otherwise)
Characteristics
VIN Quiescent Current3
VBIAS Input Current
Buck Switch On Resistance
Fixed Off-Time Proportion
Feedback Voltage
Output Voltage Regulation
Symbol
IVIN(Q)
IBIAS
RDS(on)
toff
Test Conditions
Min.
Typ.
Max.
Units
VENB = LOW, IOUT = 0 mA, VIN = 42 V,
VBIAS = VOUT
–
0.90
1.35
mA
VENB = LOW, IOUT = 0 mA, VIN = 42 V,
VBIAS < 3 V
–
4.4
6.35
mA
VENB = HIGH
–
–
100
µA
VBIAS = VOUT
–
3.5
5
mA
TA = 25°C, IOUT = 3 A
–
450
–
mΩ
TA = 125°C, IOUT = 3 A
–
650
–
mΩ
–15
–
15
%
0.784
0.8
0.816
V
Based on calculated value
VFB
VOUT
–3
–
3
%
Feedback Input Bias Current
IFB
IOUT = 0 mA to 3 A
–400
–100
100
nA
Soft Start Time
tss
5
10
15
ms
Buck Switch Current Limit
ICL
VFB > 0.4 V
3.5
–
5
A
VFB < 0.4 V
0.5
–
1.5
A
ENB Open Circuit Voltage
VOC
Output disabled
2.0
–
7
V
–
–
1.0
V
ENB Input Voltage Threshold
VENB(0)
LOW level input (Logic 0), output enabled
ENB Input Current
IENB(0)
VENB = 0 V
–10
–
–1
µA
VIN Undervoltage Threshold
VUVLO
VIN rising
6.6
6.9
7.2
V
VIN Undervoltage Hysteresis
VUVLO(hys)
VIN falling
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
TJTSD
TJTSD(hys)
0.7
–
1.1
V
Temperature increasing
–
165
–
°C
Recovery = TJTSD – TJTSD(hys)
–
15
–
°C
1Negative
current is defined as coming out of (sourcing) the specified device pin.
over the junction temperature range of 0ºC to 125ºC are assured by design and characterization.
3VBIAS is connected to VOUT when the V
OUT target is between 3.3 and 5 V.
2Specifications
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A8447
High Voltage Step Down Regulator
Functional Description
The value of a resistor between the TSET and GND determines
the fixed off-time (see graph in the tOFF section).
VOUT. The output voltage is adjustable from 0.8 to 24 V, set by an
external resistor divider. The voltage can be calculated with the
following formula:
VOUT = VFB × (1 + R1/R2)
(1)
Light Load Regulation. To maintain voltage regulation during
light load conditions, the switching regulator enters a cycle-skipping mode. As the output current decreases, there remains some
energy that is stored during the power switch minimum on-time.
In order to prevent the output voltage from rising, the regulator
skips cycles once it reaches the minimum on-time, effectively
making the off-time larger.
Soft Start. An internal ramp generator and counter allow the output to slowly ramp up. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any dc load at startup.
Internally, the ramp is set to 10 ms nominal rise time. During soft
start, current limit is 3.5 A minimum.
The following conditions are required to trigger a soft start:
• VIN > 6 V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
VBIAS. To improve overall system efficiency, the regulator output,
VOUT, is connected to the VBIAS input to supply the operating
bias current during normal operating conditions. During startup
the circuitry is run off of the VIN supply. VBIAS should be connected to VOUT when the VOUT target level is between 3.3 and
5 V. If the output voltage is less than 3.3 V, then the A8447 can
operate with an internal supply and pay a penalty in efficiency,
as the bias current will come from the high voltage supply, VIN.
VBIAS can also be supplied with an external voltage source. No
power-up sequencing is required for normal operation.
ON/OFF Control. The ENB pin is externally pulled to ground
to enable the device and begin the soft start sequence. When the
ENB is open circuited, the switcher is disabled and the output
decays to 0 V.
Protection. The buck switch will be disabled under one or more
of the following fault conditions:
• VIN < 6 V
• ENB pin = open circuit
• TSD fault
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
tOFF. The value of a resistor between the TSET pin and ground
determines the fixed off-time. The formula to calculate tOFF (µs)
is:
 1– 0.03 × VBIAS
(2)
 ,
tOFF = RTSET 
10.2 × 109


where RTSET (kΩ) is the value of the resistor. Results are shown
Off-Time Setting versus Resistor Value
200
180
160
RTSET (kΩ)
The A8447 is a fixed off-time, current mode controlled, buck
regulator. The regulator requires an external clamping diode,
inductor, and filter capacitor. It operates in both continuous and
discontinuous modes. An internal blanking circuit is used to filter
out transients resulting from the reverse recovery of the external
clamp diode. Typical blanking time is 200 ns.
140
VBIAS = 5 V
120
VBIAS = 3.3 V
100
80
60
40
20
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
16
tOFF (µs)
in the following graph:
The RTSET resistor should be not smaller than 7.65 kΩ ±2% to
prevent very short off-times from violating the minimum on-time
of the switcher.
Shorted Load. If the voltage on the FB pin falls below 0.4 V, the
regulator will invoke a 1.5 A typical overcurrent limit to handle
the shorted load condition at the regulator output. For low output
voltages at power up and in the case of a shorted output, the offtime is extended to prevent loss of control of the current limit due
to the minimum on-time of the switcher.
The extension of the off-time is based on the value of the TSET
multiplier and the FB voltage, as shown in the following table:
VFB (V)
TSET Multiplier
< 0.16
8 × tOFF
< 0.32
4 × tOFF
< 0.5
2 × tOFF
> 0.5
tOFF
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A8447
High Voltage Step Down Regulator
Component Selection
L1. The inductor must be rated to handle the total load current.
The value should be chosen to keep the ripple current to a reasonable value. The ripple current, IRIPPLE, can be calculated by:
IRIPPLE = VL(OFF) × tOFF / L (3)
VL(OFF) = VOUT + Vf + IL(AV) × RL (4)
Substituting into equation 7:
fSW = 1 / (7 µs +1.12 µs) = 123 kHz
Higher inductor values can be chosen to lower the ripple current. This may be an option if it is required to increase the total
maximum current available above that drawn from the switching
regulator. The maximum total current available, ILOAD(MAX) , is:
Example:
ILOAD(MAX) = ICL(min) – IRIPPLE / 2 (8)
Given VOUT = 5 V, Vf = 0.55 V, VIN = 42 V, ILOAD = 0.5 A, power
inductor with L = 180 µH and RL = 0.5 Ω Rdc at 55°C, tOFF =
7 µs, and RDS(on) = 1 Ω.
where ICL(min) is 3.5 A, from the Electrical Characteristics table.
Substituting into equation 4:
D1. The Schottky catch diode should be rated to handle 1.2 times
the maximum load current. The voltage rating should be higher
VL(OFF) = 5 V + 0.55 V+ 0.5 A × 0.5 Ω = 5.8 V
than the maximum input voltage expected during all operating
Substituting into equation 3:
conditions. The duty cycle for high input voltages can be very
close to 100%.
IRIPPLE = 5.8 V × 7 µs / 180 µH = 225 mA
The switching frequency, fSW, can then be estimated by:
COUT. The main consideration in selecting an output capacitor fSW = 1 / ( tON + tOFF ) (5)
tON = IRIPPLE × L / VL(ON) (6)
VL(ON) = VIN – IL(AV) × RDS(on) – IL(AV) × RL– VOUT (7)
Substituting into equation 7:
VL(ON) = 42 V – 0.5 A × 1 Ω – 0.5 A × 0.5 Ω – 5 V = 36 V
Substituting into equation 6:
tON = 225 mA × 180 µH / 36 V = 1.12 µs
is voltage ripple on the output. For electrolytic output capacitors,
a low-ESR type is recommended.
The peak-to-peak output voltage ripple is simply IRIPPLE ×
ESR. Note that increasing the inductor value can decrease the
ripple current. The minimum voltage rating of the capacitor is
10 V. However, because ESR decreases with voltage, the most
cost-effective choice may be rated higher in voltage. It is recommended that the ESR be less than 100 mΩ.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A8447
High Voltage Step Down Regulator
RTSET Selection. Correct selection of RTSET values will
ensure that minimum on time of the switcher is not violated
and prevent the switcher from cycle skipping. For a given VIN
to VOUT ratio, RTSET must be greater than or equal to the value
defined by the curve in the RTEST Value Selection graph below.
Note. The curve represents the minimum RTSET value. When
calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor
tolerance should also be considered, so that under all operating
conditions the resistance on the TSET pin remains as close to the
curve as possible.
The RTEST Selection table shows recommended RTSET values
based on common operating conditions. For other operating conditions, refer to the RTSET Value Selection graph.
FB Resistor Selection. The impedance of the FB network
should be kept low to improve noise immunity. Large value resistors can pick up noise generated by the inductor, which can affect
voltage regulation of the switcher.
RTSET Value Selection*
Selection Graph
Recommended Common Values
VIN
(V)
42
42
42
42
24
24
24
24
12
12
12
12
70
65
60
55
VIN / VOUT
50
45
40
35
30
25
20
15
10
5
0
0
15
30
45
60
75
90
105
120
135
150
165
180
195
210
RTSET (kΩ)
VOUT
(V)
5
3.3
1.8
1.5
5
3.3
1.8
1.5
5
3.3
1.8
1.5
VIN / VOUT
8.4
12.7
23.3
28
4.8
7.3
13.3
16
2.4
3.6
6.6
8
RTSET Value
(kΩ)
37.4
54.9
90.9
105
20.0
32.4
54.9
66.5
7.68
13.7
30.1
37.4
*The RTSET resistor should be not smaller than 7.65 kΩ ±2% to prevent very short off-times from violating the minimum on-time of
the switcher.
Recommended Components
Component
Description
Part Number
L1
Sumida 68 µH
RCH1216BNP-680K
D1
NIEC Schottky Barrier Diode 60 V TO-252AA
NSQ03A06
CBYP
Ceramic X7A 0.22 µF 100 V
Generic
CBOOT
Ceramic X7A 0.01 µF 100 V
Generic
Electrolytic 100 µF 50 V; must be able to handle worst case ripple curent
Generic
Ceramic X7A 0.22 µF 50 V
Generic
United Chemi-Con PXA 220 µF 16 V Low ESR
PXA16VC221MJ12TP
Rubycon ZL 220 µF 25 V Low ESR
25ZL220M8x11.5
CIN
COUT
(Option 1)
Panasonic FM 220 µF 25 V Low ESR (Option 2)
EEUFM1E221
VOUT
1.5 V
1.8 V
3.3 V
5V
R1
1.3 kΩ
2.55 kΩ
2.87 kΩ
6.3 kΩ
R2
1.47 kΩ
2 kΩ
0.910 kΩ
1.2 kΩ
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A8447
High Voltage Step Down Regulator
Recommended PCB Layout
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance ground located
very close to the device. This grounding scheme is known as star
grounding. It is likely that a ground plane will be necessary to
meet thermal requirements. The recommended land pattern illustrates how to create a low impedance ground that will also assist
with removing thermal energy from the device.
The input capacitor must be placed as close as possible to the
VIN terminal because during the on cycle it is responsible for
supplying the current to the switcher. During the off cycle, the
current path is from the negative terminal of the COUT cap,
through the diode and inductor, and then to the load. As a result,
COUT and the rectifier diode must share the connection at the
negative terminal of the CIN capacitor in order to reduce ground
bounce when the diode is conducting.
The inductor should be connected as close as possible to the
switching node to minimize noise. Some applications may require
a shielded inductor due to EMI restrictions. This will depend on
the application and parameters defined by the system that will
host the regulator.
The high voltage-switching node could affect RTSET. If longer
off-times are used, the resistance on the RTSET pin can be quite
large. When designing the layout, try to keep RTSET away from
the inductor and switching node. It is also beneficial to keep the
trace as short as possible to reduce the effect of noise injection.
Because of this layout guideline, the TSET pin is located on the
other side of the device, away from the switching node.
The FB resistor network should have a lower impedance to avoid
interference from the switching node. Because the impedance
on the FB node can be controlled, it is not as critical to keep the
network isolated. It is important to keep the ground trace short so
that ground bounce cannot effect the output voltage regulation.
Star Ground
CIN1
VIN
VIN
GND
U1
CBOOT
CIN2
CBOOT
CIN2
1
GND
BOOT
ENB
D1
RTSET
GND
RTSET
R2
A8447
PAD
VBIAS
GND
FB
CBYP
R2
L1
R1
COUT
L1
CBYP
D1
LX
TSET
R1
GND
VIN
CIN1
COUT
VOUT
VOUT
Exposed copper thermal
ground area on the
unpopulated side of the PCB
The large star ground area on the populated side of the PCB, shown in the diagram as the GND nodes, supports high current throughput, and allows
the VOUT node to be located as close as practical to the A8447 (U1). Thermal conduction from the A8447 is enhanced by direct contact of its
exposed thermal pad to the smaller ground area under the A8447. This area is connected by thermal vias to the large copper ground plane on the
unpopulated side of the PCB.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A8447
High Voltage Step Down Regulator
Package LJ 8 Pin SOIC
4.90 ±0.10
0.65
8°
0°
8
B
3.90 ±0.10
A
1
6.00 ±0.20
2.41
1.04 REF
2
0.25 BSC
SEATING PLANE
GAUGE PLANE
Branded Face
SEATING
PLANE
0.10 C
C
0.15
0.00
1.27 BSC
3.30
C
PCB Layout Reference View
For Reference Only; not for tooling use (reference MS-012BA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.70 MAX
0.51
0.31
5.60
2
1
1.27
0.40
3.30 NOM
8X
1.27
1.75
0.25
0.17
2.41 NOM
8
A Terminal #1 mark area
B
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Terminal List Table
Pin Out Diagram
BOOT
1
8
VIN
ENB
2
7
LX
TSET
3
6
VBIAS
GND
4
5
FB
Pad
Number
1
2
3
4
5
6
7
8
Name
BOOT
ENB
TSET
GND
FB
VBIAS
LX
VIN
Description
Gate drive boost node
On/off control; logic input
Off-time setting
Ground
Feedback for adjustable regulator
Bias supply input
Buck switching node
Supply input
Copyright ©2006-2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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