TM Operation of the HC5503C, HC5503T Family of SLICs Evaluation Board (HC5503XEVAL1) Application Note November 1998 Features AN9813.1 designated GND. It is recommended that the analog, digital and battery grounds of the SLIC be tied together as close to the device pins as possible. The three external power supplies should each be grounded to the evaluation board. • One Evaluation Board for Performance Testing of the HC5503C, HC5503J and HC5503T Family of SLICs • Includes On-Board Op Amp and Cross Point Switch for Evaluation of “Junctor” Applications Getting Started • Monitoring of Switch Hook Detect (SHD) via On Board LED Verify that the sample is oriented in its socket correctly. Correct orientation is with pin 1 pointing towards the onboard pin 1 designator located in the upper left hand corner of the sockets. (Reference the data sheet for location of device pin 1.) • Automatic On/Off Controller for Cross Point Switch Connection Functional Description Evaluation Board Verifying Basic SLIC Operation To facilitate testing of all 3 parts on one evaluation board, the board is equipped with one Double Pole Double Throw (DPDT) toggle switch S1 . The DPDT switch determines the connection of the SLIC’s Transmit (TX) and Receive (RX) outputs. The outputs are either connected to banana jacks TX or RX for full evaluation of the voice and DC feeding characteristics (reference Figure 4) or the Onboard Op Amp and Cross Point Switch for evaluation of the end-to-end application (reference Figure 6). The operation of the sample parts can be verified by performing 4 tests: 1. 2. 3. 4. Power Supply Current Verification. Normal Loop Feed Verification. Tip and Ring Voltage Verification. Gain Verification (4-wire to 2-wire). The above 4 tests require the following equipment: a 600Ω load, a sine wave generator, an AC volt meter and two external supplies (VBAT, VCC). The HC5503C/J/T evaluation board is configured to match a 600Ω line impedance via the tip and ring feed resistors RB1 , RB2 , RB3 and RB4 . Provided with the evaluation board are two generic HC5503X samples. Application Tip: When terminating tip and ring, it is handy to assemble terminators using a Pomona MDP dual banana plug connector as the terminating resistor receptacle. Refer to Figure 1 for details. HC5503C GND The HC5503C is a low cost Subscriber Line Interface Circuit (SLIC), that replaces the components of an unbalanced discrete Analog circuit design. A B HC5503J 600Ω The HC5503J is a low cost Subscriber Line Interface Circuit (SLIC), that replaces discrete or thick film hybrid “Junctor” unbalanced design solutions [1]. FIGURE 1. TERMINATION ADAPTER Using the termination shown in Figure 1 provides an unobtrusive technique for terminating tip and ring while still providing access to both signals using the banana jack feature of the MDP connector. Posts are also available that fit into holes A and B, providing a solderable connection for the terminating resistor. HC5503T The HC5503T is a low cost Subscriber Line Interface Circuit (SLIC), that replaces the components of a discrete Transformer Analog circuit design. Power Requirements for the HC5503C/J/T Power Supply Connections Test #1 Power Supply Current Verification The HC5503C/J/T Evaluation Board requires three external power supplies. The SLIC is powered by two supplies VBAT = -48V (Typ) and VCC = +5V. The third supply (VEE = -5V) powers the external Op Amps and Cross Point Switch for the Junctor application. A quick check of evaluation board and the sample is to measure the supply currents. The readings should be similar to the values listed in Table 1. The measurements can be made using a series ammeter on each supply, or power supplies with current displays. Ground Connections Discussion The HC5503C/J/T evaluation board has tied the analog, digital and battery grounds to a common ground plane The currents measured include those of the SLIC and supporting circuitry (i.e., 2nd HC5503X SLIC, Op Amp, 4-1 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Application Note 9813 Channel A’s LED, the Cross Point Switch and Transistors Q1 and Q2). For SLIC supply currents consult the applicable data sheet. Setup 1. Connect the power supplies to the Evaluation board. 2. Set VBAT to -48V, VCC to +5V and Ground the VEE pin (VEE supply not required for this test). 3. Set the DPDT switch (S1) to standard operation. This connects the Transmit and Receive outputs to banana jacks TX and RX. 4. Terminate tip and ring Channel A with a 600Ω load (Channel B is disconnected during standard operation). 5. Measure the supply currents and compare to those in Table 1. TABLE 1. HC5503C, HC5503J, HC5503T RL (Ω) TYP (mA) VCC = +5V 600 10.9 VBAT = -48V 600 33.5 SUPPLY Test #2 Normal Loop Feed Verification This test verifies loop current operation and loop current detection via the onboard LED. Discussion When power is applied to the SLIC a loop current will flow from tip to ring through the 600Ω load. Loop current detection occurs when this loop current triggers an internal detector that pulls the output of SHD low, illuminating the LED through the +5V supply. Setup 1. Connect the power supplies to the Evaluation board. 2. Set VBAT to -48V, VCC to +5V and Ground the VEE pin (VEE supply not required for this test). 3. Set the DPDT switch (S1) to standard operation. This connects the Transmit and Receive outputs to banana jacks TX and RX. 4. Terminate tip and ring Channel A with a 600Ω load (Channel B is disconnected during standard operation). Verification: 1. The SHD LED is on when tip and ring are terminated with 600Ω. 2. The SHD LED is off when tip and ring are an open circuit. Test #3 Tip and Ring Voltage Verification This test verifies the tip and ring voltages. Setup 1. Connect the power supplies to the Evaluation board. 2. Set VBAT to -48V, VCC to +5V and Ground the VEE pin (VEE supply not required for this test). 3. Set the DPDT switch (S1) to standard operation. This connects the Transmit and Receive outputs to banana jacks TX and RX. 4-2 4. Terminate tip and ring Channel A with a 600Ω load (Channel B is disconnected during standard operation). 5. Measure tip and ring voltages with respect to ground and compare to those in Table 2. TABLE 2. BATTERY VBAT = -48V TIP TYP (V) RING TYP (V) -12.8 -30.6 Test #4 Gain Verification (4-Wire to 2-Wire) This test will verify the SLIC is operating properly and that the 4-wire to 2-wire gain is 1.0 or 0.0dB. Discussion When terminated with 600Ω load, the SLIC will exhibit unity gain from the RX input pin to across tip and ring (VTR). When an open circuit exists, a mismatch occurs and the tip to ring voltage doubles. The dB gain is calculated in Equation 1. V TR dB = 20 log ----------V RX (EQ. 1) Setup 1. Connect the power supplies to the Evaluation board. 2. Set VBAT to -48V, VCC to +5V and Ground the VEE pin (VEE supply not required for this test). 3. Set the DPDT switch (S1) to standard operation. This connects the Transmit and Receive outputs to banana jacks TX and RX. 4. Terminate tip and ring Channel A with a 600Ω load (Channel B is disconnected during standard operation). 5. Connect a sine wave generator, referenced to ground, to the RX input. 6. Set the generator for 1VRMS at 1kHz. 7. Connect an AC voltmeter across tip and ring. Verification 1. Tip to ring AC voltage of 1VRMS when terminated. 2. Tip to ring AC voltage of 2VRMS when not terminated. Verifying Junctor Operation The operation of the Junctor application circuit using the 2 HC5503X samples provided can be verified by performing 4 tests: 1. 2. 3. 4. Channel to Channel Transhybrid Balance. Inter-Channel Transhybrid Balance. Channel to Channel Gain. Intra-Channel Transhybrid Balance with different loads. The above 4 tests require the following equipment: Two 600Ω loads, a sine wave generator, an AC volt meter and three external supplies (VBAT, VCC , VEE). Definition of Junctor Circuit The function of the Junctor application circuit is to convert a two port network with a Transmit Output (TX) and a Receive Input (RX) into a one-port network. The conversion to a one-port network now makes it easy to connect phone lines in a small PBX or Key System through a single Cross Point. This Application Note 9813 conversion is accomplished by the connection of a Differential Amplifier and a Summing Amplifier. The Differential Amplifier and Summing Amplifier are used to cancel the return signal and prevent echo (reference Figure 6). In this one-port network, echo can occur in two ways: Channel to Channel and IntraChannel. Reference Figure 5 for signal path for both channelto-channel and intra-channel signals. Test #5 Channel to Channel Transhybrid Definition The removal of the receive signal from the transmit signal, to prevent an echo on the transmit side is defined as Channel to Channel Transhybrid Balance. In other words, Channel to Channel Transhybrid signals occur when the receive signal (from Channel B) is retransmitted along with the transmit signal of Channel A back to Channel B. Channel to Channel Transhybrid Balance is performed by the Summing Amplifier (the output of this amplifier is SUM A and SUM B in Figure 6). Setup 1. Connect the power supplies to the Evaluation board. 2. Set VBAT to -48V, VCC to +5V and VEE to -5V. 3. Set the DPDT switch (S1) to Junctor operation. This connects the Onboard Op Amp, Cross Point Switch and the second HC5503X SLIC to the Transmit and Receive outputs of Channel A. 4. Terminate tip and ring of both Channel A and Channel B with a 600Ω load. 5. Connect a sine wave generator in parallel with the 600Ω load across tip and ring of Channel A. The output of this generator needs to be floating. 6. Set the generator for 1VRMS at 1kHz. 7. Connect an AC volt meter between test point DIFF B and ground. This will measure the AC voltage at the output to the Differential Amplifier (DIFF B). 8. Connect an AC volt meter between test point SUM B and ground. This will measure the AC voltage at the output of the Summing Amplifier (SUM B). 9. The Channel to Channel Transhybrid Balance is calculated using the following formula in Equation 2. SUMB dB = 20 log ------------------DIFFB (EQ. 2) 10. To measure Channel to Channel Transhybrid Balance on Channel A, connect the sine wave generator in parallel with the 600Ω load across tip and ring of Channel B and repeating steps 7 through 9 in a similar fashion. Voltage measurements taken at DIFF A and SUM A. Results for both Channels should be the same. 11. Compare results to that listed in Table 3. Test #6 Intra-Channel Transhybrid Definition Intra-Channel Transhybrid Balance is defined as the removal of the transmit signal from the receive signal, and thereby 4-3 cancellation of echo, within a channel. In other words, IntraChannel Transhybrid Balance is when the transmit signal from Channel A is feed back into the input of Channel A. Intra-Channel Transhybrid Balance is performed by the Differential Amplifier (the output of this amplifier is DIFF A and DIFF B in Figure 6). Calculation of resistor value (R4) for optimum Intra-Channel Transhybrid Balance is discussed in Test #8. Setup 1. Connect the power supplies to the Evaluation board. 2. Set VBAT to -48V, VCC to +5V and VEE to -5V. 3. Set the DPDT switch (S1) to Junctor operation. This connects the Onboard Op Amp, Cross Point Switch and the second HC5503X SLIC to the Transmit and Receive outputs of Channel A. 4. Terminate tip and ring of both Channel A and Channel B with a 600Ω load. 5. Connect a sine wave generator in parallel with the 600Ω load across tip and ring of Channel A. The output of this generator needs to be floating. 6. Set the generator for 1VRMS and 1kHz. 7. Connect an AC volt meter between test point SUM A and ground. This will measure the AC voltage at the input to the Differential Amplifier (SUM A). 8. Connect an AC volt meter between test point DIFF A and ground. This will measure the AC voltage at the output of the Differential Amplifier (DIFF A). 9. The Inter-Channel Transhybrid Balance is calculated using the following formula in Equation 3. DIFFA dB = 20 log ------------------SUMA (EQ. 3) 10. To measure Inter-Channel Transhybrid Balance on Channel B, connect the sine wave generator in parallel with the 600Ω load across tip and ring of Channel B and repeating steps 7 through 9 in a similar fashion. Voltage measurements taken at SUM B and DIFF B. Results for both Channels should be the same. 11. Compare results to that listed in Table 3. TABLE 3. TEST SUM TYP DIFF TYP (VRMS) (VRMS) Channel to Channel Transhybrid Balance Channel A to B Channel B to A 18.45m 20.79m Intra-Channel Transhybrid Balance Channel A Channel B 0.986 0.990 TRANSHYBRID BALANCE (dB) 1.009 1.007 -34.7 -33.7 64.9m 67.0m -23.6 -23.4 Test #7 Channel A to Channel B Gain This demo board is configured to have a Channel to Channel gain of 1 or 0dB. This test will illustrate a procedure for calculating the proper R4 resistor value to achieve a Channel Application Note 9813 Discussion Channel to Channel gain is dependent upon: the 2-wire to 4-wire and the 4-wire to 2-wire gains of the HC5503X being one, the gain setting resistors of the differential amplifier (R4 , R5 , R14 , and R15), the resistance of the Cross Point Switch (Rx) and resistors R6 and R16 (Reference Figure 5). The resistance values of R6 and R16 are generally set to 604Ω for impedance matching to a transformer line card. If impedance matching to a 600Ω transformer is not a design requirement, then the values of R6 and R16 are not critical and can be set to match various impedances. It is important however, that R6 equal R16 . Figure 2 is a simplified version of the Junctor circuit and shows the critical components required to calculate the optimum R14 value to obtain a Channel A to Channel B gain of one. Because the 2-wire to 4-wire gain of the HC5503X is one, the voltage appearing at V1 is the tip to ring voltage of Channel A (Summing amplifier configured for a gain of one). The tip to ring voltage of Channel B is equal to the voltage at VO, because the 4-wire to 2-wire gain of the HC5503X is also one. Writing an equation for VO in terms of V1 will enable the gain to be set to one and the corresponding resistor values determined. Equation 4 can be used to determine the output voltage of the differential amplifier, and therefore the tip to ring voltage of Channel B, in terms of the voltage at V2. Equation 8 can be used for the calculation of R14 to achieve a Channel A to Channel B Gain of one. A similar analysis for the calculation of R4 to achieve a Channel B to Channel A gain of one is given in Equation 9. R X ′ R 4 = R 5 1 + ---------- R6 (EQ. 9) The value of R14 and R4 can now be determined for any network resistance. The network resistance is defined as the total resistance between the Junctor inputs/outputs. In the case of the demo board the network resistance is the resistance of the Cross Point Switch (50Ω) and R10 (100Ω). If R1 = R11 = R2 = R12 = R5 = R15 = 10kΩ, R6 = R16 = 604Ω and the Network = 150Ω then R4 = 12.48kΩ. Closest standard value is 12.7kΩ. If the Network resistance is equal to 50Ω (Single CD22M3493 Cross Point), then R4 = 10.83kΩ. Closest standard value is 10.7kΩ. CHANNEL A R2 10kΩ R1 10kΩ R5 10kΩ 5V V1 R6 600Ω - + JUNC A -5V V1 (EQ. 4) VO CHANNEL B (EQ. 5) (EQ. 6) Dividing both sides by V1 yields an equation for Channel A to Channel B gain. R 16 R 14 VO ChannelB --------- = ----------------------------- = ---------------------------------------- 1 + ---------- R 15 V1 ChannelA R 6 + R X ′ + R 16 (EQ. 7) Setting V0/V1 equal to one and rearranging to solve for R14 , assuming R6 = R16 , yields Equation 8. R X ′ R 14 = R 15 1 + ---------- R6 (EQ. 8) 4-4 R10 100Ω R16 600Ω RX´ 150Ω -5V R12 10kΩ 5V - + -5V R 16 R 14 VO = V1 ---------------------------------------- 1 + ---------- R 15 R 6 + R X ′ + R 16 R10 X POINT 50Ω RX´ = RX + R10 5V + R11 10kΩ Substituting Equation 5 into Equation 4 and defining RX´ = RX + R10 . Where RX´ is the total network resistance connecting Junctor A and Junctor B input/outputs. RX DIFFERENTIAL AMPLIFIER The voltage at V2, with respect to V1, is: R 16 V2 = ------------------------------------------------------- V1 R 6 + R X + R 10 + R 16 R6 600Ω V2 - R 14 VO = V2 1 + ---------- R 15 NETWORK to Channel gain of 1 with any Cross Point or network used to connect the two line cards. Also included is an easy procedure to verify the calculations. R14 12.7kΩ R15 10kΩ R16 600Ω JUNC B V2 TRANSMIT OUTPUT OF CHANNEL B IS ZERO FIGURE 2. CHANNEL TO CHANNEL TRANSHYBRID BALANCE Verification The following procedure can be used to verify the above calculations. Setup 1. Connect the power supplies to the Evaluation board. 2. Set VBAT to -48V, VCC to +5V and VEE to -5V. 3. Set the DPDT switch (S1) to Junctor operation. This connects the Onboard Op Amp, Cross Point Switch and the second HC5503X SLIC to the Transmit and Receive outputs of Channel A. 4. Terminate tip and ring of both Channel A and Channel B with a 600Ω load. Application Note 9813 5. Connect a sine wave generator in parallel with the 600Ω load across tip and ring of Channel A. The output of this generator needs to be floating. The voltage at V2, with respect to V1, where RX = resistance of Cross Point Switch is: 6. Set the generator for 1VRMS and 1kHz. R X + R 10 + R 16 V2 = ------------------------------------------------------- V1 R X + R 10 + R 16 + R 6 7. Measure the AC voltage across tip and ring (VTR) of both Channels A and B. 8. The Channel A to Channel B Gain is calculated using the following formula in Equation 10. VTR ( channelB ) dB = 20 log ---------------------------------------------VTR ( channelA ) (EQ. 10) 9. To measure Channel B to Channel A Gain connect the sine wave generator in parallel with the 600Ω load across tip and ring of Channel B and repeating steps 7 and 8 in a similar fashion. Results for both Channels should be about the same. 10. Compare results to that listed in Table 4. TABLE 4. Channel A to Channel B Gain 1.0074 1.0063 -0.01 Channel B to Channel A Gain 1.0035 1.0068 -0.03 Test #8 Intra-Channel Transhybrid Balance with Different Loads This evaluation board is configured to give the optimum Intra-Channel Transhybrid Balance for an impedance of 150Ω between the two Junctor inputs/outputs. This test will illustrate a procedure for calculating the proper R4 and R14 resistor values to optimize the Intra-Channel Transhybrid Balance when a different Cross Point or network is used. Also included is an easy procedure to verify the calculations. Discussion Substituting Equation 12 into Equation 11, setting V0 equal to Zero, defining RX´ = RX + R10 and rearranging to solve for R4: R 5 ( R X ′ + R 16 ) R 4 = --------------------------------------R 16 (EQ. 13) Equation 13 can be used for the calculation of R4 to achieve a good Intra-Channel Transhybrid Balance in Channel A. A similar analysis for Channel B is given in Equation 14. R 15 ( R X ′ + R 6 ) R 14 = ---------------------------------------R6 (EQ. 14) The value of R4 and R14 can now be determined for any network resistance. In the case of the demo board, the network resistance (RX´) is the resistance of the Cross Point Switch (50Ω) and R10 (100Ω). If R1 = R11 = R2 = R12 = R5 = R15 = 10kΩ, R6 = R16 = 604Ω and the Network = 150Ω then R4 = 12.48kΩ. Closest standard value is 12.7kΩ . If the Network resistance is equal to 50Ω (Single CD22M3493 Cross Point), then R4 = 10.83kΩ . Closest standard value is 10.7kΩ . Notice that the calculated value of R4 and R14 for both Channel to Channel and Intra-channel are the same. This is because the gain from Channel to Channel is set for one. If the Channel to Channel gain was set to anything other than one, the Intra-channel Transhybrid Balance would become unacceptable. Proper operation of this circuit requires that the Channel to Channel gain be set to one. R6 DIFFERENTIAL AMPLIFIER Intra-Channel Transhybrid Balance is performed by the Differential Amplifier (Reference Figure 3). The goal is to cancel all of the transmit signal of Channel A by the Differential Amplifier, so that none of the transmit signal is feed back into the receive terminal of channel A. The transmit signal can be cancelled by the differential amplifier by adjusting the value of resistor R4 . The value of R4 is dependent upon: the resistance value of R6 , the resistance of the network that connects the two Junctor inputs/outputs together (Cross Point + R10) and resistor R16 . Figure 3 is a simplified version of the Junctor circuit and shows the critical components required to calculate the optimum R4 value for Intra-Channel Transhybrid Balance. Equation 11 is the characteristic equation for the output voltage of the Differential Amplifier. R4 R 4 VO = V1 1 + ------- – V2 ------R5 R 5 (EQ. 11) 4-5 V1 V2 600Ω VO 5V NETWORK TEST TIP TO RING TIP TO RING CHANNEL A CHANNEL B GAIN (VRMS) (VRMS) (dB) (EQ. 12) + - CHANNEL A -5V R2 10kΩ R1 10kΩ R4 12.7kΩ 5V CHANNEL B -5V X POINT 50Ω R10 100Ω R16 600Ω RX´ = RX + R10 JUNC A + R12 R10 R5 10kΩ R6 600Ω - RX V2 V1 RX´ 150Ω 5V R16 - + JUNC B 600Ω -5V TRANSMIT OUTPUT OF CHANNEL B IS ZERO FIGURE 3. INTRA-CHANNEL TRANSHYBRID BALANCE Application Note 9813 Verification TABLE 6. JUNCTOR CIRCUIT The following procedure can be used to verify the above calculations. Setup 1. Replace resistors R4 and R14 with a 10.7kΩ resistor as calculated above. Note, R14 is Channel B’s equivalent of Channel A’s R4 . 2. Connect the power supplies to the Evaluation board. 3. Set VBAT to -48V, VCC to +5V and VEE to -5V. 4. Set the DPDT switch (S1) to Junctor operation. This connects the Onboard Op Amp, Cross Point Switch and the second HC5503J SLIC to the Transmit and Receive outputs of Channel A. 5. Replace resistor R10 with a short. This will result in a network resistance of 50Ω total. 6. Terminate tip and ring of both Channel A and Channel B with a 600Ω load. 7. Connect a sine wave generator in parallel with the 600Ω load across tip and ring of Channel A. The output of this generator needs to be floating. CA324E Intersil Quad Op Amp. R1 , R2 , R3 , Transhybrid Balance and Gain setting resistors for R11 , R12 , R13 the Summing Amplifiers. R4 , R5 , R14 , R15 Transhybrid Balance and Gain setting resistors for the Differential Amplifiers. C8 , C17 , C25 , Compensation Capacitors to roll of the high freC26 , C23 , C24 quency gain of the Summing and Differential Amplifier. C23 and C24 prevent a DC loop. R6 , R16 Provides a 600Ω termination looking into the Junctor input. R10 Series resistor to bring the total resistance of the “Network” to 150Ω. The “Network” is defined as the total resistance that connects Junctor A to Junctor B. C4 , C5 , C6 , C7, C21, C22 AC decoupling capacitors for the HC5503X Transmit (TX) and Receive (RX) outputs. CDM22M3493 Cross Point Switch. The resistance of the switch (X0 to Y0) is approximately 50Ω. S1 DPDT Switch used to connect the SLIC’s Transmit and Receive outputs of Channel A to either banana jacks TX and RX or the onboard Op Amp and Cross Point for evaluation of the Junctor circuit. Q1 , Q2 , R7 , R8 , R 9 , D 9 Automatic on/off controller of the Cross Point Switch. This circuit senses the SHD outputs of both SLICs. If both SLICs are in the off-hook condition, then the Cross Point Switch is activated and the Junctor A and Junctor B outputs are connected together. If either SLIC is in the On-hook condition, the Cross Point Switch is off and Junctor A and Junctor B outputs are disconnected. 8. Set the generator for 1VRMS and 1kHz. 9. Connect an AC volt meter between test point SUM A and ground. This will measure the AC voltage at the input to the Differential Amplifier (SUM A). 10. Connect an AC volt meter between test point DIFF A and ground. This will measure the AC voltage at the output of the Differential Amplifier (DIFF A). 11. The Intra-Channel Transhybrid Balance is calculated using the following formula in Equation 15. DIFFA dB = 20 log ------------------SUMA (EQ. 15) 12. To measure Intra-Channel Transhybrid Balance on Channel B, connect the sine wave generator in parallel with the 600Ω load across tip and ring of Channel B and repeating steps 8 through 11 in a similar fashion. Voltage measurements taken at SUM B and DIFF B. Results for both Channels should be the same. 13. Compare results to that listed in Table 3 section “Intra-Channel Transhybrid Balance.” Functional Circuit Component Descriptions A brief description of each component is provided below. The components will be grouped by function to provide further insight into the operation of the HC5503C/J/T board. TABLE 7. FILTER CAPACITOR C1 , C18 C1 and C18 are required for proper operation of the SLIC’s loop current limit function. TABLE 8. SUPPLY DECOUPLING CAPACITORS C2 , C 3 , C9 -C16 , C19 , C20 Supply decoupling capacitors. TABLE 9. SHD LEDs R9 , R20 , D9 , R9 and R20 are the Current limiting resistors for the D10 SHD LEDs (D9 and D10). TABLE 10. PULLUP RESISTORS R17 , R19 Pull up resistors (R17 , R19). Required for proper operation of the SLIC. TABLE 5. TWO WIRE SIDE, TIP AND RING RB1 , RB2 , RB3 , RB4 , RB5 , RB6 , RB7 , RB8 D1 , D2 , D3 , D4 , D5 , D6 , D7 , D8 Feed resistors (RB1 , RB2 , RB3 , RB4 , RB5 , RB6 , RB7 and RB8) that set the 2-wire impedance to 600Ω. RB2 , RB4 , RB6 and RB8 are used for loop current detection. RB1 , RB3 , RB5 and RB7 are used for current limiting during a surge event. Secondary surge protection. 4-6 Reference [1] HC5503J - Future Product. For more information call Don LaFontaine at (321) 729-5604. Application Note 9813 Schematic Diagram for Standard Operation 5V D11 R17 1K TIP RB1 1 RB2 8 RX R18 510 6 12 RS SHD C6 U1 9 VBAT 19 RX HC5503X TIP FEED T3 VB(INT) / RF RB4 T2 2 RING RING VBAT RB3 C7 TIP 22 TX CHANNEL A TX T1 C1 BGND DGND AGND 10 C 11 2 18 S1 17 STANDARD OPERATION 16 4 VCC 21 C 3 3 5 -48V PIN NUMBERS GIVEN FOR 22 PIN DIP C1 VCC FIGURE 4. APPLICATION SCHEMATIC FOR STANDARD OPERATION CHANNEL A HC5503 PATH FOR CHANNEL-TO-CHANNEL TRANSHYBRID CROSS POINT SWITCH JUNCTOR CHANNEL B JUNCTOR HC5503 PATH FOR INTRA-CHANNEL TRANSHYBRID FIGURE 5. INTRA-CHANNEL AND CHANNEL-TO-CHANNEL PATHS THROUGH THE SYSTEM HC5503C/J/T Evaluation Board Parts List VALUE TOLERANCE RATING SLIC COMPONENT U1 U2 HC5503X HC5503X C2 , C19 0.01µF 20% 100V Quad Op Amp U3 CA324E C3 , C20 0.01µF 20% 50V C4 , C5 , C6 , C7 , C21 , C22 0.47µF 20% 50V C8 , C17 , C25 , C26 .001µF 10% 50V C23 , C24 0.82µF 20% 50V Cross Point Switch VALUE U4 TOLERANCE RATING CD22M3493 COMPONENT R1 , R2 , R3 , R5 , R9 , R11 , R12 , R13 , R15 10kΩ 1% 1/4W RB1 , RB2 , RB3 , RB4 , RB5 , RB6 , RB7 , RB8 150Ω 1% 2W R8 5.62kΩ 1% 1/4W C9 , C11 , C13 , C15 Supply Decoupling 0.1µf 10% 50V R4 , R14 12.7kΩ 1% 1/4W C10 , C12 , C14 , C16 Supply Decoupling 0.01µF 10% 50V R6 , R16 604Ω 1% 1/4W D1 , D2 , D3 , D4 , D5 , D6 , D7 , D8 , D11 1N40007 n/a 100V, 1A R18 , R20 510Ω 5% 1/4W D9 , D10 R7 , R17 , R19 1.0kΩ 5% 1/4W S1 C1 , C18 0.33µF 10% 50V R10 4-7 LED, RED SPDT CO PC Mount Switch 100Ω 1% 1/4W Application Note 9813 Schematic Diagram for Junctor Application 5V D11 R17 1K SUM A 6 RS SHD U1 TIP RB1 1 RB2 8 D2 CH A D4 SLIC HC5503X TIP TIP FEED 9 VB(INT) / RF RING VBAT RING 10 BGND DGND AGND C2 11 5 21 C1 VCC C3 S1 JUNCTOR OPERATION R3 R2 R4 R6 + C13 C15 C14 5V C1 5V VCC D9 U4 CD22M3493 CROSS POINT SWITCH R8 DATA Q2 5V D6 CH B D8 8 RX TIP TIP FEED SLIC HC5503X TX T3 9 VB(INT) / RF T2 T1 RING C1 RING 19 + C22 22 18 C23 C26 R13 R12 -5V R14 R15 C17 5V R11 R16 - RB8 2 5V C21 SHD D5 VBAT D7 R10 DIFF B -5V U2 1 Y0 SUM B R20 510 12 -5V AX0 AX1 AX2 AX3 AY0 AY1 AY2 RESET R9 D10 RB6 X0 VSS STROBE Q1 TIP RB5 C16 -5V 3 AUTOMATIC ON/OFF CONTROLLER RS JUNC A -5V 4 R7 R19 1K 6 R5 C8 - VCC -48V -5V 5V R1 16 T1 2 RB3 C25 17 T2 RB4 C24 C5 18 T3 + - 22 TX 5V C4 19 RX D1 VBAT D3 DIFF A R18 510 12 VBAT RB7 BGND DGND AGND 10 C19 11 -48V 5 + 17 C9 4 C10 VCC 21 C20 3 VCC JUNC B -5V 16 C11 C12 U3 CA324E QUAD OP AMP C18 PIN NUMBERS GIVEN FOR 22 PIN DIP FIGURE 6. APPLICATION SCHEMATIC FOR JUNCTOR OPERATION All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 4-8