DATASHEET

ESIGNS
NEW D
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MENDE 503PRC
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HC5
Data Sheet
June 2004
Low Cost 24V SLIC For PABX/Key
Systems
HC5503
FN4344.5
Features
• Wide Operating Battery Range (-21V to -44V)
The Intersil HC5503 low cost SLIC is optimized for use in
small Analog or mixed Analog and Digital Key Telephone
Systems (KTS) or PBX products. The low component count
solution and surface mount package options, enable a small
desktop Key System/PBX product to be achieved. The
internal power dissipation of the end product is minimized by
the low power consumption and minimal power supply
voltage requirements of the HC5503.
The HC5503 integrated solution provides higher quality,
higher reliability and better performance solution than a
transformer, thick film hybrid or discrete analog subscriber
interface design.
The HC5503 is designed in a Dielectrically isolated bipolar
technology and is inherently latch proof and does not require
hot plug or power supply sequencing precautions.
• Single Additional +5V Supply
• 25mA Short Loop Current Limit
• Ring Relay Driver
• Switch Hook and Ring Trip Detect
• Low On-Hook Power Consumption
• On-Hook Transmission
• ITU-T Longitudinal Balance Performance
• Loop Power Denial Function
• Thermal Protection
• Supports Tip, Ring or Balanced Ringing Schemes
• Low Profile Surface Mount Packaging
• Pin Compatible with Industry Standard HC5504B SLIC
Ordering Information
PART NUMBER
TEMP.
RANGE (°C)
• Pb-free Available
PACKAGE
PKG.
DWG. #
HC5503CB
0 to 75
24 Ld SOIC
M24.3
HC5503CBZ (Note)
0 to 75
24 Ld SOIC (Pb-free) M24.3
HC5503CBZ96
(Note)
0 to 75
24 Ld SOIC (Pb-free) M24.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
1
Applications
• Analog Subscriber Line Interfaces in Analog Key Systems
and Digital ISDN PABX Systems
• Related Literature
- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1997-1998, Copyright Intersil Americas Inc. 1999, 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HC5503
Block Diagram
RING RELAY
DRIVER
RD
RFS
4-WIRE
INTERFACE
VF SIGNAL
PATH
RING TRIP
DETECTOR
C2
TX
RX
TIP
TF
2-WIRE
INTERFACE
RING
LOOP CURRENT
DETECTOR
RF
THERMAL LIMIT
SHD
LOGIC
INTERFACE
RS
RC
PD
VBAT
VCC
BIAS
AGND
BGND
C1
DGND
2
HC5503
Absolute Maximum Ratings (Note 1)
Thermal Information
Maximum Continuous Supply Voltages
(VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V
(VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
(VCC - VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
Relay Drive Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Thermal Resistance (Typical, Note 2)
Operating Conditions
Operating Temperature Range
HC5503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V
Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . 4.75V to 5.25V
Negative Supply Voltage (VBAT) . . . . . . . . . . . . . . . . . . -22V to -26V
High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V
Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V
JA (°C/W)
24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, VBAT = -24V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25°C. Min-Max Parameters are Over Operating Temperature Range.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
On Hook Power Dissipation
ILONG = 0 (Note 3), VCC = 5V
-
80
100
mW
Off Hook Power Dissipation
RL = 600, ILONG = 0 (Note 4), VCC = 5V
-
180
200
mW
Off Hook IVCC
RL = 600, ILONG = 0 (Note 3), TA = 0°C
-
-
6.0
mA
Off Hook IVCC
RL = 600, ILONG = 0 (Note 3), TA = 25°C
-
-
4.0
mA
Off Hook IBAT
RL = 600, ILONG = 0 (Notes 3, 4)
-
19
23
mA
Off Hook Loop Current
RL = 400, ILONG = 0 (Note 3)
-
22.9
-
mA
Off Hook Loop Current
RL = 400, VBAT = -21.6V, ILONG = 0 (Note 3),
TA = 25°C
17.5
-
-
mA
Off Hook Loop Current
RL = 200, ILONG = 0 (Note 3)
-
25
30
mA
(Note 4)
-
27.5
-
mA
-
70
-
mA
-
30
-
mA
-
140
-
mA
Fault Currents
TIP to Ground
RING to Ground
TIP to RING
(Note 4)
TIP and RING to Ground
Ring Relay Drive VOL
IOL = 62mA
-
0.2
0.5
V
Ring Relay Driver Off Leakage
VRD = 12V, RC = 1 = HIGH, TA = 25°C
-
-
25
A
Ring Trip Detection Period
RL = 600(Note 5)
-
2
3
Ring Cycles
5
-
10.5
mA
-
2
-
mA
Switch Hook Detection Threshold
Loop Current During Power Denial
3
RL = 200
HC5503
Electrical Specifications
Unless Otherwise Specified, VBAT = -24V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25°C. Min-Max Parameters are Over Operating Temperature Range. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Dial Pulse Distortion
(Note 4)
0
-
0.5
ms
Receive Input Impedance
(Note 5)
-
90
-
k
Transmit Output Impedance
(Note 5)
-
10
20

2-Wire Return Loss
Referenced to 600 +2.16F (Note 4)
SRL LO
-
15.5
-
dB
ERL
-
24
-
dB
SRL HI
-
31
-
dB
53
58
-
dB
2-Wire On Hook
53
58
-
dB
4-Wire Off Hook at 1kHz
50
58
-
dB
-
0.05
0.2
dB
-3.8
-4.0
-4.2
dB
-
0.02
0.05
dB
-
1
5
dBrnC
-
-89
-85
dBm0p
-
1
5
dBrnC
-
-89
-85
dBm0p
-
-
2
s
30
40
-
dB
2-Wire to 4-Wire (On-hook)
2.5
-
-
VPEAK
4-Wire to 2-Wire (Off-hook, RL = 600
3.1
-
-
VPEAK
+3 to -40dBm
-
-
0.05
dB
-40 to -50dBm
-
-
0.1
dB
-50 to -55dBm
-
-
0.3
dB
1VRMS 200Hz - 3400Hz, (Note 4) IEEE Method
0°C  TA  75°C
Longitudinal Balance
2-Wire Off Hook
Insertion Loss
0dBm Input Level, Referenced 600
2-Wire to 4-Wire at 3.4kHz
VTR to VO
VO is the Output of the Transhybrid
Amplifier
4-Wire to 2-Wire at 300Hz
Frequency Response
200 - 3400Hz Referenced to Absolute Loss at 1kHz
and 0dBm Signal Level (Note 4)
Idle Channel Noise,
2-Wire to 4-Wire
Idle Channel Noise,
4-Wire to 2-Wire
(Note 4)
Absolute Delay
(Note 5)
2-Wire to 4-Wire, 4-Wire to 2-Wire
Trans Hybrid Loss
Balance Network Set Up for 600 Termination at
1kHz
Overload Level
VCC = +5V
Level Linearity
At 1kHz, (Note 4) Referenced to 0dBm Level
2-Wire to 4-Wire, 4-Wire to 2-Wire
4
HC5503
Electrical Specifications
Unless Otherwise Specified, VBAT = -24V, VCC = 5V, AG = BG = DG = 0V, Typical Parameters
TA = 25°C. Min-Max Parameters are Over Operating Temperature Range. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
35
-
-
dB
VCC to Transmit
35
-
-
dB
VBAT to 2-Wire
20
-
-
dB
VBAT to Transmit
20
-
-
dB
35
-
-
dB
VCC to Transmit
35
-
-
dB
VBAT to 2-Wire
35
-
-
dB
VBAT to Transmit
35
-
-
dB
-
-
20
A
Logic ‘0’ VIL
-
-
0.8
V
Logic ‘1’ VIH
2.0
-
5.5
V
-
0.1
0.4
V
2.7
-
5.0
V
Power Supply Rejection Ratio
(Note 4),
30 - 60Hz, RL = 200
VCC to 2-Wire
VCC to 2-Wire
200 - 16kHz, RL = 200
Logic Input Current (RS, RC, PD)
0V  VIN 2.4V
Logic Inputs
SHD Output
ILOAD 800A, VCC = 5V
Logic ‘0’ VOL
ILOAD 40A, VCC = 5V
Logic ‘1’ VOH
NOTES:
3. ILONG = Longitudinal Current.
4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.
5. Guaranteed by design, not tested.
5
HC5503
The received audio signal RX is fed into the tip feed amplifier
and appears at the tip feed terminal. It is also fed through the
ring feed amplifier and is inverted. Thus, a differential signal
of 2VRX appears between tip feed and ring feed. The RX
signal causes AC audio currents to flow around the loop
which are then AC coupled to the earpiece of the telephone
set.
Design Information
Line Feed Amplifiers
The line feed amplifiers are high power operational
amplifiers and are connected to the subscriber loop through
150 of feed resistance as shown in Figure 1. The feed
resistors and synthesized impedance via feedback provide a
600 balanced load for the 2-wire to 4-wire transmission.
2-Wire Impedance Matching
The tip feed amplifier is configured as a unity gain
noninverting buffer. A -4V bias (derived from the negative
battery (VBAT) in the bias network) is applied to the input of
the amplifier. Hence, the tip feed DC level is at -4V. The
principal reason for this offset is to accommodate sourcing
and sinking of longitudinal noise currents up to 15mARMS
without saturating the amplifier output and to provide
sufficient overhead for receive signals. The tip feed amplifier
also feeds the ring feed amplifier, which is configured as a
unity gain inverting amplifier as seen from the tip feed
amplifier. The noninverting input to the ring feed amp is
biased at a VBAT/2. Looking into this terminal the amplifier
has a noninverting gain of 2. Thus, the DC output at ring
feed is:
The HC5503 is optimized for operation with a -24V battery.
Impedance matching to a 600 load, is achieved through
the combination of the feed resistors (RB1, RB2) and
negative feedback through resistor R2 (reference Figure 1).
RB1 and RB2 are sense resistors that detect loop current
and provide negative feedback to synthesize the remaining
300 required to match a 600 line.
The impedance looking into the tip terminal is 150 (RB1)
plus the synthesized impedance of the tip amplifier. The
synthesized tip impedance is equal to the tip feed voltage Va
divided by IL. (Note, the tip feed amplifier is a voltage
follower. Thus, the tip feed voltage is equal to the receive
input voltage VRX , both are labeled Va.) The synthesized
impedance of the ring terminal is calculated the same way
and is the ring feed voltage divided by IL. (Note, the ring
feed voltage is equal in magnitude to the tip feed voltage, but
opposite in phase as a result of the ring feed amplifier gain.)
VRF(DC) = (4 + VBAT) Volts
For a -24V battery, VRF = -20V. Hence, the nominal battery
feed across the loop provided by the SLIC is 16V. When the
subscriber goes off-hook this DC feed causes current
(metallic current) to flow around the loop.
Va
+ IL
TIP
TO TRANSHYBRID OP-AMP
-
C3
R3
90k
+
TIP FEED
-
150
VIN
+ 4VDC
R2
(NOTE)
+
-
ZIN
+2
-
RB1 = RB2 = RS = 150
-
+
R
RING
R1
RX
RB1
+4RSIL
TX
C4
4RSIL
+
R
HC5503
RB2
RING FEED
150
- IL +
-
+
-
+
VBAT
2
(NOTE)
NOTE: Grounded for AC analysis.
FIGURE 1. IMPEDANCE MATCHING CIRCUITRY
6
INPUT
FROM
CODEC
HC5503
The value of Va, as a result of feedback through R2 from the
TX output, is given in Equation 1. Equation 1 is a voltage
divider equation between resistors R2 and the parallel
combination of resistors; R1, R3 and the internal 90k
resistor RINTERNAL. The Voltage on the transmit out (TX) is
the sum of the voltage drops across resistors RB1 and RB2
that is gained up by 2 to produce an output voltage at the
VTX pin that is equal to -4RSIL.
R 1 90k R 3
V a = -------------------------------------------------  V TX
R 1 90k R 3 + R 2
HC5503
FEED BACK
RX
R2
24.9k
To match a 600 line, the synthesized tip and ring impedances
must be equal to 150. The impedance looking into either the
tip or ring terminal is once again the voltage at the terminal (Va)
divided by the AC current IL as shown in Equation 2.
TX = -4RSIL
The voltage that is feed back into the RX pin is equal to the
voltage at VTX times the feedback factor (Equation 5).
V a = V TX  X 
(EQ. 5)
Where VTX is equal to -4RSIL (RS = 150)
(EQ. 2)
Substituting the value of 600IL for VTX in Equation 1 and
dividing both sides by IL results in Equation 3.
(EQ. 3)
Setting Va/IL equal to 150 and solving for R2 , given that
R1 = 10k, RINTERNAL = 90k and R3 = 150k the value of
R2 to match the input impedance of 600 is determined to
be 25.47k. (Note: nearest standard value is 24.9k
The amount of negative feedback is dependent upon the
additional synthesized resistance required for matching. The
sense resistors RB1 and RB2 should remain at 150 to
maintain the SHD threshold listed in the electrical
specifications. The additional synthesized resistance is
determined by the feed back factor X (Equation 4) which
needs to be applied to the transmit output and fed into the
RX pin of the HC5503. The feed back factor is equal to the
voltage divider between R2 and the parallel combination of
R1 , R3 and RINTERNAL , reference Figure 2.
R 1 90k R 3
FeedbackFactor = X = ------------------------------------------------R 1 90k R 3 + R 2
RINTERNAL
90.0k
FIGURE 2. FEEDBACK EQUIVALENT CIRCUIT
Where: VTX = -4RSIL = -600IL.
R 1 90k R 3
Va
-------= -------------------------------------------------  600
I L
R 1 90k R 3 + R 2
R1
10k
TX
(EQ. 1)
Va
Z Tipfeed = Z Ringfeed = -------- = 150
I L
R3
150k
(EQ. 4)
So:
Va
X = ------------------I L 600
(EQ. 6)
But, from Equation 2:
Va
-------= 150
I L
(EQ. 7)
Therefore:
Va
150
1
X = ----------- = ---------- = --4
600
V TX
(EQ. 8)
Equation 8 shows that 1/4 of the TX output voltage is
required to synthesize 150 at both the Tip feed and Ring
feed amplifiers.
To match a 900 load would require 300 worth of
synthesized impedance (300 from RB1 + RB2 and 600
from the Tip feed + Ring feed amplifiers).
Setting Va/IL equal to 300 and solving for R2 in Equation 3,
given that R1 = 10k, RINTERNAL = 90k and R3 = 150k
the value of R2 to match the input impedance of 900 is
determined to be 8.49k (Note: nearest standard value is
8.45k). The feed back factor to match a 900 load is 1/2
(300/600).
The selection of the value of 150k for R3 is arbitrary. The
only requirement is that it be large enough to have little effect
on the parallel combination between RINTERNAL (90k) and
R1 (10k). R3 should be greater then 90k.
The selection of the value of 10k for R1 is also arbitrary.
The only requirement is that the value be small enough to
offset any process variations of RINTERNAL and large
enough to avoid loading of the CODEC’s output. A value of
10k is a good compromise.
7
HC5503
2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is defined as the output voltage
VTX divided by the tip to ring voltage (VTR). Where:
VTX = -4RSIL = -600IL and VTR = (RL)IL = 600IL. The
2-wire to 4-wire gain is therefore equal to -1.0, as shown in
Equation 9.
– 600 I L
V TX
A 2 – 4 = ----------- = ---------------------- = – 1.0
V TR
600I L
(EQ. 9)
VRX for the recommended values of R1 and R2 is given in
Equations 15 and 16. For impedance matching to a load
other than 600, recalculate the parallel impedances R1 ,
R2 and substitute into Equation 15. The 4-wire to 2-wire
gain is recalculated by using the Equations below.
8.49k
17.25k
V RX = V TF =  ---------------------------------------------- V TX +  --------------------------------------------- V IN
 8.49k + 24.9k
 17.25k + 10k
(EQ. 15)
V RX = V TF =  0.25 V TX +  0.633 V IN
4-Wire to 2-Wire Gain
The 4-wire to 2-wire gain is defined as the output voltage
VTR divided by the input voltage, VIN . To determine the
4-wire to 2-wire gain we need to define VTR in terms of VIN .
The voltage at VTR is the loop current times the load
impedance ZL .
V TR = I L  Z L = I L  Z O
(EQ. 10)
For optimum 2-wire return loss, the input impedance of the
SLIC (ZO) must equal the load impedance (ZL) of the line. All
Equations going further assume ZL= ZO .
The loop current IL is the total voltage across the loop
divided by the total resistance of the loop. The total voltage
across the loop is the sum of the tip feed voltage (VTF) and
the ring feed voltage (VRF) where VTF = -VRF . The total
resistance is the sum of the sense resistors RB1 and RB2
and the load ZL (ZL +2RS). The total loop current is defined
in Equation 11.
2  V TF 
V TF – V RF
I L = ---------------------------- = -------------------------Z O + 2R S
Z O + 2R S
(EQ. 11)
(EQ. 16)
Substituting Equation 16 into Equation 13:
 2   0.25 V TX +  0.633 V IN 
V TR =  ------------------------------------------------------------------------- Z O
Z O + 2R S


(EQ. 17)
From Equation 10:
V TR
I L = ----------ZO
(EQ. 18)
From Equation 1:
V TX = – 4RSI L
(EQ. 19)
Substituting Equation 18 into Equation 19:
V TR
V TX = – 4RS ----------ZO
(EQ. 20)
Substituting Equation 20 into Equation 17:
ZO
V TR


V TR =  – 2RS ----------- + 1.266V IN -------------------------ZO

 Z O + 2R S
(EQ. 21)
Assuming RS = 150 and rearranging terms:
From Equation 10:
V TR
I L = ----------ZO
(EQ. 12)
Substituting Equation 12 into Equation 11 and solving for
VTR :
 2  V TF  
V TR =  -------------------------- Z O
 Z O + 2R S
(EQ. 13)
Using Superposition, the voltage at the receive input RX is
given as:
 R 1 
 R 2 
V RX = V TF =  ----------------------- V TX +  ----------------------- V IN
 R 1 + R 2
 R 2 + R 1
(EQ. 14)
Where R1 is the effective impedance that is formed by the
parallel combination of RINTERNAL (90k), R3 (150k), R1
(10k) and is equal to 8.49k. R2 is the effective
impedance that’s formed by the parallel combination of
RINTERNAL (90k), R3 (150k), R2 (24.9k) and is equal
to 17.25k.
8
 1.266Z O 
300 
 1 + ----------------------- V
=  ------------------------ V IN

Z O + 300 TR
 Z O + 300
(EQ. 22)
The 4-wire to 2-wire gain (Given that: R1 = 10k, R2 = 24.9k
and R3 = 150kfor a 600 load is:
V TR
 1.266Z O 
A 4 – 2 = ----------- =  ------------------------ = 0.633 = – 3.96dB
V IN
 Z O + 600
(EQ. 23)
HC5503
The Transversal Amplifier (TA)
Whereas the feed amplifiers perform the 4-wire to 2-wire
transmission function, the transversal amplifier acts as the
2-wire to 4-wire hybrid. The TA is a summing amplifier
configured to reject common mode signals. It will reject 2wire common mode signals. RB1 and RB2 act as loop
current sense resistors. The voice signal output of the
amplifier is a function of the differential voltages appearing
across RB1 and RB2 .
VTF
TRANSVERSAL
AMP
VRING
VTX = -600 ILOOP
VTX
-
+
RB1
RB2
AVCL = 2
VTIP
R18
90K
KVTX
VRF
R19
1.8K
The transversal amplifier also has a DC output proportional
to the metallic current in the loop. The output voltage is
given by:
Voice signals on the loop are transformed by the TA into
ground referenced signals. Since the TA output has a DC
offset it is necessary to AC couple the output to any external
circuitry. Note, that during 4-wire to 2-wire transmission, the
transversal amplifier will have an audio signal at its output
proportional to the 4-wire audio receive signal and the loop’s
equivalent AC impedance. This is called the transhybrid
return, and must be cancelled (or balanced) out to prevent
an echo effect. Reference the Transhybrid Circuit section for
more information.
Loop Current Limiting
The maximum loop length for this application is a 533 load
across the feed amplifiers (24VSUPPLY - 8VOVERHEAD)/
30mAMAX loop current). However, on a short loop the line
resistance often approaches zero. Thus, a need exists to
control the maximum DC loop current that can flow around
the loop to prevent an excessive current drain from the
system battery. This limit is internally set to 30mA on the
HC5503. Figure 3 depicts the feedback network that
modifies the VRF voltage as a function of metallic current.
Figure 4 illustrates the loop current characteristics as a
function of line resistance.
As indicated above, the TA has a DC voltage output directly
proportional to the loop current. This voltage level is scaled
by R19 and R18 . The scaled level forms the ‘Metallic’ input
to one side of a Transconductance Amplifier.
VB5
IGM > 0,
FOR KVTX < VB5
VTX = 2(ITIP + IRING) (RB1 + RB2)
This DC level is used as an input to a comparator whose
output feeds into the logic circuitry as SH. This signal is used
to gate SHD output.
-
+
-4V
R21
-
VRF
+
RING
FEED
90K
C1
VB /2
FIGURE 3. DC LOOP CURRENT CHARACTERISTICS
The reference input to this amplifier is generated in the bias
network, and is equivalent to 30mA. When the metallic input
exceeds the set reference level, the transconductance
amplifier sources current. This current will charge C1 in
positive direction causing the VRF (Ring Feed) voltage to
approach the VTF (Tip Feed), effectively reducing the battery
feed across the loop which will limit the DC loop current. C1
will continue to charge until an equilibrium level is attained at
ILOOP = ILOOPmA (Max). The time constant of this feedback
loop is set by R21 (90k) and C1 which is nominally 0.33F.
The VRF voltage level is also modified to reduce or control
loop current during ring line faults (e.g., ground or power line
crosses), and thermal overload. Figure 8 illustrates this. The
thermal and fault current circuitry works in parallel with the
transconductance amplifier.
Longitudinal Amplifier
The longitudinal amplifier is an operational amplifier
configured as a closed loop differential amplifier with a
nominal gain of 0.1. The output is a measure of any
imbalance between ITIP and IRING. The transfer function of
this amplifier is given by:
VLONG = 0.1(ITIP - IRING) 150.
The gain factor is much less than one since ring voltage (up
to 150VPEAK) can appear at the Ring or Ring Feed Sense
terminals and are attenuated to avoid exceeding the
common mode range of the longitudinal amplifier’s input.
9
HC5503
HC5503 ILOOP SATURATION
ILOOP (mA)
30
20
RLOOP = RB1 + RB2 + ZTF + ZRF + RLINE + RSET
10
0
533
RLOOP ()
FIGURE 4. DC LOOP CURRENT CHARACTERISTICS
The longitudinal amplifier’s principal function is Ring Trip
Detection. The output of the amplifier after being filtered by R20
and C2 to attenuate AC signals is fed into a detector whose
output inhibits the ring relay driver to remove ringing signals
from the line in an off-hook condition, reference Figure 8.
owing to the 90 degree phase shift introduced by the low pass
filter (R20 , C2) the RS pulse will occur at the most negative
point of the attenuated ring signal that is fed into the ring trip
detector. Hence, when DC conditions are established for
SHD, the AC component actually assists ring trip taking place.
For a ring side injected ring system, the RS pulse should
occur at the positive zero crossing of the ring signal as it
appears at RFS. If ring synchronization is not used, then the
RS pin should be held permanently to a logic high of 5V
nominally: ring trip will occur asynchronously with respect to
the ring voltage. Ring trip is guaranteed to take place within
three ring cycles after the telephone going off-hook.
It is recommended that an RC snubber network is placed
across the ring relay contacts to minimize inductive kickback effects from the telephone ringer. Typical values for
such a network are shown in Figure 10.
150V
VRING
150VPEAK,
MAX
Ringing The Line
The Ring Command (RC) input is taken low during ringing.
This activates the ring relay driver (RD) output providing the
telephone is not off-hook or the line is not in a power denial
state. The ring relay connects the ring generator to the
subscriber loop. The ring generator output is usually an
80VRMS , 20Hz signal. The ring signal should not exceed
150V peak. Since the telephone ringer is AC coupled only
ring current will flow. This ringing current flows directly into
VBAT via a set of relay contacts. The high impedance
terminal RFS is provided so that the low impedance VRF
node can be isolated from the hot end of the ring path in the
battery referenced ring scheme.
The AC ring current flowing in the subscriber circuit will be
sensed across RB2 , and will give rise to an AC voltage at the
output of the longitudinal amplifier. R20 and C2 attenuate this
signal before it reaches the ring trip detector to prevent false
ring trip. C2 is nominally set at 1.0F.
When the subscriber goes off-hook, a DC path is established
between the output of the ring generator and the battery
ground or VBAT terminal. A DC longitudinal imbalance is
established since no tip feed current is flowing through the
tip feed resistors. The longitudinal amplifier output is driven
negative. Once it exceeds the ring trip threshold of the ring
trip detector, the logic circuitry is driven by GK to trip the ring
relay establishing an off-hook condition such that SHD will
become active as loop metallic current starts to flow.
In addition to its ability to be used for tip or ring injected
systems, the HC5503 can also be configured for systems
utilizing balanced ringing. The main advantage of balanced
ringing is that it tends to minimize cross coupling effects owing
to the differential nature of the ring tone across the line.
Figure 5 illustrates the sequence of events during ring trip with
ring synchronization for a tip injected ring system. Note that
10
RS
5V
>50s
0V
VC4
0V
RING
TRIP
THRESHOLD
SUBSCRIBER
GOES OFF-HOOK
C2 CHARGES
TO 0V
QUIESCENT
VALUE
RING RELAY
DC SHIFT OWING TO HAS TRIPPED
DC CURRENT DIFFERENCE
BETWEEN ITIP AND IRING
FIGURE 5. RING TIP SEQUENCE
Transhybrid Circuit
The purpose of the transhybrid circuit is to remove the
receive signal (RX) from the transmit signal (TX), thereby
preventing an echo on the transmit side. This is
accomplished by using an external op amp (usually part of
the CODEC) and by the inversion of the signal from the
4-wire receive port (RX) to the 4-wire transmit port (TX).
Figure 6 shows the transhybrid circuit. Because the voltage
at RX is 180 degrees out of phase with the voltage at TX , the
input signal will be subtracted from the output signal if I1
equals I2 . Node analysis yields the following Equation:
TX RX
I 1 + I 2 = ------- + -------- = 0
R4 R3
(EQ. 24)
The voltage at TX is the product of the 4-wire to 2-wire
(A4-2 = 0.633) and 2-wire to 4-wire (A2-4 = -1.0) voltage
gains, and is therefore equal to 0.633. The voltage at RX ,
when taking into account the negative feedback through R2 ,
HC5503
is the calculated value of 0.633 plus the feedback which is
1/4 TX (for matching to a 600 load, reference Equation 8).
The voltage at Rx is calculated in Equation 25.
1
R X = 0.633 – ---  0.633  = 0.474
4
(EQ. 25)
Substituting the values for TX and RX into Equation 24 and
setting them equal to each other, the values of R3 and R4
can then be determined.
0.474
0.633
--------------- = --------------R3
R4
(EQ. 26)
Setting the value of R3 to 150ksets the value of R4 to be
200k.
Notice that the input voltage for the incoming signal (I1) is
taken at RX , instead of the conventional method at the
CODEC (point A, Figure 6). This alternative method is used
because the tolerance effects of R1 on the transhybrid
balance are eliminated.
-
HC5503
RX
R3
I1
+
R4 200k
+
V0
I2
A
R1
R2
-
+
VIN
-
TX
CODEC/
FILTER
FIGURE 6. TRANSHYBRID CIRCUIT
Power Denial (PD)
Power denial limits power to the subscriber loop: it does not
power down the SLIC, i.e., the SLIC will still consume its
normal on-hook quiescent power during a power denial
period. This function is intended to “isolate” from the battery,
under processor control, selected subscriber loops during an
overload or similar fault status.
If PD is selected, the logic circuitry inhibits RC and switches in
a current source to C1 . The capacitor charges up to a nominal
-3.5V at which point it is clamped. Since tip feed is always at
-4V, the battery feed across the loop is essentially zero, and
minimum loop power will be dissipated if the circuit goes offhook. No signaling functions are available during this mode.
After power denial is released (PD = 1), it will be several
hundred milliseconds (300ms) before the VRF output
reaches its nominal battery setting. This is due to the RC
time constant of R21 and C1 .
11
The logic network utilizes I2L logic. All external inputs and
outputs are LS TTL compatible: the relay driver is an open
collector output that can sink 60mA with a VCE of 1V.
Figure 9 is a schematic of the combination logic within the
network. The external inputs RC (Relay Control) and PD
(Power Denial) allow the switch controller to ring the line or
deny power to the loop, respectively. The Ring
Synchronization input (RS) facilitates switching of the ring
relay near a ring current zero crossing in order to minimize
inductive kickback from the telephone ringer.
Line Fault Protection
The subscriber loop can exist in a very hostile electrical
environment. It is often in close proximity to very high
voltage power lines, and can be subjected to lightning
induced voltage surges. The SLIC has to provide isolation
between the subscriber loop and the PBX/Key telephone
system.
The most stringent line fault condition that the SLIC has to
withstand is that of the lightning induced surge.
R5
150k
The Logic Network
The Intersil monolithic SLIC, in conjunction with a simple low
cost diode bridge, can achieve up to 450V of isolation
between the loop and switch. The level of isolation is a
function of the packaging technology and geometry together
with the chip layout geometries. One of the principal reasons
for using DI technology for fabricating the SLIC is that it
lends itself most readily to manufacturing monolithic circuits
for high voltage applications.
Figures 10 shows the application circuit for the HC5503. A
secondary protection diode bridge is indicated which
protects the feed amplifiers during a fault. Most line systems
will have primary protection networks. They often take the
form of a carbon block or arc discharge device. These limit
the fault voltage to less than 450V peak before it reaches the
line cards. Thus when a transient high voltage fault has
occurred, it will be transmitted as a wave front down the line.
The primary protection network must limit the voltage to
less than 450V. The attenuated wave front will continue
down the line towards the SLIC. The feed amplifier outputs
appear to the surge as very low impedance paths to the
system battery. Once the surge reaches the feed resistors,
fault current will flow into or out of the feed amplifier output
stages until the relevant protection diodes switch on. Once
the necessary diodes have started to conduct all the fault
current will be handled by them.
If the user wishes to characterize SLIC devices under
simulated high voltage fault conditions on the bench, he should
ensure that the negative battery power supply has sufficient
current capability to source the negative peak fault current and
low series inductance. If this is not the case, then the battery
supply could be pulled more negative and destroy the SLIC if
the total (VCC + VBAT) voltage across it exceeds 75V.
HC5503
Pin Descriptions
24 PIN
SOIC
SYMBOL
DESCRIPTION
1
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop. Functions with the Ring terminal to
receive voice signals from the telephone and for loop monitoring purposes.
2
RING
An analog input connected to the RING (more negative) side of the subscriber loop. Functions with the Tip terminal to
receive voice signals from the telephone and for loop monitoring purposes.
3
RFS
Senses ring side of loop for ring trip detection. During ringing, the ring signal is inserted into the line at this node and
RF is isolated from RFS via a relay.
Positive Voltage Source - Most positive supply. VCC is typically 5V.
4
VCC
5
C1
Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation
of the loop current limiting function, and for filtering VBAT. Typical value is 0.3F, 16V.
6
DG
Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the
SLIC microcircuit.
7
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a positive pulse
transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected
systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive
going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is
near zero. If synchronization is not required, the pin should be tied to 5V.
8
RD
Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized.
9
TF
Tip Feed - A low impedance analog output connected to the TIP terminal through a 150 feed resistor. Functions with
the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current.
10
RF
Ring Feed - A low impedance analog output connected to the RING terminal through a 150 feed resistor. Functions
with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current.
11
VBAT
12
BG
13
SHD
15
PD
Power Denial - A low active TTL - Compatible logic input. When enabled, the switch hook detect (SHD) is not
necessarily valid, and the relay driver (RD) output is disabled.
16
RC
Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on
the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the
subscriber is not already off-hook (SHD = 0).
21
RX
Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input
is required. AC signals appearing at this input deferentially drive the Tip feed and Ring feed terminals, which in turn drive tip
and ring through 150 of feed resistance on each side of the line.
22
C2
Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This capacitor prevents
false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from nearby
power lines and other noise sources. Recommended value is 1.0F, 20V. This capacitor should be nonpolarized.
23
AG
Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive
input (RX) terminals.
24
TX
Transmit Output, Four Wire Side - A low impedance analog output which represents the differential voltage across Tip and
Ring. Transhybrid balancing must be performed beyond this output to completely implement two to four wire conversion. This
output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive
coupling to the next stage is essential.
14
NC
Used during production testing. For proper operation of the SLIC, this pin should float.
17, 18, 19,
20
NC
No internal connection.
Negative Voltage Source - Most negative supply. VBAT is typically -24V. Frequently referred to as “battery”.
Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground
terminal.
Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop currents
exceeding 10.5mA and disabled for loop currents less than 5mA.
NOTE: All grounds (AG, BG, and DG) must be applied before VCC or VBAT. Failure to do so may result in premature failure of the part. If a user
wishes to run separate grounds off a line card, the AG must be applied first.
12
HC5503
Pinout
HC5503 (SOIC)
TOP VIEW
TIP
1
24
TX
RING
2
23
AG
RFS
3
22
C2
VCC
4
21
RX
C1
5
20
N/C
DG
6
19
N/C
RS
7
18
N/C
RD
8
17
N/C
TF
9
16
RC
RF 10
15
PD
11
14
N/C
BG 12
13
SHD
VBAT
Functional Block Diagram
RING SYNC
RING COMMAND
RC
RD
RING
CONTROL
SHD SWITCH HOOK
DETECTION
LOOP
MONITORING
TIP
1/2 RING
RELAY
TIP
RING
TRIP
RS
+
-
150
DIFF
AMP
TX
TRANSMIT
OUTPUT
RX
RECEIVE
INPUT
TF
2-WIRE
LOOP
VBAT
SECONDARY
PROTECTION
BATTERY
FEED
+1
BG
VBAT
RF
RFS
1/2 RING
RELAY
LOOP
CURRENT
LIMITER
LINE
DRIVERS
150
RING
RING
RING
VOLTAGE
POWER DENIAL
PD
-1
SLIC MICROCIRCUIT
VBAT
FIGURE 7.
13
HC5503
Schematic Diagram
21
22
RX
C2
11
12
23
6
4
VBAT
BAT
GND
ANA
GND
DIG
GND
VCC
VCC
VB1
VB2
VB3
VB4
VB5
5V
VOLTAGE AND CURRENT
BIAS NETWORK
VCC
A-400
TIP FEED
AMP
TF
9
VBAT
R17
+
VB2
IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11
-
IB4
RING TRIP DETECTOR
R12
R7
TIP
R8
1
VCC
QD3 QD36
RING
FEED
SENSE
R9
3
R22
R11
R4
2
R1
IB7
-
VBAT
VBAT
R14
R18
R21
QD28
RC
THERMAL
LIMITING
LOAD CURRENT
LIMITING I
B2
16
RFC
V
- B5
PD
VB5
+
+
VBAT
13
VB1
IB6
QD27
SHD
SH
-
+
A-300
RING FEED
AMP
10
STTL
AND LOGIC
INTERFACE
VCC
VBAT/2 REFERENCE
-
+
SWITCH HOOK
DETECTOR
R6
VB2
14
IB1
VB3
IB6
R15
NC
GND SHORTS
CURRENT
LIMITING
VCC
A-100
TRANSV’L
I/V AMP
R16
VB4
IB8
+
R2
VBAT
+
VBAT
R5
V
VBAT
R23 CC
R3
RF
+
GK
R20
A-200
LONG’L
I / V AMP
VBAT
RING
VCC
-
R10
5V IB10 VCC
5V
15
R19
VBAT
IB5
R13
VBAT
VBAT
C1
TX
RS
RD
5
24
7
8
FIGURE 8. FUNCTIONAL SCHEMATIC
14
HC5503
Schematic Diagram
(Continued)
LOGIC GATE SCHEMATIC
GK
2
1
4
SH
6
8
7
9
5
12
16
10
13
11
15
TTL
TO
STTL
TTL
TO
STTL
RELAY
DRIVER
14
TTL
TO
STTL
TO
R21
STTL
TO
TTL
C
B
A
A
B
RS
RC
PD
C
RD
SHD
SCHOTTKY LOGIC
FIGURE 9. LOGIC NETWORK
Overvoltage Protection and Longitudinal
Current Protection
TABLE 1.
PARAMETER
TEST
CONDITION
PERFORMANCE
(MAX)
UNITS
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
Longitudinal
Surge
10s Rise/
1000s Fall
450 (Plastic)
VPEAK
High voltage surge conditions are as specified in Table 1.
Metallic Surge
10s Rise/
1000s Fall
450 (Plastic)
VPEAK
The SLIC will withstand longitudinal currents up to a
maximum or 10mARMS , 5mARMS per leg, without any
performance degradation.
T/GND
R/GND
10s Rise/
1000s Fall
450 (Plastic)
VPEAK
50/60Hz Current
T/GND
R/GND
11 Cycles
Limited to
10ARMS
315 (Plastic)
VRMS
15
HC5503
Application Circuit
SYSTEM CONTROLLER
R5 (NOTE 6)
+5V
13
RS1
CS1
D5
SHD
K1
8
TIP
1
K1A
RB1
9
Z1
PRIMARY
PROTECTION
MUST LIMIT
INPUT VOLTAGE
TO LESS THAN
450V
D2
D1
D4
D3
7
16
RS
PD
VOUT
RC
U2
R3
RD
TIP
TIP FEED
RX
R1
21
VIN
C3
HC5503
U1
CS2
3
R2
TX
RING FEED
RING FEED SENSE
C1
RS2
RB2
RING
C2
2
RING
R4
CODEC/FILTER
VBAT
-24V
10
K1B
15
-BAT
PTC
BGND
11
VBAT
-24V
C5
12
DGND
6
AGND
24
5
22
VCC
23
4
C6
C4
C2
C1
VCC
+5V
VBAT
-24V
NOTES:
6. R5 sets the 2-wire to 4-wire gain. R5 = 150k then A2-4 = 0dB. R5 = 75k then A2-4 = -6.0dB.
7. Secondary protection diode bridge recommended is a 2A, 200V type.
8. All grounds (AG, BG, and DG) must be applied before VCC or VBAT. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
9. Application shows Ring Injected Ringing, Balanced or Tip injected configuration may be used.
FIGURE 10. -24V APPLICATION CIRCUIT
Typical Component Values:
C1 = 0.33F, 20%, 20V.
R1 = 10k, 1%, 1/4W.
C2 = 1.0F, 10%, 20V.
R2 = 24.9k, 1%, 1/4W.
C3 = C4 = 0.47F, 20%, 30V.
R3 = R5 = 150k, 1%, 1/4W.
C5 , C6 = 0.01F, 30V.
R4 = 200k, 1%, 1/4W.
CS1 = CS2 = 0.1F, 200V typically, depending on VRING and
line length.
D1, D2 , D3 , D4 , D5 = 1N40007, 100V, 3A.
RB1 = RB2 = 150 (1% absolute value).
RS1 = RS2 = 1k, 1%, 1/4W.
16
Z1 = 250V to 350V transient protection.
PTC used as ring generator ballast.
HC5503
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
µ
B S
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N

NOTES:
MILLIMETERS
24
0o
24
8o
0o
7
8o
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
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