DATASHEET

Radiation Hardened Quad Differential Line Receiver
HS-26C32RH, HS-26C32EH
Features
The Intersil HS-26C32RH, HS-26C32EH are differential line
receivers designed for digital data transmission over balanced
lines and meets the requirements of EIA Standard RS-422.
Radiation hardened CMOS processing assures low power
consumption, high speed, and reliable operation in the most
severe radiation environments.
• Electrically screened to SMD #5962-95689
The HS-26C32RH, HS-26C32EH have an input sensitivity
typically of 200mV over the common mode input voltage
range of ±7V. The receivers are also equipped with input fail
safe circuitry, which causes the outputs to go to a logic “1”
when the inputs are open. Enable and Disable functions are
common to all four receivers.
• EIA RS-422 compatible inputs
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the “Ordering Information” table must be
used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95689. A “hot-link” is provided on our
homepage for downloading
• QML qualified per MIL-PRF-38535 requirements
• 1.2 micron radiation hardened CMOS
- Total dose . . . . . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (max)
• Latch-up free
• CMOS compatible outputs
• Input fail safe circuitry
• High impedance inputs when disabled or powered down
• Low power dissipation 138mW standby (max)
• Single 5V supply
• Full -55°C to +125°C military temperature range
Applications
• Line receiver for MIL-STD-1553 serial data bus
Ordering Information
ORDERING NUMBER
(Note 1)
INTERNAL
MKT. NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
5962F9568901QEC
HS1-26C32RH-8
Q 5962F95 68901QEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9568901QXC
HS9-26C32RH-8
Q 5962F95 68901QXC
-55 to +125
16 Ld FLATPACK
K16.A
5962F9568901V9A
HS0-26C32RH-Q
-55 to +125
Die
HS0-26C32RH/SAMPLE
HS0-26C32RH/SAMPLE
-55 to +125
Die
5962F9568901VEC
HS1-26C32RH-Q
Q 5962F95 68901VEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9568901VXC
HS9-26C32RH-Q
Q 5962F95 68901VXC
-55 to +125
16 Ld FLATPACK
K16.A
HS1-26C32RH/PROTO
HS1-26C32RH/PROTO
HS1- 26C32RH /PROTO
-55 to +125
16 Ld SBDIP
D16.3
HS9-26C32RH/PROTO
HS9-26C32RH/PROTO
HS9- 26C32RH /PROTO
-55 to +125
16 Ld FLATPACK
K16.A
5962F9568903VEC
HS1-26C32EH-Q
Q 5962F95 68903VEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9568903VXC
HS9-26C32EH-Q
Q 5962F95 68903VXC
-55 to +125
16 Ld FLATPACK
K16.A
5962F9568903V9A
HS0-26C32EH-Q
Q 5962F95 68903V9A
-55 to +125
Die
5962F9568901VYC
HS9G-26C32RH-Q (Note 2)
Q 5962F95 68901VYC
-55 to +125
16 Ld FLATPACK
K16.A
HS9G-26C32RH/PROTO
HS9G-26C32RH/PROTO (Note 2) HS9G-26C32RH/PROTO
-55 to +125
16 Ld FLATPACK
K16.A
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. The lid of these packages are connected to the ground pin of the device.
May 28, 2013
FN3402.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HS-26C32RH, HS-26C32EH
Logic Diagram
ENABLE
ENABLE DIN DIN
+
-
CIN CIN
BIN BIN
AIN AIN
+
+
+
DOUT
-
COUT
-
BOUT
-
AOUT
Pin Configurations
HS9-26C32RH, HS9-26C32EH
(16 LD FLATPACK)
MIL-STD-1835: CDFP4-F16
TOP VIEW
HS1-26C32RH, HS1-26C32EH
(16 LD SBDIP)
MIL-STD-1835: CDIP2-T16
TOP VIEW
AIN 1
AIN 2
16 VDD
AIN
1
16
VDD
15 BIN
AIN
2
15
BIN
AOUT
3
14
BIN
ENABLE
4
13
BOUT
COUT
5
12
ENABLE
CIN
6
11
DOUT
CIN
7
10
DIN
GND
8
9
DIN
14 BIN
AOUT 3
13 BOUT
ENABLE 4
COUT 5
12 ENABLE
CIN 6
11 DOUT
CIN 7
10 DIN
GND 8
9 DIN
Propagation Delay Timing
Diagram
Three-State Low Timing Diagram
VIH
VS
-VIN
+2.5V
INPUT
VSS
0V
+VIN = 0V
tPZL
-2.5V
VS = 50%
tPLZ
VOZ
tPHL
tPLH
VOH
INPUT
VT
OUTPUT
VW
VOL
OUTPUT
VOL
2
FN3402.5
May 28, 2013
HS-26C32RH, HS-26C32EH
Propagation Delay Load Circuit
Three-State Low Load Circuit
VDD
TEST
POINT
DUT
CL
RL
TEST
POINT
DUT
RL
CL
CL = 50pF
CL = 50pF
RL = 1000Ω
RL = 1000Ω
TABLE 2. THREE-STATE HIGH VOLTAGE LEVELS
Three-State High Timing
Diagrams
VIH
VS
INPUT
VSS
tPZH
HS-26C32RH
HS-26C32EH
UNITS
VDD
4.50
V
VIH
4.50
V
VS
2.25
V
VT
50
%
VW
VOH - 0.5
V
0
V
PARAMETER
GND
tPHZ
VOH
VT
OUTPUT
VW
VOZ
Three-State High Load Circuit
TEST
POINT
DUT
TABLE 1. THREE-STATE LOW VOLTAGE LEVELS
CL
HS-26C32RH
HS-26C32EH
UNITS
VDD
4.50
V
CL = 50pF
VIH
4.50
V
RL = 1000Ω
VS
2.25
V
VT
50
%
VW
VOL + 0.5
V
0
V
PARAMETER
GND
RL
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
FN3402.5
May 28, 2013
HS-26C32RH, HS-26C32EH
Die Characteristics
Top Metallization:
M1: Mo/Tiw
Thickness: 5800Å
M2: Al/Si/Cu
Thickness: 5800Å
DIE DIMENSIONS:
78 mils x 123 mils
(1970µm x 3120µm)
INTERFACE MATERIALS:
Worst Case Current Density:
<2.0 x 105A/cm2
Glassivation:
Bond Pad Size:
Type: SiO2
Thickness: 10kÅ ± 1kÅ
110µm x 100µm
Metallization Mask Layout
HS-26C32RH, HS-26C32EH
AIN
(1)
VDD
(16)
BIN
(15)
(14) BIN
AIN (2)
(13) BOUT
AOUT (3)
ENAB (4)
(12) ENAB
COUT (5)
(11) DOUT
(10) DIN
CIN (6)
(7)
CIN
4
(8)
GND
(9)
DIN
FN3402.5
May 28, 2013
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