DATASHEET

DATASHEET
Highly Efficient 3A Synchronous Buck Regulator
ISL85003, ISL85003A
Features
The ISL85003 and ISL85003A are synchronous buck regulators
with integrated high-side and low-side FETs. The regulator can
operate from an input voltage range of 4.5V to 18V while
delivering a very efficient continuous 3A current. This is all
delivered in a very compact 3mmx4mm DFN package.
• Input voltage range 4.5V to 18V
• Output voltage adjustable from 0.8V, ±1%
• Efficiency up to 95%
• Integrated boot diode with undervoltage detection
The ISL85003 is designed on Intersil’s proprietary fab process
that is designed to deliver very low rDS(ON) FETs with an
optimized current mode controller wrapped around it. The
high-side NFET is designed to have an rDS(ON) of 65mΩ while
the low-side NFET is designed to have an rDS(ON) of 45mΩ.
With these two FETs, the device delivers very high efficiency
power to the load.
• Current mode control
- DCM/CCM
- Internal or external compensation options
- 500kHz switching frequency option
- External synchronization up to 2MHz on ISL85003
The ISL85003 can automatically switch between DCM and
CCM for light-load efficiency in DCM. The switching frequency
in CCM is internally set to 500kHz.
• Open-drain PG window comparator
- Built-in protection
- Positive and negative overcurrent protection
- Overvoltage and thermal protection
- Input overvoltage protection
• Adjustable soft-start time on the ISL85003A
The device provides a maximum static regulation tolerance of
±1% over wide line, load and temperature ranges. The output
is user adjustable, with external resistors, down to 0.8V. Pulling
EN above 0.6V enables the controller. The regulator supports
prebiased output.
• Small 12 Ld 3mmx4mm Dual Flat No-Lead (DFN) package
Applications
Fault protection is provided by internal current limiting during
positive or negative overcurrent conditions, output and input
under and overvoltage detection and an over-temperature
monitoring circuit.
• Network and communication equipment
• Industrial process control
• Multifunction printers
Related Literature
• Point-of-load regulators
• AN1935, “ISL85003DEMO1Z, ISL85003ADEMO1Z
Evaluation Board User Guide”
• Standard 12V rail supplies
• Embedded computing
• AN1930, “ISL85003EVAL2Z, ISL85003AEVAL2Z Evaluation
Board User Guide”
• AN1965, “Effectively Using the Intersil Small Form Factor
Power Management Evaluation Boards”
L = 0.5V H = 1.20V POS EDGE 1
L = DE H = FPWM
SYNC
2
PG
OPEN DRAIN, ADD PULL-UP
3
EN
EN
THRESHOLD 1V, HYST 100mV
+0.8V ±8mV 4
AGND
FB
R2
R1
301k 57.1k 5
C1
COMP
1%
1%
4.7pF
6
AGND
OPTIONAL CAP
NO CAP: tSS = 2ms
For tSS>2ms, ADD CAP:
C[nF] = 4.1 * tSS[ms]-1.6nF
ISL85003
BOOT
PG
VDD
VIN
VIN
13
PGND
PHASE
PHASE
12
C3 0.1µF
11 C4 1µF
4.5 TO 18V
10
C5
10µF
C6
10µF
VIN
GND
8
7
2
OPEN DRAIN, ADD PULL-UP
3
EN
THRESHOLD 1V, HYST 100mV
+0.8V ±8mV 4
AGND
R2
R1
301k 57.1k 5
C1
1%
1%
4.7pF
6
PG
+5V
9
U1
+5V
MAX 3A
L1
fSW = 500kHz 4.7µH
C8
47µF
C9,22µF
VOUT
ISL85003A
C2
SS
22nF 1
SYNC
GND
BOOT
PG
VDD
EN
VIN
FB
VIN
COMP
PHASE
AGND
PHASE
PGND
SYNC
U1
13
tSS = 2ms, FIXED
DEVICE MUST BE
CONNECTED TO GND
PLANE WITH 8 VIAs.
12
C3 0.1µF
11 C4 1µF
+5V
4.5 TO 18V
10
9
C5
10µF
C6
10µF
VIN
GND
8
+5V
MAX 3A
L1
7
fSW = 500kHz 4.7µH
C8
47µF
C9,22µF
VOUT
GND
DEVICE MUST BE
CONNECTED TO GND
PLANE WITH 8 VIAs.
+5V
FIGURE 1A. ISL85003 VIN RANGE FROM 4.5V TO 18V, VOUT = 5V AND
INTERNAL COMPENSATION WITH EXTERNAL
FREQUENCY SYNC
FIGURE 1B. ISL85003A VIN RANGE FROM 4.5V TO 18V, VOUT = 5V
AND INTERNAL COMPENSATION WITH EXTERNAL
SOFT-START
FIGURE 1. TYPICAL APPLICATION SCHEMATICS
January 15, 2016
FN7968.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL85003, ISL85003A
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCM Control Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light-Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable, Soft-Start and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
16
16
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Regulator Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
17
17
17
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
19
19
Compensator Design Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
High DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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January 15, 2016
ISL85003, ISL85003A
Functional Block Diagram
1
SS (ISL85003A)
SOFT-START
CONTROL
BOOT
1
2
BOOT
REFRESH
SYNC (ISL85003)
VDD
12
11
PG
VIN
LDO
1.5ms
DELAY
10
VIN
FAULT
MONITOR
9
CSA
CIRCUITS
UNDERVOLTAGE
LOCKOUT
0.8V
3
EN
+
SLOPE COMP
REFERENCE
+
POR
+
FB
-
4
-
PHASE
EA
600k
GATE DRIVE
7
PGND
30pF
5
PHASE
8
13
COMP
OSCILLATOR
DCM
GND DETECT
DETECTOR
ZERO CROSS
DETECTOR
6
AGND
NEGATIVE
CURRENT
LIMIT
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
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January 15, 2016
ISL85003, ISL85003A
Pin Configurations
ISL85003A
(12 LD 3X4 DFN)
TOP VIEW
ISL85003
(12 ld 3X4 DFN)
TOP VIEW
SYNC
1
12 BOOT
SS
1
12 BOOT
PG
2
11 VDD
PG
2
11 VDD
EN
3
10 VIN
EN
3
PGND
9
VIN
5
8
6
7
FB
4
COMP
AGND
13
10 VIN
PGND
9
VIN
5
8
PHASE
6
7
PHASE
FB
4
PHASE
COMP
PHASE
AGND
13
Pin Descriptions
PIN
NUMBER
PIN
NAME
1
(ISL85003)
SYNC
Synchronization and mode selection input. Connect to VDD for CCM mode. Connect to AGND for DCM mode. Connect to an
external function generator for synchronization with the positive edge trigger. There is an internal 1MΩ pull-up resistor to VDD,
which prevents an undefined logic state in cases where SYNC is floating.
1
(ISL85003A)
SS
Soft-Start input. This pin provides a programmable soft-start. When the chip is enabled, the regulated 4µA pull-up current
source charges a capacitor connected from SS to ground. The output voltage of the converter follows the ramping voltage on
this pin. Without the external capacitor, the default soft-start is 2ms.
2
PG
Power-good open-drain output. Connect 10kΩ to 100kΩ pull-up resistor between PG and VDD or between PG and a voltage not
exceeding 5.5V. PG transitions high about 1ms after the switching regulator’s output voltage reaches the regulation threshold,
which is 85% of the regulated output voltage typically.
3
EN
Enable input. The regulator is held off when the pin is pulled to ground. The device is enabled when the voltage on this pin rises
above 0.6V.
4
FB
Feedback input. The synchronous buck regulator employs a current mode control loop. FB is the negative input to the voltage
loop error amplifier. The output voltage is set by an external resistor divider connected to FB. The output voltage can be set to
any voltage between the power rail (reduced by converter losses) and the 0.8V reference.
5
COMP
Compensation node. This pin is connected to the output of the error amplifier, and is used to compensate the loop. Internal
compensation is used to meet most applications. Connect COMP to AGND to select internal compensation. Connect a
compensation network between COMP and FB to use external compensation.
6
AGND
The AGND terminal provides the return path for the core analog control circuitry within the device. Connect AGND to the board
ground plane. AGND and PGND are connected internally within the device. Do not operate the device with AGND and PGND
connected to dissimilar voltages.
7, 8
PHASE
Phase switch output node. This is the main output of the device. Connect to the external output inductor.
9, 10
VIN
Voltage supply input. The main power input for the IC. Connect to a suitable voltage supply. Place a ceramic capacitor from VIN
to PGND, close to the IC for decoupling (typical 10µF).
11
VDD
Low dropout linear regulator decoupling pin. VDD is the internally generated 5V supply voltage and is derived from VIN. The
VDD is used to power all the internal core analog control blocks and drivers. Connect a 1µF capacitor from VDD to the board
ground plane. If VIN is between 4.5V to 5.5V, then connect VDD directly to VIN to improve efficiency.
12
BOOT
Bootstrap input. Floating bootstrap supply pin for the upper power MOSFET gate driver. Connect a 0.1µF capacitor between
BOOT and PHASE.
13
(EPAD)
PGND
Power ground terminal. Provides thermal relief for the package and is connected to the source of the low-side output MOSFET.
Connect PGND to the board ground plane using as many vias as possible. AGND and PGND are connected internally within the
device. Do not operate the device with AGND and PGND connected to dissimilar voltages.
DESCRIPTION
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January 15, 2016
ISL85003, ISL85003A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
OPTION
FREQUENCY
(kHz)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL85003FRZ
003F
-40 to +125
SYNC
500
12 Ld DFN
L12.3x4
ISL85003AFRZ
003A
-40 to +125
Soft-Start
500
12 Ld DFN
L12.3x4
ISL85003EVAL2Z
Evaluation Board
ISL85003AEVAL2Z
Evaluation Board
ISL85003DEMO1Z
Demo Evaluation Board
ISL85003ADEMO1Z
Demo Evaluation Board
NOTES:
1. Add “-T” suffix for 6k unit, “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel
specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL85003, ISL85003A. For more information on MSL, please see tech
brief TB363.
4. The ISL85003 is provided with a frequency synchronization input. The ISL85003A is a version of the part with programmable soft-start.
TABLE 1. COMPONENTS SELECTION (Refer to Figures 1A and 1B)
VOUT
0.8V
1V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
C5, C6
10µF
10µF
10µF
10µF
10µF
10µF
10µF
10µF
C8
22µF
22µF
22µF
47µF
47µF
47µF
47µF
47µF
C9
22µF
22µF
22µF
22µF
22µF
22µF
22µF
22µF
C1
Open
Open
Open
4.7pF
4.7pF
4.7pF
4.7pF
4.7pF
L1
1.8µH
2.2µH
2.2µH
3.3µH
3.3µH
3.3µH
4.7µH
4.7µH
R1
301kΩ
301kΩ
301kΩ
301kΩ
301kΩ
301kΩ
301kΩ
301kΩ
R2
Open
1.2MΩ
604kΩ
344kΩ
241kΩ
142kΩ
96.3kΩ
57.1kΩ
NOTE: VIN = 12V, IOUT = 3A; The components selection table is a suggestion for typical application using internal compensation mode. For application
that required high output capacitance greater than 200µF, R1 should be adjusted to maintain loop response bandwidth about 40kHz. See “Loop
Compensation Design” on page 19 for more detail.
TABLE 2. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
INTERNAL/EXTERNAL
COMPENSATION
EXTERNAL FREQUENCY
SYNC
PROGRAMMABLE
SOFT-START
SWITCHING FREQUENCY
ISL85003
Yes
Yes
No
300kHz to 2MHz
ISL85003A
Yes
No
Yes
500kHz
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January 15, 2016
ISL85003, ISL85003A
Absolute Maximum Ratings
Thermal Information
VIN, EN to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +24V (DC)
PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -2V to +24V (40ns)
FB to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
VDD, COMP, SYNC, PG to AGND and PGND . . . . . . . . . . . . . . . -0.3V to +7V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . .-55°C to +150°C
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 150V
Charged Device Model (Tested per JESD22-A115-A). . . . . . . . . . . . . 1kV
Thermal Resistance
JA (°C/W) JC (°C/W)
DFN Package (Notes 5, 6) . . . . . . . . . . . . . .
49
5
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All parameter limits are established over the Recommended Operating Conditions with TJ = -40°C to +125°C,
and with VIN = 12V unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating junction temperature range,
-40°C to +125°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
MAX
(Note 7)
UNIT
18
V
3.2
4.5
mA
TYP
SUPPLY VOLTAGE
VIN Voltage Range
VIN
VIN Quiescent Supply Current
IQ
SYNC = Low, EN > 1V, FB = 0.85V, not
switching
VIN Shutdown Supply Current
ISD
EN = AGND
6
11
µA
Rising Edge
4.20
4.35
V
4.5
UNDERVOLTAGE LOCKOUT
VIN UVLO Threshold
Falling Edge
3.6
3.8
VIN = 6V to 18V, IVDD = 0mA to 30mA
4.3
5.00
V
INTERNAL VDD LDO
VDD Output Voltage
VDD Output Current Limit
5.50
50
V
mA
OSCILLATOR
Nominal Switching Frequency
fSW
Minimum On-Time
tON
Minimum Off-Time
Synchronization Range
400
500
600
kHz
IOUT = 0mA (Note 8)
120
140
ns
tOFF
(Note 8)
140
180
ns
SYNC
ISL85003
300
2000
kHz
SYNC High-Time
tHI
ISL85003
100
ns
SYNC Low-Time
tLO
ISL85003
100
ns
SYNC Logic Input Low
ISL85003
0.50
SYNC Logic Input High
ISL85003
1.20
VIN = 4.5V to 18V
0.792
V
V
ERROR AMPLIFIER
FB Regulation Voltage
VFB
FB Leakage Current
VFB = 0.8V (Note 8)
Open Loop Bandwidth
BW
Gain
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0.8
0.808
V
0.3
10
nA
5.5
MHz
70
dB
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Electrical Specifications
All parameter limits are established over the Recommended Operating Conditions with TJ = -40°C to +125°C,
and with VIN = 12V unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating junction temperature range,
-40°C to +125°C. (Continued)
PARAMETER
SYMBOL
Output Drive
TEST CONDITIONS
MIN
(Note 7)
VCOMP = 1.5V
Current Sense Gain
RT
Slope Compensation
Se
fSW = 500kHz
TYP
MAX
(Note 7)
UNIT
±110
µA
0.2
Ω
550
mV/µs
ENABLE INPUT
Rising Edge
0.5
0.6
0.7
V
Hysteresis
60
100
140
mV
Default Soft-Start Time
ISL85003, ISL85003A with soft-start open
1
2.3
3.6
ms
SS Internal Soft-Start Charging Current
ISL85003A
2.5
3.5
4.5
µA
EN Input Threshold
SOFT-START FUNCTION
POWER GOOD OPEN DRAIN OUTPUT
Output Low Voltage
IPG = 5mA sinking
0.25
V
PG Pin Leakage Current
VPG = VDD
0.01
µA
PG Lower Threshold
Percentage of output regulation
80
85
90
%
PG Upper Threshold
Percentage of output regulation
110
115
120
%
PG Thresholds Hysteresis
Delay Time
3
%
Rising Edge
1.5
ms
Falling Edge
18
µs
FAULT PROTECTION
Positive Overcurrent Protection Threshold
IPOCP
Negative Overcurrent Protection Threshold
INOCP
Positive Overcurrent Protection Low-Side MOSFET
Current forced into PHASE node, high-side
MOSFET is off, SYNC = High
4.0
5.0
6.0
A
-3.2
-2.2
-1.1
A
Current in low-side MOSFET at end of low-side
cycle.
19
VIN Overvoltage Threshold
Hysteresis
6
A
20
V
1
V
TSD
Rising Threshold
165
°C
THYS
Hysteresis
10
°C
High-Side MOSFET rDS(ON)
RHDS
IPHASE = 100mA
65
110
mΩ
Low-Side MOSFET rDS(ON)
RLDS
IPHASE = 100mA
45
75
mΩ
EN = AGND
10
KΩ
ISL85003
150
mA
Thermal Shutdown Temperature
POWER MOSFET
PHASE Pull-Down Resistor
DIODE EMULATION
Zero Crossing Threshold
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Compliance to limits is assured by characterization and design.
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FN7968.2
January 15, 2016
ISL85003, ISL85003A
Typical Performance Curves
Typical values are at TA = +25°C.
Circuit of VIN = 12V, VOUT = 5V, IOUT = 3A, TJ = -40°C to +125°C unless otherwise noted.
90
90
80
3.3VOUT
70
EFFICIENCY (%)
100
EFFICIENCY (%)
100
2.5VOUT
1VOUT
1.8VOUT
60
80
1.5VOUT
1.8VOUT
1.2VOUT 2.5VOUT
70
3.3VOUT
1VOUT
60
1.5VOUT
50
50
1.2VOUT
40
0
0.1
1.0
40
10
0
0.3
0.6
0.9
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD, 5VIN DCM
3.3VOUT
3.0
90
5VOUT
70
1.2VOUT
1.5VOUT
60
1VOUT
EFFICIENCY (%)
EFFICIENCY (%)
2.7
100
90
1.8VOUT
50
40
2.4
FIGURE 4. EFFICIENCY vs LOAD, 5VIN CCM
100
80
1.2 1.5 1.8 2.1
OUTPUT LOAD (A)
1.8VOUT
70
60
0.1
1.0
OUTPUT LOAD (A)
40
10
1.2VOUT
3.3VOUT
1.5VOUT
2.5VOUT
1VOUT
50
2.5VOUT
0
80
5VOUT
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD, 12VIN DCM
FIGURE 6. EFFICIENCY vs LOAD, 12VIN CCM
100
100
1.8VOUT
90
2.5VOUT
3.3VOUT
80
70
EFFICIENCY (%)
EFFICIENCY (%)
90
1.5VOUT
5VOUT
60
80
1.8VOUT
40
50
1VOUT
0
0.1
1.0
OUTPUT LOAD (A)
FIGURE 7. EFFICIENCY vs LOAD, 18VIN DCM
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10
1.2VOUT
2.5VOUT
60
1.2VOUT
50
1.5VOUT 3.3VOUT
70
40
0
1VOUT
5VOUT
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
OUTPUT LOAD (A)
FIGURE 8. EFFICIENCY vs LOAD, 18VIN CCM
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Typical Performance Curves
Circuit of VIN = 12V, VOUT = 5V, IOUT = 3A, TJ = -40°C to +125°C unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
1.006
1.204
5 VIN DCM
5 VIN CCM
12 VIN DCM
12 VIN CCM
1.002
1.202
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.004
5 VIN DCM
5 VIN CCM
12 VIN DCM
12 VIN CCM
18VIN DCM
18 VIN CCM
1.000
0.998
0.996
1.200
1.198
1.196
1.194
0.994
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
1.192
3.0
0
0.3
0.6
0.9
OUTPUT LOAD (A)
1.500
1.496
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.1
2.4
2.7
3.0
5VIN DCM
5VIN CCM
12VIN DCM
12VIN CCM
18VIN DCM
18VIN CCM
1.798
1.494
1.492
1.796
1.794
1.792
1.790
1.490
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
1.788
3.0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
FIGURE 11. VOUT REGULATION vs LOAD, 1.5V
3.330
5VIN DCM
5VIN CCM
12VIN DCM
12VIN CCM
18VIN DCM
18 VIN CCM
3.0
5VIN DCM
5VIN CCM
3.328
OUTPUT VOLTAGE (V)
2.482
2.7
FIGURE 12. VOUT REGULATION vs LOAD, 1.8V
2.486
2.484
2.4
OUTPUT LOAD (A)
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
1.8
1.800
5VIN DCM
5VIN CCM
12VIN DCM
12VIN CCM
18VIN DCM
18VIN CCM
1.498
2.480
2.478
12VIN DCM
12VIN CCM
18VIN DCM
18VIN CCM
3.326
3.324
3.322
3.320
2.476
2.474
1.5
FIGURE 10. VOUT REGULATION vs LOAD, 1.2V
FIGURE 9. VOUT REGULATION vs LOAD, 1V
1.488
1.2
OUTPUT LOAD (A)
0
0.3
0.6
0.9
1.2 1.5 1.8 2.1
OUTPUT LOAD (A)
2.4
FIGURE 13. VOUT REGULATION vs LOAD, 2.5V
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2.7
3.0
3.318
0.0
0.3
0.6
0.9
1.2 1.5 1.8 2.1
OUTPUT LOAD (A)
2.4
2.7
3.0
FIGURE 14. VOUT REGULATION vs LOAD, 3.3V
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Typical Performance Curves
Circuit of VIN = 12V, VOUT = 5V, IOUT = 3A, TJ = -40°C to +125°C unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
4.989
7VIN DCM
7VIN CCM
OUTPUT VOLTAGE (V)
4.986
PHASE 10V/DIV
12VIN DCM
12VIN CCM
18VIN DCM
18VIN CCM
4.983
4.980
VOUT 5V/DIV
4.977
VEN 10V/DIV
4.974
4.971
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
PG 5V/DIV
OUTPUT LOAD (A)
1ms/DIV
FIGURE 15. VOUT REGULATION vs LOAD 5V
FIGURE 16. START-UP VEN AT NO LOAD (DCM)
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 5V/DIV
VOUT 5V/DIV
VEN 10V/DIV
VEN 10V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
50ms/DIV
FIGURE 17. START-UP VEN AT NO LOAD (CCM)
FIGURE 18. SHUTDOWN VEN AT NO LOAD (DCM)
PHASE 10V/DIV
PHASE 10V/DIV
VOUT 5V/DIV
VOUT 5V/DIV
VEN 10V/DIV
VEN 10V/DIV
PG 5V/DIV
PG 5V/DIV
50ms/DIV
FIGURE 19. SHUTDOWN VEN AT NO LOAD (CCM)
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1ms/DIV
FIGURE 20. START-UP VEN AT 3A LOAD
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Typical Performance Curves
Typical values are at TA = +25°C. (Continued)
Circuit of VIN = 12V, VOUT = 5V, IOUT = 3A, TJ = -40°C to +125°C unless otherwise noted.
PHASE 10V/DIV
VOUT 5V/DIV
VIN 10V/DIV
VOUT 5V/DIV
IL 2A/DIV
VEN 10V/DIV
PG 5V/DIV
PG 5V/DIV
50ms/DIV
1ms/DIV
FIGURE 21. SHUTDOWN VEN AT 3A LOAD
FIGURE 22. START-UP VIN AT NO LOAD (CCM)
VIN 10V/DIV
VOUT 5V/DIV
VIN 10V/DIV
VOUT 5V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
100ms/DIV
1ms/DIV
FIGURE 23. SHUTDOWN VIN AT NO LOAD (CCM)
FIGURE 24. START-UP VIN AT NO LOAD (DCM)
VIN 10V/DIV
VOUT 5V/DIV
VIN 10V/DIV
VOUT 5V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
100ms/DIV
1ms/DIV
FIGURE 25. SHUTDOWN VIN AT NO LOAD (DCM)
FIGURE 26. STAR-TUP VIN AT 3A LOAD
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FN7968.2
January 15, 2016
ISL85003, ISL85003A
Typical Performance Curves
Typical values are at TA = +25°C. (Continued)
Circuit of VIN = 12V, VOUT = 5V, IOUT = 3A, TJ = -40°C to +125°C unless otherwise noted.
VIN 10V/DIV
PHASE 5V/DIV
VOUT 5V/DIV
IL 2A/DIV
PG 5V/DIV
1ms/DIV
20ns/DIV
FIGURE 27. SHUTDOWN VIN AT 3A LOAD
FIGURE 28. JITTER AT NO LOAD (CCM )
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 10mV/DIV
IL 2A/DIV
20ns/DIV
500ns/DIV
FIGURE 29. JITTER AT FULL LOAD 3A (CCM)
FIGURE 30. STEADY STATE AT NO LOAD CCM
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 10mV/DIV
VOUT 20mV/DIV
IL 0.2A/DIV
IL 2A/DIV
50µs/DIV
500ns/DIV
FIGURE 31. STEADY STATE AT NO LOAD DCM
FIGURE 32. STEADY STATE AT 3A LOAD DCM
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FN7968.2
January 15, 2016
ISL85003, ISL85003A
Typical Performance Curves
Typical values are at TA = +25°C. (Continued)
Circuit of VIN = 12V, VOUT = 5V, IOUT = 3A, TJ = -40°C to +125°C unless otherwise noted.
IL 2A/DIV
IL 2A/DIV
VOUT RIPPLE 100mV/DIV
VOUT RIPPLE 50mV/DIV
100µs/DIV
100µs/DIV
FIGURE 33. LOAD TRANSIENT (CCM)
FIGURE 34. LOAD TRANSIENT (DCM)
PHASE 10V/DIV
VOUT 5V/DIV
VOUT 2V/DIV
IL 2A/DIV
IOUT 2A/DIV
PG 5V/DIV
PG 5V/DIV
100µs/DIV
1ms/DIV
FIGURE 35. OUTPUT SHORT-CIRCUIT
FIGURE 36. OVERCURRENT PROTECTION
PHASE 10V/DIV
PHASE 10V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
IL 1A/DIV
5µs/DIV
10µs/DIV
FIGURE 37. DCM TO CCM TRANSITION
FIGURE 38. CCM TO DCM TRANSITION
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FN7968.2
January 15, 2016
ISL85003, ISL85003A
Typical Performance Curves
Typical values are at TA = +25°C. (Continued)
PHASE 10V/DIV
Circuit of VIN = 12V, VOUT = 5V, IOUT = 3A, TJ = -40°C to +125°C unless otherwise noted.
VOUT 2V/DIV
+165°C
VOUT 2V/DIV
IL 2A/DIV
PG 2V/DIV
PG 5V/DIV
1µs/DIV
20ms/DIV
FIGURE 39. 0VERVOLTAGE PROTECTION
FIGURE 40. OVER-TEMPERATURE PROTECTION
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FN7968.2
January 15, 2016
ISL85003, ISL85003A
Detailed Description
The ISL85003 and ISL85003A combine a synchronous buck
controller with a pair of integrated switching MOSFETs. The buck
controller drives the internal high-side and low-side N-channel
MOSFETs to deliver load currents up to 3A. The buck regulator
can operate from an unregulated DC source, such as a battery,
with a voltage ranging from +4.5V to +18V. An internal 5V LDO
voltage regulator is used to bias the controller. The converter
output voltage is programmed using an external resistor divider
and will generate regulated voltages down to 0.8V. These
features make the regulator suited for a wide range of
applications.
The controller uses a current mode loop, which simplifies the
loop compensation and permits fixed frequency operation over a
wide range of input and output voltages. The internal feedback
loop compensation option allows for simple circuit design. The
regulator switches at a default of 500kHz or it can be
synchronized from 300kHz to 2MHz on an ISL85003.
The buck regulator is equipped with a lossless current limit
scheme. The current in the output stage is derived from
temperature compensated measurements of the drain-to-source
voltage of the internal power MOSFETs. The current limit
threshold is internally set at 5A.
Operation Initialization
Pull EN high to start operation. The power-on reset circuitry will
prevent operation if the input voltage is below 4.2V. Once the
power-on reset requirement is met, the controller will soft-start
with a 2ms ramp on an ISL85003 or at a rate determined by the
value of a capacitor connected between SS and AGND on an
ISL85003A.
CCM Control Scheme
The regulator employs a current-mode pulse-width modulation
control scheme for fast transient response and pulse-by-pulse
current limiting. The current loop consists of the oscillator, the
PWM comparator, current sensing circuit, and a slope
compensation circuit. The gain of the current sensing circuit is
typically 200mV/A and the slope compensation is 1.1V/T. The
reference for the current loop is in turn provided by the output of
an Error Amplifier (EA), which compares the feedback signal at
the FB pin to the integrated 0.8V reference. Thus, the output
voltage is regulated by using the error amplifier to control the
reference for the current loop.
PWM operation is initialized by the clock from the oscillator. The
upper MOSFET is turned on at the beginning of a cycle and the
current in the MOSFET starts to ramp up. When the sum of the
current amplifier CSA signal and the slope compensation reaches
the control reference of the current loop, the PWM comparator
sends a signal to the logic to turn off the upper MOSFET and turn
on the lower MOSFET. The lower MOSFET stays on until the end of
the cycle. Figure 41 shows the typical operating waveforms during
Continuous Conduction Mode (CCM) operation. The dotted lines
illustrate the sum of the compensation ramp and the
current-sense amplifier’s output.
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 41. CCM OPERATION WAVEFORMS
Light-Load Operation
The ISL85003 monitors both the current in the low-side MOSFET
and the voltage of the FB node for regulation. Pulling the SYNC
pin low allows the ISL85003 to enter discontinuous operation
when lightly loaded by operating the low-side MOSFET in Diode
Emulation Mode (DEM). In this mode, reverse current is not
allowed in the inductor, and the output falls naturally to the
regulation voltage before the high-side MOSFET is switched for
the next cycle. Figure 42 shows the transition from CCM to DCM
operation. In CCM mode, the boundary is set by Equation 1:
V OUT  1 – D 
I OUT = ----------------------------------2Lf SW
(EQ. 1)
Where D = duty cycle, fSW = switching frequency, L = inductor
value, IOUT = output loading current, VOUT = output voltage.
The error amplifier is an operational amplifier that converts the
voltage error signal to a voltage output. The voltage loop is
internally compensated with the 30pF and 600kΩ RC network
that can support most applications.
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FN7968.2
January 15, 2016
ISL85003, ISL85003A
CCM
DCM
CLOCK
IL
LOAD CURRENT
0
VOUT
NOMINAL
FIGURE 42. DCM MODE OPERATION WAVEFORMS
The ISL85003 can be synchronized from 300kHz to 2MHz by an
external signal applied to the SYNC pin. The rising edge on the SYNC
triggers the rising edge of the PHASE pulse. Make sure that the
on-time of the SYNC pulse is greater than 100ns. Although the
maximum synchronized frequency can be as high as 2MHz, the
ISL85003 is a current mode regulator that requires a minimum
of 140ns on-time to regulate properly. As an example, the
maximum recommended synchronized frequency will be about
600kHz with 12VIN and 1VOUT.
Chip operation begins after VIN exceeds its rising POR trip point
(nominal 4.2V). If EN is held low externally, nothing happens until
this pin is released. Once the voltage on the EN pin is above 0.6V,
the LDO powers up and soft-start control begins. The default
soft-start time is 2ms.
On the ISL85003A, let SS float to select the internal soft-start
time with a default of 2ms. The soft-start time is extended by
connecting an external capacitor between SS and AGND. A 3.5µA
current source charges up the capacitor. The soft-start capacitor
is charged until the voltage on the SS pin reaches a 2.0V clamp
level. However, the output voltage reaches its regulation value
when the voltage on the SS pin reaches approximately 0.9V. The
capacitor, along with an internal 3.5µA current source, sets the
soft-start interval of the converter, tSS, according to Equation 2:
(EQ. 2)
Output Voltage Selection
The regulator output voltage is programmed using an external
resistor divider that scales the feedback relative to the internal
reference voltage. The scaled voltage is fed back to the inverting
input of the error amplifier; refer to Figure 43.
The output voltage programming resistor, R2, will depend on the
value chosen for the feedback resistor, R1, and the desired
regulator output voltage, VOUT; (see Equation 3). The R1 value will
determine the gain of the feedback loop. (See “Loop
Compensation Design” on page 19) for more details. The value
for the feedback resistor is typically between 10kΩ and 400kΩ.
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16
(EQ. 3)
If the output voltage desired is 0.8V, then R2 is left unpopulated.
R1 is still required to set the low frequency pole of the modulator
compensation.
VOUT
R1
EA
Enable, Soft-Start and Disable
C SS  nF  = 4.1  t SS  mS  – 1.6nF
R 1  0.8V
R 2 = ---------------------------------V OUT – 0.8V
+
-
Synchronization Control
R2
0.8V
REFERENCE
FIGURE 43. EXTERNAL RESISTOR DIVIDER
Protection Features
The regulator limits current in all on-chip power devices.
Overcurrent limits are applied to the two output switching
MOSFETs as well as to the LDO linear regulator that feeds VDD.
Input and output overvoltage protection circuitry on the switching
regulator provides a second layer of protection.
Switching Regulator Overcurrent Protection
Current flowing through the internal high-side switching MOSFET
is monitored during the on-time. The current is compared to a
nominal 5A overcurrent limit. If the measured current exceeds
the overcurrent limit reference level, the high-side MOSFET is
immediately turned off and will not turn on again until the next
switching cycle. Current through the low-side switching MOSFET
is sampled during off time. If the low-side MOSFET current
exceeds 6A at the end of the low-side cycle, then the high-side
MOSFET will skip the next cycle, allowing the inductor current to
decay to a safe level before resuming switching.
Once an output overload condition is removed, the output voltage
will rise into regulation at the internal SS rate.
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Negative Current Protection
T
Output Overvoltage Protection
Input Overvoltage Protection
The input overvoltage protection system prevents operation of the
switching regulator whenever the input voltage is higher than 20V.
The high-side and low-side MOSFETs are tri-stated and the
converter will restart under internal SS control when the input
voltage returns to normal.
Thermal Overload Protection
Thermal overload protection limits the maximum die
temperature, thus the total power dissipation in the regulator. A
sensor on the chip monitors the junction temperature. A signal is
sent to the fault monitor circuits whenever the junction
temperature (TJ) exceeds +165°C and this causes the switching
regulator and LDO to shut down.
The switching regulator turns on again and soft-starts after the
IC’s junction temperature cool by 10°C. The switching regulator
exhibits hiccup mode operation during continuous thermal
overload conditions. For continuous operation, do not exceed the
+125°C junction temperature rating.
Power Derating Characteristics
(EQ. 4)
Where PD is the power dissipated by the regulator and θJA is the
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by
Equation 5:
(EQ. 5)
Where TA is the ambient temperature. For the DFN package, the
θJA is 49 (°C/W).
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C when considering
the thermal design.
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17
2.0
2.5V
1.5
5V
1.0
0
50
VIN = 12V, ZERO LFM
60
70
80
90
100
TEMPERATURE (°C)
110
120
130
FIGURE 44. DERATING CURVE vs TEMPERATURE
Application Guidelines
BOOT Undervoltage Detection
The internal driver of the high-side FET is equipped with a BOOT
Undervoltage (UV) detection circuit. In the event the voltage
difference between BOOT and PHASE falls below 2.5V, the UV
detection circuit allows the low-side MOSFET on for 300ns, to
recharge the bootstrap capacitor.
While the ISL85003 includes an internal bootstrap diode,
efficiency can be improved by using an external supply voltage
and bootstrap Schottky diode. The external diode is then sourced
from a fixed external 5V supply or from the output of the
switching regulator if this is at 5V. The bootstrap diode can be a
low cost type, such as the BAT54.
PHASE
BOOT
C4
0.1µF
ISL85003
ISL85003A
BAT54
To prevent the regulator from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 4:
T J =  T A + T RISE 
3.3V
1.8V
0.5
The output overvoltage protection is triggered when the output
voltage exceeds 115% of the set voltage. In this condition,
high-side and low-side MOSFETs are tri-stated until the output
drops to within the regulation band. Once the output is in
regulation, the controller will restart under internal SS control.
T RISE =  PD    JA 
1V
2.5
OUTPUT CURRENT (V)
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side MOSFET, as
shown in “Functional Block Diagram” on page 3. When the
inductor current reaches -2.2A, the synchronous rectifier is turned
off. This limits the ability of the regulator to actively pull down on
the output and prevents large reverse currents that may fall
outside the range of the high-side current sense amp.
3.0
5VOUT or 5V SOURCE
FIGURE 45. EXTERNAL BOOTSTRAP DIODE
Switching Regulator Output Capacitor
Selection
An output capacitor is required to filter the inductor current and
supply the load transient current. The filtering requirements are a
function of the switching frequency, the ripple current and the
required output ripple. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the transient
load current. These requirements are generally met with a mix of
capacitor types and careful layout.
High frequency ceramic capacitors initially supply the transient and
slow the current load rate seen by the bulk capacitors. The bulk filter
capacitor values are generally determined by the (Equivalent Series
Resistance) ESR and voltage rating requirements rather than actual
capacitance requirements.
FN7968.2
January 15, 2016
ISL85003, ISL85003A
DVHUMP
VOUT
(EQ. 6)
dI tran
V ESL = ESL  --------------dt
(EQ. 7)
2
L out  I tran
V SAG = -------------------------------------------------C out   V in – V out 
DVESR
DVSAG
(EQ. 8)
2
L out  I tran
V HUMP = -------------------------------C out  V out
DVESL
(EQ. 9)
Where: Itran = Output Load Current Transient and Cout = Total
Output Capacitance.
IOUT
Itran
FIGURE 46. TYPICAL TRANSIENT RESPONSE
The high frequency decoupling capacitors should be placed as close
to the power pins of the load as physically possible. Be careful not to
add inductance in the circuit board wiring that could cancel the
usefulness of these low inductance components. Consult with the
manufacturer of the load on specific decoupling requirements.
The shape of the output voltage waveform during a load transient
that represents the worst case loading conditions will ultimately
determine the number of output capacitors and their type. When
this load transient is applied to the converter, most of the energy
required by the load is initially delivered from the output capacitors.
This is due to the finite amount of time required for the inductor
current to slew up to the level of the output current required by the
load. This phenomenon results in a temporary dip in the output
voltage. At the very edge of the transient, the Equivalent Series
Inductance (ESL) of each capacitor induces a spike that adds on top
of the existing voltage drop due to the ESR.
After the initial spike, attributable to the ESR and ESL of the
capacitors, the output voltage experiences sag. This sag is a direct
consequence of the amount of capacitance on the output.
During the removal of the same output load, the energy stored in the
inductor is dumped into the output capacitors. This energy dumping
creates a temporary hump in the output voltage. This hump, as with
the sag, can be attributed to the total amount of capacitance on the
output. Figure 46 shows a typical response to a load transient.
The amplitudes of the different types of voltage excursions can
be approximated using Equations 6, 7, 8 and 9.
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V ESR = ESR  I tran
18
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the ESL are
typically the major contributing factors in determining the output
capacitance. The number of output capacitors can be
determined by using Equation 10, which relates the ESR and ESL
of the capacitors to the transient load step and the voltage limit
(Vo):
ESL  I tran
----------------------------- + ESR  I tran
dt
Number of Caps = -------------------------------------------------------------------V o
(EQ. 10)
If VSAG or VHUMP are found to be too large for the output
voltage limits, then the amount of capacitance may need to be
increased. In this situation, a trade-off between output
inductance and output capacitance may be necessary.
The ESL of the capacitors, which is an important parameter in
the above equations, is not usually listed in specification.
Practically, it can be approximated using Equation 11 if an
Impedance vs Frequency curve is given for a specific capacitor:
1
ESL = ---------------------------------------2
C  2    f res 
(EQ. 11)
Where: fres is the resonant frequency where the lowest
impedance is achieved.
The ESL of the capacitors becomes a concern when designing
circuits that supply power to loads with high rates of change in
the current.
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. The inductor value determines the converter’s
ripple current and the output ripple voltage is a function of the
ripple current. The ripple voltage and current are approximated
by Equations 12 and 13:
 V IN – V OUT  V OUT
I = ------------------------------------  ---------------V IN
Fs  L
(EQ. 12)
VOUT = I x ESR
(EQ. 13)
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Increasing the value of inductance reduces the ripple current and
voltage. However, the large inductance values reduce the
converter’s response time to a load transient. Furthermore, the
ripple current is an important signed in current mode control.
Therefore, set the ripple inductor current to approximately 30%
of the maximum output current or about 1A for optimized
performance.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
regulator will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval, the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.
The response time to a transient is different for the application of
load and the removal of load. Equations 14 and 15 give the
approximate response time interval for application and removal
of a transient load:
tFALL =
L x ITRAN
(EQ. 14)
VIN - VOUT
L x ITRAN
Use a mix of input bypass capacitors to control the input voltage
ripple. Use ceramic capacitors for high frequency decoupling and
bulk capacitors to supply the current needed each time the
switching MOSFET turns on. Place the ceramic capacitors
physically close to the MOSFET VIN pins (switching MOSFET
drain) and PGND.
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and largest RMS current required by the
circuit. Their voltage rating should be at least 1.25x greater than
the maximum input voltage, while a voltage rating of 1.5x is a
conservative guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
more closely approximated through Equation 16:
 MAX 
V IN – V OUT V OUT 2
V OUT 
2
1
--------------  I OUT
+ ------   -----------------------------  -------------- 
V IN 
V IN  
12  L  f s
 MAX 
^
iin
+
Input Capacitor Selection
=
When COMP is not connected to GND, the COMP pin is active for
external loop compensation. In an application where extreme
temperature such as less than -10°C or greater than +85°C,
external compensation mode should be used. The regulator uses
constant frequency peak current mode control architecture to
achieve a fast loop transient response. An accurate current
sensing pilot device in parallel with the upper MOSFET is used for
peak current control signal and overcurrent protection. The
inductor is not considered as a state variable since its peak
current is constant, and the system becomes a single order
system. It is much easier to design a type II compensator to
stabilize the loop than to implement voltage mode control. Peak
current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 47 shows the
small signal model of the synchronous buck regulator.
(EQ. 15)
VOUT
Where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case response
time can be either at the application or removal of load. Be sure
to check both of these equations at the minimum and maximum
output levels for the worst case response time.
I RMS
Loop Compensation Design
^
iL
LP
+
vo^
RLP
VIN d^
ILd^ 1:D
^
VIN
RT
GAIN (VLOOP (S(fi))
tRISE =
For a through-hole design, several electrolytic capacitors may be
needed, especially at temperature less than -25°C. The
electrolytic's ESR can increase ten times higher than at room
temperature and cause input line oscillation. In this case, a more
thermally stable capacitor such as X7R ceramic should be used.
For surface mount designs, solid tantalum capacitors can be
used, but caution must be exercised with regard to the capacitor
surge current rating. Some capacitor series available from
reputable manufacturers are surge current tested.
Rc
Co
Ro
Ti (S)
d^
K
Fm
+
Tv(S)
He(S)
^
Vcomp
-Av(S)
FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
C7
Vo
R6
R1
C3
V FB
R2
V REF
C6
-
VCOMP
+
FIGURE 48. TYPE II COMPENSATOR
(EQ. 16)
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19
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Figure 48 shows the type II compensator and its transfer function
is expressed, as shown in Equation 17:
5V  60 F
C 6 = ------------------------------------------ = 65pF
10  3A  153k
S
S - 
 1 + -----------1 + -------------





v̂ comp
1
cz1
cz2
A v  S  = ----------------- = -------------------------------------- -------------------------------------------------------------- C6 + C7   R1 
S 
S 
v̂ o
S 1 + ------------- 1 + ------------
 cp1 
 cp2
1
1.5m  60F
C 7 = max [--------------------------------------, ----------------------------------------------------] = (0.06pF, 4.2pF)
10  153k   500kHz  153k
(EQ. 24)
(EQ. 17)
Where,
C6 + C7
1
1
 cz1 = --------------- ,  cz2 = ---------------  cp1 = -----------------------  cp2  350kHz
R6 C6 C7
R6 C6
R1 C3
Compensator Design Goal
High DC Gain
Choose Loop bandwidth fc of approximately 50kHz or 1/10 of
the switching frequency.
Gain margin: >10dB
Use the closest standard values for R6, C6 and C7. There is
approximately 3pF parasitic capacitance from VCOMP to GND;
therefore, C7 is optional. Use R6 = 150kΩ, C6 = 62pF, and
C7 = OPEN.
1
C 3 = --------------------------------------------- = 62pF
250kHz  51k
60
BANDWIDTH OF CLOSE LOOP
The compensator design procedure is as follows:
40
20
GAIN (db)
(EQ. 18)
R 6 = 2f c C o R t R 1  f c  C o R 1
(EQ. 25)
Use C3 = 68pF. Note that C3 may increase the loop bandwidth
from the previous estimated value. Figure 49 shows the
simulated voltage loop gain. It has a 42kHz loop bandwidth with
54°of phase margin and 17dB of gain margin. It may be more
desirable to achieve an increased phase margin. This can be
accomplished by lowering R6 or increasing C3 by 20% to 30%.
Phase margin: >40°
The loop gain at crossover frequency of fc has a unity gain.
Therefore, the compensator resistance R6 is determined by
Equation 18.
(EQ. 23)
0
-20
Note that Co is the actual capacitance seen by the regulator,
which may include ceramic high frequency decoupling and bulk
output capacitors. Ceramic may have to be derated by
approximately 40% depending on dielectric, voltage stress and
temperature. Compensator capacitor C6 is then given by
Equations 19 and 20.
Vo Co
Ro Co
C 6 = --------------- = ------------------10R 6 10I o R 6
(EQ. 19)
-40
-60
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+05
1.E+06
FREQUENCY (kHz)
120
PHASE MARGIN CLOSED LOOP
80
Rc Co 1
-,----------------]
C 7 = max [-------------10R 6 f s R 6
(EQ. 20)
An optional zero can boost the phase margin. CZ2 is a zero due
to R1 and C3
Put compensator zero, CZ2 from 1/2fc to fc.
1
C 3 = -------------------2f c R 2
(EQ. 21)
For internal compensation mode, R6 is equal 600kΩ and C6 is
30pF. Equation 18 can be rearranged to solve for R1.
Example: VIN = 12V, VO = 5V, IO = 3A, fSW = 500kHz, R1 = 51kΩ,
R2 = 9.7kΩ, Co = 2x47µF/3mΩ 6.3V ceramic (~60µF with
derating), L = 4.7µH, fc = 50kHz, then compensator resistance
R6:
R 6 = 50k  60F  51k = 153k
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20
PHASE (°)
40
0
-40
-80
-120
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
FREQUENCY (kHz)
FIGURE 49. SIMULATED LOOP GAIN
(EQ. 22)
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Layout Considerations
The layout is very important in high frequency switching
converter design. With power devices switching efficiently at
500kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage spikes
can degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
VIN
CIN
ISL85003
ISL85003A
A multi-layer printed circuit board is recommended. Figure 50
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage levels.
Keep the metal runs from the PHASE terminals to the output
inductor short. The power plane should support the input power
and output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring.
L
VOUT1
COUT1
PGND
COMP
C6
C7
R6
R1
FB
PGND PAD
LOAD
PHASE
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the internal body diode. Any parasitic inductance
in the switched current path generates a large voltage spike
during the switching interval. Careful component selection, tight
layout of the critical components and short, wide traces minimize
the magnitude of voltage spikes.
There are two sets of critical components in the regulator
switching converter. The switching components are the most
critical because they switch large amounts of energy and
therefore tend to generate large amounts of noise. Next are the
small signal components, which connect to sensitive nodes or
supply critical bypass current and signal coupling.
VIN
R2
C3
KEY
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
The critical small signal components include any bypass
capacitors, feedback components and compensation
components. Place the compensation components close to the
FB and COMP pins. The feedback resistors should be located as
close as possible to the FB pin with vias tied straight to the
ground plane.
In order to dissipate heat generated by the internal LDO and
MOSFETs, the ground pad should be connected to the internal
ground plane through at least five vias. This allows the heat to
move away from the IC and also ties the pad to the ground plane
through a low impedance path.
The switching components should be placed close to the
regulator first. Minimize the length of the connections between
the input capacitors, CIN, and the power switches by placing
them nearby. Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible.
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21
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
January 15, 2016
FN7968.2
Added the Related Literature section on page 1.
On page 4, updated VDD pin description by changing VIN range from “3V to 5.5V” to “4.5V to 5.5V”.
Updated Note 1 in the ordering information table to include all tape and reel options.
Added Table 2 on page 5.
Updated POD L12.3x4 to the latest revision the changes are as follows:
Tiebar Note 5 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
July 17, 2014
FN7968.1
Detailed Description on page 15 changed from 4.5A to 5A.
“Switching Regulator Overcurrent Protection” on page 16: Changed 4.5A to 5A.
Equation 12 on page 18, updated from “dI=/(Fs*L)*Vout/Vin” to “dI=(Vin-Vout)/(Fs*L)*Vout/Vin”
“Input Capacitor Selection” on page 19 : Change RESR to ESR
“Negative Current Protection” on page 17: Changed -2.5A to -2.2A.
Updated Package information from 4x3 to 3x4 on page 1, Pin Configuration on page 4, Ordering Information on
page 5, and replaced the “Package Outline Drawing” on page 23.
Updated the Ordering Information on page 5 to include the new Evaluation Boards that are now available.
March 21, 2014
FN7968.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
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22
FN7968.2
January 15, 2016
ISL85003, ISL85003A
Package Outline Drawing
L12.3x4
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/15
3.00
B
6
PIN 1
INDEX AREA
1
12
4.00
(4X)
6
PIN #1
INDEX AREA
SEE DETAIL "X"
A
3.30 ±0.10
0.10
2X 2.50
6
7
12X 0.25 ±0.05
0.10 M C A B
TOP VIEW
0.90 MAX
4
C
SIDE VIEW
1.70
±0.10
10X 0.50
12X 0.40 ± 0.05
BOTTOM VIEW
(12X 0.60)
( 12 X 0.25)
( 3.30 )
( 2.50)
0.10 C
(10x 0.50)
C
0 . 203 REF
SEATING PLANE
(1.70)
0.08 C
0 . 00 MIN.
0 . 05 MAX.
( 2.80 )
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
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23
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
Reference document JEDEC MO-229.
FN7968.2
January 15, 2016
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