s3921-128q etc kmpd1044e

IMAGE SENSOR
NMOS linear image sensor
S3921/S3924 series
Voltage output type with current-integration readout circuit and impedance conversion circuit
NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning
circuit is made up of N-channel MOS transistors, operates at low power consumption and is easy to handle. Each photodiode has a large active
area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output
linearity and wide dynamic range.
S3921/S3924 series have a current-integration readout circuit utilizing the video line and an impedance conversion circuit. The output is available
in boxcar waveform allowing signal readout with a simple external circuit.
The photodiodes of S3921 series have a height of 2.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S3924 series also
have a height of 2.5 mm but are arrayed at a spacing of 25 µm. The photodiodes are available in 3 different pixel quantities for each series, 128
(S3921-128Q), 256 (S3921-256Q, S3924-256Q) and 512 (S3921-512Q, S3924-512Q) and 1024 (S3924-1024Q). Quartz glass is the standard
window material.
Features
Applications
Built-in current-integration readout circuit utilizing
Multichannel spectrophotometry
video line capacitance and impedance conversion
Image readout system
circuit (boxcar waveform output)
Wide active area
Pixel pitch: 50 µm (S3921 series)
25 µm (S3924 series)
Pixel height: 2.5 mm
High UV sensitivity with good stability
Low dark current and high saturation charge allow a long
integration time and a wide dynamic range at room temperature
Excellent output linearity and sensitivity spatial uniformity
Low voltage, single power supply operation
Start pulse, clock pulse and video line reset pulse are
CMOS logic compatible
■ Equivalent circuit
1
Clock
2
Digital shift register
(MOS shift register)
End of scan
Source follower circuit
Vdd
Address
switch
Active
photodiode
2.5 mm
st
Active video
Vss
Saturation
control gate
Saturation
control drain
Address
switch
Dummy diode
b
a
Dummy video
Oxidation silicon
1.0 µm
Start
Clock
■ Active area structure
N type silicon
Reset V
KMPDC0019EA
Parameter
Supply voltage
Input pulse (φ1, φ2, φst) voltage
Power consumption* 1
Operating temperature* 2
Storage temperature
*1: Vdd=5 V, Vr=2.5 V
*2: No condensation
P type silicon
S3921 series: a=50 µm, b=45 µm
S3924 series: a=25 µm, b=20 µm
■ Absolute maximum ratings
Symbol
Vdd
Vφ
P
Topr
Tstg
1.0 µm
Reset
400 µm
Reset switch
Value
15
15
10
-40 to +65
-40 to +85
KMPDA0067EA
Unit
V
V
mW
°C
°C
1
NMOS linear image sensor
S3921/S3924 series
I Shape specifications
S3921S3921S3921128Q
256Q
512Q
Number of pixels
128
256
512
Package length
31.75
40.6
Number of pin
22
Window material*3
Quartz
Weight
3.0
3.5
*3: Fiber optic plate is available (excluding the S3921-128Q, S3924-256Q).
S3924S3924256Q
512Q
256
512
31.75
22
Quartz
3.0
Parameter
S39241024Q
1024
40.6
3.5
Unit
mm
g
■ Specifications (Ta=25 °C )
Parameter
Symbol
Pixel pitch
Pixel height
Spectral response range (10% of peak)
Peak sensitivity wavelength
Photodiode dark current*4
Photodiode capacitance*4
Saturation exposure*4 *5
Saturation charge*4
λ
λp
ID
Cph
Esat
Qsat
Saturation output voltage*4
Vsat
Min.
-
Photo response non-uniformity*6
PRNU
*4: Reset V=2.5 V, Vdd=5.0 V, Vφ=5.0 V
*5: 2856 K, tungsten lamp
*6: 50% of saturation, excluding the start pixel and last pixel
S3921 series
Typ.
50
2.5
200 to 1000
600
0.2
20
220
50
1350 (-128Q)
1300 (-256Q)
1100 (-512Q)
-
Max.
-
Min.
-
0.6
±3
-
S3924 series
Typ.
25
2.5
200 to 1000
600
0.1
10
220
25
1050 (-256Q)
820 (-512Q)
570 (-1024Q)
-
Max.
0.3
±3
Unit
μm
mm
nm
nm
pA
pF
mlx· s
pC
mV
mV
mV
%
I Electrical characteristics (Ta=25 °C)
Parameter
Symbol
Clock pulse (φ1, φ2)
voltage
High Vφ1, Vφ2 (H)
Low Vφ1, Vφ2 (L)
High
Vφs (H)
Start pulse (φst) voltage*7
Low
Vφs (L)
High
Vrφ (H)
Reset pulse (Reset φ)
Voltage*7
Low
Vrφ (L)
Source follower circuit drain voltage*7
Vdd
Reset voltage (Reset V)*8
Vr
Saturation control gate voltage
Vscg
Saturation control drain voltage*8
Vscd
trφ1, trφ2
Clock pulse (φ1, φ2) rise / fall time
tfφ1, tfφ2
Clock pulse (φ1, φ2) pulse width
tpwφ1, tpwφ2
Start pulse (φst) rise / fall time
trφs, tfφs
Start pulse (φst) pulse width
tpwφs
Reset pulse rise / fall time
trrφ, tfrφ
Start pulse (φst) and clock pulse
tφov
(φ2) overlap
Clock pulse (φ2) and reset
tφovr
pulse (Reset φ) overlap
Clock pulse (φ2) and reset
tdφr-2
pulse (Reset φ) delay time
9
Clock pulse (φ1, φ2) space*
X1, X 2
Clock pulse (φ2, Reset φ) space*9
tsφr-2
Data rate*10
f
S3921 series
Typ.
Max.
5
10
0.4
10
Vφ
0.4
10
Vφ
0.4
10
Vφ
Vφ - 2.5 Vφ - 2.0
0
Vr
-
Unit
-
-
20
-
-
20
-
ns
-
200
200
-
20
20
-
200
200
-
20
20
-
ns
ns
ns
ns
-
200
-
-
200
-
-
ns
-
660
-
-
660
-
-
ns
-
50
-
-
50
-
-
ns
500
-
trf - 20
0
0.1
-
100 (-256 Q)
150 (-512 Q)
200 (-1024 Q)
27 (-256 Q)
50 (-512 Q)
100 (-1024 Q)
500
-
ns
ns
kHz
ns
ns
ns
pF
pF
pF
-
trf - 20
0
0.1
100 (-128 Q)
150 (-256 Q)
200 (-512 Q)
21 (-128 Q)
36 (-256 Q)
67 (-512 Q)
-
Min.
4.5
0
4.5
0
4.5
0
4.5
2.0
-
S3924 series
Typ.
Max.
5
10
0.4
10
Vφ
0.4
10
Vφ
0.4
10
Vφ
Vφ - 2.5 Vφ - 2.0
0
Vr
-
Min.
4.5
0
4.5
0
4.5
0
4.5
2.0
-
V
V
V
V
V
V
V
V
V
V
Video delay time
tvd
50% of
saturation*10
Clock pulse (φ1, φ2)
line capacitance
Cφ
5 V bias
Reset pulse (Reset φ)
line capacitance
Cr
5 V bias
-
6
-
-
6
-
pF
Cscg
5 V bias
-
12 (-128 Q)
20 (-256 Q)
35 (-512 Q)
-
-
14 (-256 Q)
24 (-512 Q)
45 (-1024 Q)
-
pF
pF
pF
Vdd=5 V
200
200
Vr=2.5 V
*7: Vφ is input pulse voltage (refer to “IReset V voltage margin”)
*8: Terminal pin 7 is used for both Reset V and saturation control drain voltage
*9: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more
should be input if the clock pulse rise or fall time is longer than 20 ns. (refer to “ITiming chart for driver circuit”)
*10: Reset V=2.5 V, Vdd=5.0 V, Vφ=5.0 V
Ω
Saturation control gate (Vscg)
line capacitance
Output impedance
2
Condition
Zo
NMOS linear image sensor
S3921/S3924 series
■ Dimensional outlines (unit: mm)
S3921-128Q, S3924-256Q
S3921-256Q, S3924-512Q
Active area
12.8 × 2.5
Active area
6.4 × 2.5
6.4 ± 0.3
3.2 ± 0.3
1 ch
5.0 ± 0.5
1.3 ± 0.2*1
0.51 ± 0.05
2.54 ± 0.13
10.16 ± 0.25
1.4 ± 0.2*2
0.5 ± 0.05*3
3.0 ± 0.3
0.25
25.4 ± 0.13
Chip surface
Direction of scan
1.4 ± 0.2*2
1.3 ± 0.2*1
0.51 ± 0.05
5.0 ± 0.5
5.2 ± 0.2
Chip surface
3.0 ± 0.3
Direction of scan
31.75 ± 0.3
0.5 ± 0.05*3
31.75 ± 0.3
5.2 ± 0.2
10.4 ± 0.25
10.4 ± 0.25
1 ch
0.25
2.54 ± 0.13
25.4 ± 0.13
10.16 ± 0.25
*1: Distance from upper surface of quartz
window to chip surface
*2: Distance from chip surface
to bottom of package
*3: Window thickness
*1: Distance from upper surface of quartz
window to chip surface
*2: Distance from chip surface
to bottom of package
*3: Window thickness
KMPDA0060ED
KMPDA0061ED
■ Pin connection
S3921-512Q, S3924-1024Q
Active area
25.6 × 2.5
12.8 ± 0.3
2
1
22
NC
1
2
21
NC
st
3
20
NC
Vss
4
19
NC
Vscg
5
18
NC
6
17
NC
Reset V (Vscd)
7
16
NC
Vss
8
15
NC
Active video
9
14
NC
Dummy video
10
13
End of scan
Vsub
11
12
Vdd
5.2 ± 0.2
10.4 ± 0.25
1 ch
Reset
0.5 ± 0.05*3
3.0 ± 0.3
5.0 ± 0.5
0.51 ± 0.05
1.4 ± 0.2*2
Chip surface
Direction of scan
1.3 ± 0.2*1
40.6 ± 0.3
0.25
Vss, Vsub and NC should be grounded.
2.54 ± 0.13
25.4 ± 0.13
10.16 ± 0.25
KMPDC0025EA
*1: Distance from upper surface of quartz
window to chip surface
*2: Distance from chip surface
to bottom of package
*3: Window thickness
KMPDA0062ED
3
NMOS linear image sensor
Input or output
φ1, φ2
Input
(CMOS logic compatible)
φst
Input
(CMOS logic compatible)
Input
Input
(CMOS logic compatible)
Vss
Vscg
Reset φ
Reset V
Input
Vscd
Input
Active video
Output
Dummy video
Output
Vsub
-
Vdd
Input
Description
Pulses for operating the MOS shift register. The video data rate is equal
to the clock pulse frequency since the video output signal is obtained
synchronously with the rise of φ2 pulse.
Pulse for starting the MOS shift register operation. The time interval
between start pulses is equal to the signal accumulation time.
Connected to the anode of each photodiode. This should be grounded.
Used for restricting blooming. This should be grounded.
With Reset φ at high level, the video line is reset at the Reset V voltage.
The Reset V terminal connects to each photodiode cathode via the video
line when the address turns on. A positive voltage should be applied to
the Reset V terminal to use each photodiode at a reverse bias. Setting
the Reset V voltage to 2.5 V is recommended when the amplitude of φ1,
φ2 and Reset φ is 5 V. Terminal pin 7 is used for both Reset V and Vscd.
Used for restricting blooming. This should be biased at a voltage equal
to “Reset V”.
Low-impedance video output signal after internal current-voltage
conversion. Negative-going output including DC offset.
This has the same structure as the active video, but is not connected to
photodiodes, so only DC offset is output. Leave this terminal open when
not used.
Connected to the silicon substrate. This should be grounded.
Supply voltage to the internal impedance conversion circuit. A voltage
equal to the amplitude of each clock should be applied to this terminal.
This should be pulled up at 5 V by using a 10 kΩ resistor. This is a
negative going pulse that appears synchronously with the φ2 timing
right after the last photodiode is addressed.
Should be grounded.
Output
(CMOS logic compatible)
End of scan
NC
-
■ Spectral response (typical example)
■ Output voltage vs. exposure
(Ta=25 ˚C)
0.3
101
(Typ. Reset V=2.5 V, Vdd=5.0 V, V =5 V, light source: 2856 K)
0
Output voltage (V)
Photo sensitivity (A/W)
10
0.2
0.1
101
10
Saturation voltage
Output voltage (V)
Terminal
S3921/S3924 series
-1
10
S3921-128Q
S3921-256Q
-2
10
S3921-512Q
(Typ. Reset V=2.5 V, Vdd=5.0 V, V =5 V, light source: 2856 K)
0
Saturation voltage
10-1
S3924-256Q
10-2
S3924-512Q
S3924-1024Q
Saturation exposure
-3
10
0
200
-4
400
600
800
1000
1200
10
-5
10
-4
10
Wavelength (nm)
-3
10
-2
10
-1
10
0
10
Exposure (lx · s)
KMPDB0149EA
10
-3
10
-4
Saturation exposure
10-5
10-4
10-3
10-2
10-1
100
Exposure (lx · s)
KMPDB0118EA
KMPDB0119EA
■ Construction of image sensor
The NMOS image sensor consists of a scanning circuit made
up of MOS transistors, a photodiode array, and a switching
transistor array that addresses each photodiode, all integrated
onto a monolithic silicon chip. “■Equivalent circuit” shows
the circuit of a NMOS linear image sensor.
The MOS scanning circuit operates at low power consumption and generates a scanning pulse train by using a start
pulse and 2-phase clock pulses in order to turn on each address sequentially. Each address switch is comprised of an
NMOS transistor using the photodiode as the source, the
video line as the drain and the scanning pulse input section
as the gate.
4
The photodiode array operates in charge integration mode
so that the output is proportional to the amount of light exposure (light intensity × integration time).
Each cell consists of an active photodiode and a dummy
diode, which are respectively connected to the active video
line and the dummy video line via a switching transistor. Each
of the active photodiodes is also connected to the saturation
control drain via the saturation control gate, so that the photodiode blooming can be suppressed by grounding the saturation control gate. Applying a pulse signal to the saturation
control gate triggers all reset. (See “■Auxiliary functions”.)
NMOS linear image sensor
“■Active area structure” shows the schematic diagram of the
photodiode active area. This active area has a PN junction
consisting of an N-type diffusion layer formed on a P-type
silicon substrate.
A signal charge generated by light input accumulates as a
capacitive charge in this PN junction. The N-type diffusion
layer provides high UV sensitivity but low dark current.
■ Driver circuit
A start pulse φst and 2-phase clock pulses φ1, φ2 are needed
to drive the shift register. These start and clock pulses are
positive going pulses and CMOS logic compatible.
The 2-phase clock pulses φ1, φ2 can be either completely
separated or complementary. However, both pulses must not
be “High” at the same time.
A clock pulse space (X1 and X2 in “■Timing chart for driver
circuit”) of a “rise time/fall time - 20” ns or more should be
input if the rise and fall times of φ1, φ2 are longer than 20 ns.
The φ1 and φ2 clock pulses must be held at “High” at least
■ Timing chart for driver circuit
V
V
V
V
2
Reset
■ End of scan
The end of scan (EOS) signal appears in synchronization
with the φ2 timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
kΩ resistor.
■ Reset V voltage margin
12
tpw 1
1 (H)
1 (L)
2 (H)
2 (L)
tpw 2
10
Vr (H)
Vr (L)
Reset V voltage (V)
1
200 ns. Since the photodiode signal is obtained at the rise of
each φ2 pulse, the clock pulse frequency will equal the video
data rate.
The amplitude of start pulse φst is the same as the φ1 and φ2
pulses. The shift register starts the scanning at the “High”
level of φst, so the start pulse interval is equal to signal accumulation time. The φst pulse must be held “High” at least 200
ns and overlap with φ2 at least for 200 ns. To operate the shift
register correctly, φ2 must change from the “High” level to the
“Low” level only once during “High” level of φst. The timing
chart for each pulse is shown in “■Timing chart for driver
circuit”.
tpw s
V s (H)
V s (L)
st
S3921/S3924 series
tvd
Active video output
End of scan
tr s
st
tf s
tr 1
1
tf 2
X2
t ov
t ovr td r-2
ts r-2
e
ed
6
d
en
mm
res
x.
Ma
co
Re
4
0
2
Reset
v
tV
Reset V voltage range
2
tf 1
X1
ge
olta
8
Min.
4
5
6
7
8
9
10
Clock pulse amplitude (V)
KMPDB0047EA
tfr
trr
KMPDC0026EA
■ Signal readout circuit
S3921/S3924 series include a current integration circuit utilizing the video line capacitance and an impedance conversion circuit. This allows signal readout with a simple external
circuit. However, a positive bias must be applied to the video
line because the photodiode anode of NMOS linear image
sensors is at 0 V (Vss). This is done by adding an appropriate
pulse to the reset φ terminal. The amplitude of the reset pulse
should be equal to φ1, φ2 and φst.
When the reset pulse is at the high level, the video line is set
at the Reset V voltage. “■Reset V voltage margin” shows the
Reset V voltage margin. A higher clock pulse amplitude allows higher Reset V voltage and saturation charge. Conversely,
if the Reset V voltage is set at a low level with a higher clock
pulse amplitude, the rise and fall times of video output waveform can be shortened. Setting the Reset V voltage to 2.5 V is
recommended when the amplitude of φ1, φ2, φst and Reset φ
is 5 V.
To obtain a stable output, an overlap between the reset pulse
(Reset φ) and φ2 must be settled. (Reset φ must rise while φ2
is at the high level.) Furthermore, Reset φ must fall while φ2 is
at the low level.
S3921/S3924 series provide output signals with negativegoing boxcar waveform which include a DC offset of approximately 1 V when Reset V is 2.5 V. If you want to remove the DC
offset to obtain the positive-going output, the signal readout
circuit and pulse timing shown in “■Readout circuit example”
and “■Timing chart” are recommended. In this circuit, Rs must
be larger than 10 kΩ. Also, the gain is determined by the ratio
of Rf to Rs, so choose the Rf value that suits your application.
5
NMOS linear image sensor
■ Readout circuit example
S3921/S3924 series
■ Timing chart
+5 V
+5 V
+
10 kΩ
st
st
1
1
2
2
Reset
+2.5 V
Vdd
EOS
Active
video
Rf
EOS
Dummy
video
st
OPEN
1
Rs 10 kΩ
–
2
Reset
+
Reset V
(Vscd)
Vscg
+
Vss
Vsub
Reset
+15 V
NC
KMPDC0028EA
KMPDC0027EA
■ Anti-blooming function
If the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the saturation
charge cannot accumulate in the photodiode. This excessive charge flows out into the video line degrading the signal purity. To
avoid this problem and maintain the signal purity, applying the same voltage as the Reset V voltage to the saturation control drain
and grounding the saturation control gate are effective. If the incident light intensity is extremely high, a positive bias should be
applied to the saturation control gate. The larger the voltage applied to the saturation control gate, the higher the function for
suppressing the excessive saturation charge will be. However, this voltage also lowers the amount of saturation charge, so an
optimum bias voltage should be selected.
■ Auxiliary functions
1) All reset
In normal operation, the accumulated charge in each photodiode is reset when the signal is read out. Besides this method that
uses the readout line, S3921/S3924 series can reset the photodiode charge by applying a pulse to the saturation control gate.
The amplitude of this pulse should be equal to the φ1, φ2, φst, Reset φ pulses and the pulse width should be longer than 5 μs.
When the saturation control gate is set at the “High” level, all photodiodes are reset to the saturation control drain potential.
Conversely, when the saturation control gate is set at the “Low” level (0 V), the signal charge accumulates in each photodiode
without being reset.
2) Dummy video
S3921/S3924 series have a dummy video line. Positive-polarity video signals with the DC offset remove can be obtained by
differential amplification of the active video line and dummy video line outputs. When not needed, leave this unconnected.
■ Precautions for using NMOS linear image sensors
1) Electrostatic countermeasures
NMOS linear image sensors are designed to resist static electrical charges. However, take sufficient cautions and countermeasures to prevent damage from static charges when handling the sensors.
2) Window
If dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. Before using
the image sensor, the window surface should be cleaned. Wipe off the window surface with a soft cloth, cleaning paper or
cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. Do not
rub the window with dry cloth or cotton swab as this may generate static electricity.
6
NMOS linear image sensor
S3921/S3924 series
Information described in this material is current as of February, 2014.
Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the
information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always
contact us for the delivery specification sheet to check the latest specifications.
Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or
a suffix "(Z)" which means developmental specifications.
The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that
one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product
use.
Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
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Cat. No. KMPD1044E03
Feb. 2014 DN