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May 14, 2008
Micropower Single Supply Rail-to-Rail
Input-Output (RRIO) Precision Op Amp
The EL8178 is a precision low power, operational amplifier.
The device is optimized for single supply operation between
2.4V to 5.5V. This enables operation from one lithium cell or
two Ni-Cd batteries. The input range includes both positive
and negative rail.
For power sensitive applications, the EL8178 has and EN
pin that will shut the device down and reduce the supply
current to 3µA typ. In the active state, the EL8178 draws
minimal supply current (55µA) while meeting excellent
DC-accuracy, noise, and output drive specifications.
Ordering Information
PART
NUMBER
(Note 1)
EL8178FWZ-T7*
PART
MARKING
FN7504.7
Features
• Typical 55µA supply current
• 250µV max offset voltage
• Typical 1pA input bias current
• 266kHz gain-bandwidth product
• Single supply operation between 2.4V to 5.5V
• Rail-to-rail input and output
• Ground sensing
• Output sources and sinks 26mA load current
• Pb-free (RoHS compliant)
Applications
PACKAGE
(Pb-Free)
PKG.
DWG. #
BBWA
6 Ld SOT-23
MDP0038
EL8178FWZ-T7A* BBWA
6 Ld SOT-23
MDP0038
EL8178FSZ
8178FSZ
8 Ld SO
MDP0027
EL8178FSZ-T7*
8178FSZ
8 Ld SO
MDP0027
• Battery- or solar-powered systems
• 4mA to 20mA current loops
• Handheld consumer products
• Medical devices
• Thermocouple amplifiers
• Photodiode pre-amps
*Please refer to TB347 for details on reel specifications.
NOTE:
• pH probe amplifiers
1. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish,
which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
EL8178
(6 LD SOT-23)
TOP VIEW
OUT 1
V- 2
6 V+
+ -
IN+ 3
5 EN
4 IN-
EL8178
(8 LD SO)
TOP VIEW
NC 1
IN- 2
IN+ 3
V- 4
1
8 EN
+
7 V+
6 OUT
5 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
EL8178
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . 5.75V, 1V/µs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Current into IN+, IN-, and EN. . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
ESD Tolerance
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . .
230
8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
Ambient Operating Temperature Range . . . . . . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VOS
V+ = 5V, V- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25°C unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C.
DESCRIPTION
TEST CONDITIONS
Input Offset Voltage
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
-250
50
250
µV
450
µV
-450
ΔV OS
-----------------ΔTime
Long Term Input Offset Voltage
Stability
ΔV OS
---------------ΔT
Input Offset Drift vs Temperature
IB
Input Bias Current
-25
3
µV/Mo
1.1
µV/°C
1
-600
IOS
Input Offset Current
-30
10
-600
25
pA
600
pA
30
pA
600
pA
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz
2.8
µVP-P
Input Noise Voltage Density
fO = 1kHz
48
nV/√Hz
iN
Input Noise Current Density
fO = 1kHz
0.15
pA/√Hz
CMIR
Input Voltage Range
Guaranteed by CMRR test
0
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
80
eN
5
100
75
PSRR
Power Supply Rejection Ratio
VS = 2.4V to 5.5V
80
Large Signal Voltage Gain
2
VO = 0.5V to 4.5V,
RL = 100kΩ to (V+ + V-)/2
100
100
dB
dB
100
80
AVOL
V
dB
dB
400
V/mV
VmV
FN7504.7
May 14, 2008
EL8178
Electrical Specifications
PARAMETER
VOUT
V+ = 5V, V- = 0V, VCM = 2.5V, VO = 2.5V, TA = +25°C unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C. (Continued)
DESCRIPTION
Maximum Output Voltage Swing
SOT-23/SO-8
TEST CONDITIONS
MIN
(Note 3)
VOL; Output low,
RL = 100kΩ to (V+ + V-)/2
VOL; Output low,
RL = 1kΩ to (V+ + V-)/2
SR
TYP
MAX
(Note 3)
UNIT
3
10
mV
130
250
mV
350
mV
VOH; Output high,
RL = 100kΩ to (V+ + V-)/2
4.994
4.9975
V
VOH; Output high,
RL = 1kΩ to (V+ + V-)/2
4.750
4.875
V
Slew Rate
4.7
0.10
V
0.15
0.07
GBWP
Gain Bandwidth Product
fO = 100kHz
IS(ON)
Supply Current, Enabled
SOT-23/SO-8
Supply Current, Disabled
ISC+
Short Circuit Output Sourcing Current RL = 10Ω to opposite supply
V/µs
0.25
V/µs
266
35
55
30
IS(OFF)
0.19
3
23
kHz
75
µA
85
µA
5
µA
31
mA
18
ISC-
Short Circuit Output Sinking Current
RL = 10Ω to opposite supply
20
mA
26
mA
15
VS
Supply Voltage
Guaranteed by PSRR
mA
2.4
5.5
V
2.4
5.5
V
VINH
EN Pin High Level
2
VINL
EN Pin Low Level
IENH
EN Pin Input Current
VEN = 5V
0.25
IENL
EN Pin Input Current
VEN = 0V
-0.5
V
0.8
0.8
V
2.5
µA
+0.5
µA
NOTE:
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
3
FN7504.7
May 14, 2008
EL8178
Typical Performance Curves VS = ±2.5V, TA = +25°C, Unless Otherwise Specified
1
80
RL ≥ 10kΩ
VOUT = 0.2VP-P
50
VS = ±1.25
GAIN (dB)
-1
VS = ±2.5V
GAIN = 200
40
GAIN = 100
GAIN = 10
30
GAIN = 5
20
10
-2
GAIN = 2
0
VS = ±1.0V
-3
1k
10k
-10
100k
-20
1M
GAIN = 1
1
10
100
FREQUENCY (Hz)
200
INPUT OFFSET VOLTAGE (µV)
SUPPLY CURRENT (µA)
50
40
30
20
10
3
4.0
3.5
4.5
5.0
100
0
-100
-200
-0.5
5.5
0.5
1.5
2.5
3.5
4.5
5.5
OUTPUT VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
250
100
150
GAIN (dB)
NORMALIZED INPUT OFFSET VOLTAGE (µV)
10M
AV = -1
VCM = VDD/2
SUPPLY VOLTAGE (V)
50
-50
80
0
60
45
PHASE
-150
90
40
20
-250
-0.5
100k 1M
FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED
LOOP GAINS
60
2.5
10k
FREQUENCY (Hz)
FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at
VARIOUS SUPPLY VOLTAGES
0
2.0
1k
135
GAIN
180
0
0.5
1.5
2.5
3.5
4.5
5.5
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE
INPUT VOLTAGE
4
-20
10
PHASE SHIFT (°)
GAIN (dB)
GAIN = 500
60
0
RL ≥ 10kΩ
VOUT = 0.2VP-P
GAIN = 1k
70
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 6. OPEN LOOP GAIN AND PHASE vs FREQUENCY
(RL = 1kΩ)
FN7504.7
May 14, 2008
EL8178
Typical Performance Curves VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued)
10
90
0
80
-10
70
-20
90
50
PHASE
40
135
30
20
180
GAIN
10
CMRR (dB)
60
PHASE SHIFT (°)
ΔVCM = 1VP-P
RL = 100kΩ
AV = +1
-30
-40
-50
-60
-70
-80
0
-90
-10
10
-100
10
100
1k
10k
100k
1M
100
FREQUENCY (Hz)
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 8. CMRR vs FREQUENCY
FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY
(RL = 100kΩ)
10
100
1000
ΔVS = 1VP-P
RL = 100kΩ
-10
AV = +1
-20
VOLTAGE NOISE (nV/√Hz)
-30
-PSRR
-40
-50
+PSRR
-60
-70
-80
100
VOLTAGE
-100
10
10
1
10
CURRENT
-90
100
1k
10k
100k
1
1M
1
10
FREQUENCY (Hz)
100
1k
10k
0.1
100k
FREQUENCY (Hz)
FIGURE 10. INPUT VOLTAGE AND CURRENT NOISE vs
FREQUENCY
FIGURE 9. PSRR vs FREQUENCY
VOLTAGE NOISE (500nV/DIV)
PSRR (dB)
0
CURRENT NOISE (pA/√Hz)
GAIN (dB)
100
2.8µVP-P
TIME (1s/DIV)
FIGURE 11. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
5
FN7504.7
May 14, 2008
EL8178
20
18
15
13
10
VOS DRIFT (µV)
VOS DRIFT (µV)
Typical Performance Curves VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued)
5
0
-5
8
3
-2
-7
-10
-15 0
500
1000
1500
-12
1800
0
500
1000
TIME (HOURS)
FIGURE 12. VOS DRIFT (SOT-23 PACKAGE) vs TIME
FIGURE 13. VOS DRIFT (SOIC PACKAGE) vs TIME
75
5.0
n = 1500
MAX
70
1500
TIME (HOURS)
n = 1500
MAX
4.5
CURRENT (mA)
CURRENT (mA)
65
MEDIAN
60
55
50
MIN
45
3.5
3.0
MEDIAN
2.5
40
35
-40
4.0
-20
0
20
40
60
80
100
2.0
-40
120
MIN
-20
0
TEMPERATURE (°C)
MAX
200
400
100
200
0
MEDIAN
-200
MEDIAN
0
-200
-400
MIN
n = 1500
MAX
600
VOS (µV)
VOS (µV)
300
MIN
-600
-300
-400
-40
120
800
n = 1500
-100
100
FIGURE 15. DISABLED SUPPLY CURRENT vs
TEMPERATURE, VS = ±2.5V
FIGURE 14. ENABLED SUPPLY CURRENT vs
TEMPERATURE, VS = ±2.5V
400
20
40
60
80
TEMPERATURE (°C)
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 16. VOS vs TEMPERATURE, VS = ±2.5V
6
-800
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 17. VOS vs TEMPERATURE, VS = ±1.2V
FN7504.7
May 14, 2008
EL8178
Typical Performance Curves VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued)
250
450
n = 5000
n = 5000
350
IBIAS- (pA)
IBIAS+ (pA)
200
150
MEDIAN
100
MAX
300
250
200
MEDIAN
150
100
50
0
400
MAX
MIN
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
0
-40
120
FIGURE 18. IBIAS+ vs TEMPERATURE, VS = ±2.5V
MIN
50
-20
0
510
MAX
410
AVOL (V/mV)
IOS (pA)
150
MEDIAN
100
0
MEDIAN
310
-20
0
20
40
60
80
TEMPERATURE (°C)
100
MIN
210
MIN
160
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 20. IOS vs TEMPERATURE, VS = ±2.5V
FIGURE 21. AVOL vs TEMPERATURE, RL = 100k, VO = ±2V @
VS = ±2.5V
130
130
MAX
n = 1500
125
PSRR (dB)
110
105
MEDIAN
100
95
115
110
MEDIAN
105
100
95
90
MIN
85
80
-40
MAX
n = 1500
120
115
CMRR (dB)
360
260
50
120
MAX
460
200
-50
-40
120
n = 1500
n = 5000
250
100
FIGURE 19. IBIAS- vs TEMPERATURE, VS = ±2.5V
300
125
20
40
60
80
TEMPERATURE (°C)
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 22. CMRR vs TEMPERATURE, V+ = ±2.5V, ±1.5V
7
MIN
90
85
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 23. PSRR vs TEMPERATURE ±1.5V TO ±2.5V
FN7504.7
May 14, 2008
EL8178
Typical Performance Curves VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued)
4.90
4.9984
n = 1500
4.89
4.9980
MAX
MAX
4.9978
VOUT (V)
4.88
VOUT (V)
n = 1500
4.9982
4.87
MEDIAN
4.86
4.9976
4.9974
MEDIAN
4.9972
4.9970
4.9968
4.85
4.9964
4.84
-40
-20
0
20
40
60
MIN
4.9966
MIN
80
100
120
-40
-20
0
FIGURE 24. VOUT HIGH vs TEMPERATURE, VS = ±2.5V,
RL = 1k
190
180
5.0
n = 1500
4.8
MAX
60
80
100
120
n = 1500
MAX
4.6
160
4.4
MEDIAN
VOUT (mV)
VOUT (mV)
40
FIGURE 25. VOUT HIGH vs TEMPERATURE, VS = ±2.5V,
RL = 100k
170
150
140
MIN
130
MEDIAN
4.2
4.0
MIN
3.8
3.6
120
3.4
110
100
20
TEMPERATURE (°C)
TEMPERATURE (°C)
3.2
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 26. VOUT LOW vs TEMPERATURE, VS = ±2.5V,
RL = 1k
8
3.0
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 27. VOUT LOW vs TEMPERATURE, VS = ±2.5V,
RL = 100k
FN7504.7
May 14, 2008
EL8178
Pin Descriptions
SO PIN
NUMBER
SOT-23 PIN
NUMBER
PIN NAME
1
EQUIVALENT
CIRCUIT
NC
DESCRIPTION
No internal connection
2
4
IN-
Circuit 1
Amplifier’s inverting input
3
3
IN+
Circuit 1
Amplifier’s non-inverting input
4
2
V-
Circuit 4
Negative power supply
5
NC
No internal connection
6
1
OUT
Circuit 3
Amplifier’s output
7
6
V+
Circuit 4
Positive power supply
8
5
EN
Circuit 2
Amplifier’s enable pin with internal pull-down; Logic “1” selects the disabled
state; Logic “0” selects the enabled state.
V+
V+
IN-
IN+
CAPACITIVELY
COUPLED
ESD CLAMP
V-
V-
CIRCUIT 2
Application Information
Introduction
The EL8178 is a rail-to-rail input and output (RRIO),
micropower, precision, single supply op amp with an enable
feature. This amplifier is designed to operate from single
supply (2.4V to 5.5V) or dual supply (±1.2V to ±2.75V) while
drawing only 55µA of supply current.The device achieves
rail-to-rail input and output operation while eliminating the
drawbacks of many conventional RRIO op amps.
Rail-to-Rail Input
The PFET input stage of the EL8178 has an input
common-mode voltage range that includes the negative and
positive supplies without introducing offset errors or
degrading performance like some existing rail-to-rail input
op amps. Many rail-to-rail input stages use two differential
input pairs: a long-tail PNP (or PFET) and an NPN (or
NFET). Severe penalties result from using this topology. As
the input signal moves from one supply rail to the other, the
op amp switches from one input pair to the other causing
changes in input offset voltage and an undesired change in
the input offset current’s magnitude and polarity.
The EL8178 achieves rail-to-rail input performance without
sacrificing important precision specifications and without
degrading distortion performance. The EL8178's input offset
voltage exhibits a smooth behavior throughout the entire
common-mode input range.
9
V+
OUT
EN
V-
CIRCUIT 1
V+
VCIRCUIT 3
CIRCUIT 4
Rail-to-Rail Output
A pair of complementary MOSFET devices achieve rail-to-rail
output swing. The NMOS sinks current to swing the output in
the negative direction, while the PMOS sources current to
swing the output in the positive direction. The EL8178 with a
100kΩ load swings to within 3mV of the supply rails.
Results of Overdriving the Output
Caution should be used when overdriving the output for long
periods of time. Overdriving the output can occur in three ways:
1. The input voltage times the gain of the amplifier exceeds the
supply voltage by a large value.
2. The output current required is higher than the output stage
can deliver.
3. Operating the device in slew rate limit. These conditions can
result in a shift in the Input Offset Voltage (VOS) as much as
1µV/hr of exposure under these conditions.
Enable/Disable Feature
The EL8178 features an active low EN pin that when pulled
up to at least 2V, disables the output and drops the ICC to a
3µA. The EN pin has an internal pull-down, so an undriven
pin pulls to the negative rail, thereby enabling the op amp by
default. For applications where the EN pin is not being used,
it is recommended that the EN pin be permanently tyed to
ground.
The high impedance output during disable allows for
connecting multiple EL8178s together to implement a Mux
Amp. The outputs are connected together and activating the
appropriate EN pin selects the desired channel. If utilizing
non-unity gain op amp configurations, then the loading
FN7504.7
May 14, 2008
EL8178
effects of the disabled amplifiers’ feedback networks must be
considered when evaluating the active amplifier’s
performance in Mux Amp configurations.
Note that feed through from the IN+ to IN- pins occurs on
any Mux Amp disabled channel where the input differential
voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while
disabled channel VIN = GND), so the mux implementation is
best suited for small signal applications. In any application
where two or more amplifier outputs are muxed, use series
IN+ resistors, or large value RFs in each amplifier to keep
the feed through current low enough to minimize the impact
on the active channel. See “Usage Implications” on page 10
for more details.
IN+ and IN- Input Protection
In addition to ESD protection diodes to each supply rail, the
EL8178 has additional back-to-back protection diodes across
the differential input terminals. If the magnitude of the
differential input voltage exceeds the diode’s VF, then one of
these diodes will conduct. For elevated temperatures, the
leakage of the protection diodes (see Circuit 1 in “Pin
Descriptions” on page 9) increases, resulting in the increase
in IBIAS, as seen in Figures 18 and 19.
EN Input Protection
The EN input has internal ESD protection diodes to both the
positive and negative supply rails, limiting the input voltage
range to within one diode beyond the supply rails
(see “Circuit 2” diagram on page 9). If the input voltage is
expected to exceed V+ or V-, then an external series resistor
should be added to limit the current to 5mA.
Output Current Limiting
The EL8178 has no internal current-limiting circuitry. If the
output is shorted, it is possible to exceed the “Absolute
Maximum Rating” for “operating junction temperature”,
potentially resulting in the destruction of the device.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperature (TJMAX) under certain load and power-supply
conditions. It is therefore important to calculate TJMAX for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to remain in
the safe operating area. These parameters are related in
Equation 1:
T JMAX = T MAX + ( θ JA xPD MAX )
(EQ. 1)
USAGE IMPLICATIONS
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the
input current never exceeds 5mA. For noninverting unity gain
applications, the current limiting can be via a series IN+ resistor,
or via a feedback resistor of appropriate value. For other gain
configurations, the series IN+ resistor is the best choice, unless
the feedback (RF) and gain setting (RG) resistors are both
sufficiently large to limit the input current to 5mA.
Large differential input voltages can arise from several
sources:
1. During open loop (comparator) operation. The IN+ and
IN- input voltages don’t track.
2. When the amplifier is disabled but an input signal is still
present. An RL or RG to GND keeps the IN- at GND, while
the varying IN+ signal creates a differential voltage. Mux
Amp applications are similar, except that the active
channel VOUT determines the voltage on the IN- terminal.
where PDMAX is calculated using Equation 2:
V OUTMAX
PD MAX = V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R
(EQ. 2)
L
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of the amplifier
• VS = Supply voltage
• IMAX = Maximum supply current of the amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
3. When the slew rate of the input pulse is considerably
faster than the op amp’s slew rate. If the VOUT can’t keep
up with the IN+ signal, a differential voltage results, and
visible distortion occurs on the input and output signals.
To avoid this issue, keep the input slew rate below
0.2V/µs, or use appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled ICC.
10
FN7504.7
May 14, 2008
EL8178
Proper Layout Maximizes Precision
To achieve the optimum levels of high input impedance
(i.e., low input currents) and low offset voltage, care should
be taken in the circuit board layout. The PC board surface
must remain clean and free of moisture to avoid leakage
currents between adjacent traces. Surface coating of the
circuit board will reduce surface moisture and provide a
humidity barrier, reducing parasitic resistance on the board.
When input leakage current is a paramount concern, the use
of guard rings around the amplifier inputs will further reduce
leakage currents. Figure 28 shows a guard ring example for
a unity gain amplifier that uses the low impedance amplifier
output at the same voltage as the high impedance input to
eliminate surface leakage. The guard ring does not need to
be a specific width, but it should form a continuous loop
around both inputs. For further reduction of leakage
currents, mount components to the PC board using Teflon
standoffs..
V+
HIGH IMPEDANCE INPUT
Typical Applications
V+
+
EL8178
V-
GENERAL
PURPOSE
COMBINATION
pH PROBE
+
COAX
3V
FIGURE 29. pH PROBE AMPLIFIER
A general-purpose combination pH probe has extremely
high output impedance typically in the range of 10GΩ to
12GΩ. Low loss and expensive Teflon cables are often used
to connect the pH probe to the meter electronics. Figure 29
details a low-cost alternative solution using the EL8178 and
a low-cost coax cable. The EL8178 PMOS high impedance
input senses the pH probe output signal and buffers it to
drive the coax cable. Its rail-to-rail input nature also
eliminates the need for a bias resistor network required by
other amplifiers in the same application.
R4
IN
100kΩ
FIGURE 28. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
R3
10kΩ
R2
10kΩ
K TYPE
THERMOCOUPLE
V+
+
EL8178
V-
410μV/°C
+
5V
R1
100kΩ
FIGURE 30. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature sensing
devices because of their low cost, interchangeability, and
ability to measure a wide range of temperatures. In
Figure 30, the EL8178 converts the differential thermocouple
voltage into single-ended signal with 10x gain. The EL8178's
rail-to-rail input characteristic allows the thermocouple to be
biased at ground and permits the op amp to operate from a
single 5V supply.
11
FN7504.7
May 14, 2008
EL8178
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
12
FN7504.7
May 14, 2008
EL8178
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
TOLERANCE
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
Rev. F 2/07
NOTES:
C
A2
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
0.25
0° +3°
-0°
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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13
FN7504.7
May 14, 2008
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