DATASHEET

HI5731
Data Sheet
October 2, 2015
12-Bit, 100MSPS, High Speed D/A
Converter
Features
• Pb-free Available as an Option
The HI5731 is a 12-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
-20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 12-bit linearity is maintained along the
entire transfer curve.
PART NUMBER
HI5731BIPZ (No
longer available,
recommended
replacement:
HI5731BIBZ)
(See Note)
-40 to 85
HI5731BIBZ
(See Note)
-40 to 85
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . 3.0pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
Applications
• Cellular Base Stations
Ordering Information
TEMP.
RANGE (°C)
FN4070.10
PACKAGE
28 Ld PDIP
(Pb-free)
PKG. DWG.
#
• GSM Base Stations
• Wireless Communications
• Direct Digital Frequency Synthesis
E28.6
• Signal Reconstruction
• Test Equipment
• High Resolution Imaging Systems
28 Ld SOIC
(Pb-free)
M28.3
• Arbitrary Waveform Generators
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
1
Pinout
HI5731
(PDIP, SOIC)
TOP VIEW
1
28 DGND
D10 2
27 AGND
D11 (MSB)
D9 3
26 REF OUT
D8 4
25 CTRL OUT
D7 5
24 CTRL IN
D6 6
23 RSET
D5 7
22 AVEE
D4 8
21 IOUT
D3 9
20 IOUT
D2 10
19 ARTN
D1 11
18 DVEE
D0 (LSB) 12
17 DGND
NC 13
16 DVCC
NC 14
15 CLOCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas LLC
Copyright © Intersil Americas Inc. 2002, 2004,2015. All Rights Reserved
HI5731
Typical Application Circuit
+5V
HI5731
0.01F
DVCC (16)
D11
D11 (MSB) (1)
D10
D10 (2)
D9
D9 (3)
D8
D8 (4)
D7
D7 (5)
D6
D6 (6)
D5
D5 (7)
D4
D4 (8)
D3
D3 (9)
D2
D2 (10)
D1
D1 (11)
D0
D0 (LSB) (12)
0.1F
(24) CTRL IN
(25) CTRL OUT
-5.2V (AVEE)
(26) REF OUT
D/A OUT
(21) IOUT
64
64
(20) IOUT
(23) RSET
976
(19) ARTN
CLK (15)
(27) AGND
50
DGND (17, 28)
(22) AVEE
DVEE (18)
0.01F
0.01F
0.1F
0.1F
- 5.2V (AVEE)
- 5.2V (DVEE)
Functional Block Diagram
(LSB) D0
D1
D2
D3
8 LSBs
CURRENT
CELLS
D4
12-BIT
MASTER
REGISTER
D5
D6
DATA
BUFFER/
LEVEL
SHIFTER
R2R
NETWORK
ARTN
SLAVE
REGISTER
227
D7
227
D8
15
D9
15
UPPER
4-BIT
DECODER
D10
15
SWITCHED
CURRENT
CELLS
IOUT
(MSB) D11
IOUT
REF CELL
CTRL
IN
CLK
+
OVERDRIVEABLE
VOLTAGE
REFERENCE
AVEE
AGND
DVEE
2
DGND DVCC
-
REF OUT
RSET
25
CTRL
OUT
HI5731
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN. . . . . -5.5V
Digital Input Voltages (D11-D0, CLK) to DGND . . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . 2.5mA
Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . 2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . .-3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Thermal Resistance (Typical, Note 1)
JA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature
HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal
TA = 25oC for All Typical Values
HI5731BI
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
-
-
Bits
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
(Note 4) (“Best Fit” Straight Line)
-
0.75
1.5
LSB
Differential Linearity Error, DNL
(Note 4)
-
0.5
1.0
LSB
Offset Error, IOS
(Note 4)
-
20
75
A
Full Scale Gain Error, FSE
(Notes 2, 4)
-
1
10
%
Full Scale Gain Drift
With Internal Reference
-
50
-
ppm
FSR/oC
Offset Drift Coefficient
(Note 3)
-
-
0.05
A/oC
-
20.48
-
mA
(Note 3)
-1.25
-
0
V
Throughput Rate
(Note 3)
100
-
-
MSPS
Output Voltage Full Scale Step
Settling Time, tSETT , Full Scale
To 0.5 LSB Error Band RL = 50
(Note 3)
-
20
-
ns
Singlet Glitch Area, GE (Peak)
RL = 50(Note 3)
-
5
-
pV-s
-
3
-
pV-s
Full Scale Output Current, IFS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Doublet Glitch Area, (Net)
Output Slew Rate
RL = 50,DAC Operating in Latched Mode (Note 3)
-
1,000
-
V/s
Output Rise Time
RL = 50,DAC Operating in Latched Mode (Note 3)
-
675
-
ps
Output Fall Time
RL = 50,DAC Operating in Latched Mode (Note 3)
-
470
-
ps
Spurious Free Dynamic Range within a Window
(Note 3)
fCLK = 10MSPS, fOUT = 1.23MHz, 2MHz Span
-
85
-
dBc
fCLK = 20MSPS, fOUT = 5.055MHz, 2MHz Span
-
77
-
dBc
fCLK = 40MSPS, fOUT = 16MHz, 10MHz Span
-
75
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz, 2MHz Span
-
80
-
dBc
fCLK = 80MSPS, fOUT = 5.1MHz, 2MHz Span
-
78
-
dBc
fCLK = 100MSPS, fOUT = 10.1MHz, 2MHz Span
-
79
-
dBc
3
HI5731
Electrical Specifications
AVEE , DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal
TA = 25oC for All Typical Values (Continued)
HI5731BI
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
Spurious Free Dynamic Range to Nyquist
(Note 3)
MIN
TYP
MAX
UNITS
fCLK = 40MSPS, fOUT = 2.02MHz, 20MHz Span
-
70
-
dBc
fCLK = 80MSPS, fOUT = 2.02MHz, 40MHz Span
-
70
-
dBc
fCLK = 100MSPS, fOUT = 2.02MHz, 50MHz Span
-
69
-
dBc
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, VREF
(Note 4)
-1.27
-1.23
-1.17
V
Internal Reference Voltage Drift
(Note 3)
-
175
-
V/oC
Internal Reference Output Current Sink/Source
Capability
(Note 3)
-125
-
+50
A
Internal Reference Load Regulation
IREF = 0 to IREF = -125A
-
50
-
V
Input Impedance at REF OUT pin
(Note 3)
-
1.4
-
k
Amplifier Large Signal Bandwidth (0.6VP-P)
Sine Wave Input, to Slew Rate Limited (Note 3)
-
3
-
MHz
Amplifier Small Signal Bandwidth (0.1VP-P)
Sine Wave Input, to -3dB Loss (Note 3)
-
10
-
MHz
Reference Input Impedance
(Note 3)
-
12
-
k
Reference Input Multiplying Bandwidth (CTL IN)
RL = 50, 100mV Sine Wave, to -3dB Loss at IOUT
(Note 3)
-
200
-
MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, VIH
(Note 4)
2.0
-
-
V
Input Logic Low Voltage, VIL
(Note 4)
-
-
0.8
V
Input Logic Current, IIH
(Note 4)
-
-
400
A
Input Logic Current, IIL
(Note 4)
-
-
700
A
Digital Input Capacitance, CIN
(Note 3)
-
3.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 1 (Note 3)
3.0
2.0
-
ns
Data Hold Time, tHLD
See Figure 1 (Note 3)
0.5
0.25
-
ns
Propagation Delay Time, tPD
See Figure 1 (Note 3)
-
4.5
-
ns
CLK Pulse Width, tPW1, tPW2
See Figure 1 (Note 3)
3.0
-
-
ns
POWER SUPPLY CHARACTERISTICS
IEEA
(Note 4)
-
42
50
mA
IEED
(Note 4)
-
70
85
mA
ICCD
(Note 4)
-
13
20
mA
Power Dissipation
(Note 4)
-
650
-
mW
Power Supply Rejection Ratio
VCC 5%, VEE 5%
-
5
-
A/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 1.28mA). Ideally the
ratio should be 16.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25oC.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
4
HI5731
Timing Diagrams
50%
CLK
GLITCH AREA = 1/2 (H x W)
V
D11-D0
HEIGHT (H)
1/2 LSB ERROR BAND
IOUT
t(ps)
WIDTH (W)
tSETT
tPD
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
tPW1
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
tPW2
50%
CLK
tSU
tSU
tHLD
tSU
tHLD
tHLD
D11-D0
tPD
IOUT
tPD
tPD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
5
HI5731
Typical Performance Curves
680
-1.21
CLOCK FREQUENCY DOES NOT
ALTER POWER DISSIPATION
-1.23
(V)
(mW)
640
-1.25
600
-1.27
560
-1.29
-50
-30
-10
10
30
50
70
90
-50
TEMPERATURE
-30
-10
10
30
50
70
90
TEMPERATURE
FIGURE 4. TYPICAL POWER DISSIPATION OVER
TEMPERATURE
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER
TEMPERATURE
1.5
0.8
0.4
(LSB)
(LSB)
0.5
-0.5
0.0
-0.4
-0.8
1.5
0
600
1200
1800
2400
3000
3600
400
4200
1000
1600
2200
2800
3400
4000
CODE
CODE
FIGURE 6. TYPICAL INL
FIGURE 7. TYPICAL DNL
ATTEN 20dB
RL -10.0dBm
28
10dB/
MKR -87.33dB
-73kHz
fC = 10MSPS
(A)
24
20
S
16
12
C
-40
-20
-0
20
40
60
80
TEMPERATURE
FIGURE 8. OFFSET CURRENT OVER TEMPERATURE
6
100
CENTER 1.237MHz
SPAN 2.000MHz
FIGURE 9. SPURIOUS FREE DYNAMIC RANGE = 87.3dBc
HI5731
Typical Performance Curves
ATTEN 20dB
RL -10.0dBm
10dB/
(Continued)
MKR -76.16dB
-53kHz
ATTEN 20dB
RL -10.0dBm
10dB/
MKR -75.17dB
-70kHz
fC = 40MSPS
fC = 20MSPS
S
C
C
CENTER 5.055MHz
SPAN 2.000MHz
FIGURE 10. SPURIOUS FREE DYNAMIC RANGE = 76.16dBc
ATTEN 20dB
RL -10.0dBm
10dB/
CENTER 16.00MHz
SPAN 10.00MHz
FIGURE 11. SPURIOUS FREE DYNAMIC RANGE = 75.17dBc
MKR -81.67dB
-953kHz
ATTEN 20dB
RL -10.0dBm
10dB/
fC = 50MSPS
MKR -77.00dB
-93kHz
fC = 80MSPS
S
C
C
CENTER 10.100MHz
FIGURE 12. SPURIOUS FREE DYNAMIC RANGE = -81.67dBc
ATTEN 20dB
RL -10.0dBm
CENTER 5.097MHz
SPAN 2.000MHz
10dB/
FIGURE 13. SPURIOUS FREE DYNAMIC RANGE = 77dBc
MKR -85.60dB
-33kHz
ATTEN 20dB
RL -10.0dBm
fC = 100MSPS
S
C
C
SPAN 2.000MHz
FIGURE 14. SPURIOUS FREE DYNAMIC RANGE = -85.60dBc
7
10dB/
MKR -85.50dB
73kHz
fC = 100MSPS
S
CENTER 2.027MHz
SPAN 2.000MHz
CENTER 5.000MHz
SPAN 2.000MHz
FIGURE 15. SPURIOUS FREE DYNAMIC RANGE = 85.5dBc
HI5731
Typical Performance Curves
ATTEN 20dB
RL -10.0dBm
(Continued)
MKR -80.50dB
-807kHz
10dB/
ATTEN 20dB
RL -10.0dBm
10dB/
fC = 100MSPS
MKR -72.17dB
-467kHz
fC = 100MSPS
S
C
CENTER 10.133MHz
SPAN 2.000MHz
CENTER 26.637MHz
FIGURE 16. SPURIOUS FREE DYNAMIC RANGE = 80.5dBc
ATTEN 20dB
RL -10.0dBm
FIGURE 17. SPURIOUS FREE DYNAMIC RANGE = 72.17dBc
MKR -71.16dB
2.99MHz
10dB/
ATTEN 20dB
RL -10.0dBm
fC = 40MSPS
fO = 2.02MHz
S
C
C
STOP FREQUENCY 20MHz
START FREQUENCY 500kHz
FIGURE 18. SPURIOUS FREE DYNAMIC RANGE = 71.16dBc
ATTEN 20dB
RL -10.0dBm
10dB/
MKR -70.00dB
4.13MHz
S
C
STOP FREQUENCY 50MHz
FIGURE 20. SPURIOUS FREE DYNAMIC RANGE = 70dBc
8
MKR -70.50dB
1.98MHz
STOP FREQUENCY 40MHz
FIGURE 19. SPURIOUS FREE DYNAMIC RANGE = 70.5dBc
fC = 100MSPS
fO = 2.02MHz
START FREQUENCY 500kHz
10dB/
fC = 80MSPS
fO = 2.02MHz
S
START FREQUENCY 500kHz
SPAN 2.000MHz
HI5731
Pin Descriptions
PIN NUMBER
1-12
PIN NAME
PIN DESCRIPTION
D11 (MSB) thru Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit.
D0 (LSB)
15
CLK
13, 14
NC
Data Clock Pin DC to 100MSPS.
16
DVCC
Digital Logic Supply +5V.
17, 28
DGND
Digital Ground.
18
DVEE
-5.2V Logic supply.
No Connect.
23
RSET
External resistor to set the full scale output current. IFS = 16 x (VREF OUT / RSET). Typically 976.
27
AGND
Analog Ground supply current return pin.
19
ARTN
Analog Signal Return for the R/2R ladder.
21
IOUT
Current Output Pin.
20
IOUT
Complementary Current Output Pin.
22
AVEE
-5.2V Analog Supply.
24
CTRL IN
Input to the current source base rail. Typically connected to CTRL OUT and a 0.1F capacitor to AVEE . Allows
external control of the current sources.
25
CTRL OUT
Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such that
IFS = 16 x (VREF OUT / RSET).
26
REF OUT
-1.23V (Typ) bandgap reference voltage output. Can sink up to 125A or be overdriven by an external
reference capable of delivering up to 2mA.
Detailed Description
The HI5731 is a 12-bit, current out D/A converter. The DAC can
convert at 100MSPS and runs on +5V and -5.2V supplies. The
architecture is an R/2R and segmented switching current cell
arrangement to reduce glitch. Laser trimming is employed to
tune linearity to true 12-bit levels. The HI5731 achieves its low
power and high speed performance from an advanced
BiCMOS process. The HI5731 consumes 650mW (typical) and
has an improved hold time of only 0.25ns (typical). The HI5731
is an excellent converter for use in communications
applications and high performance instrumentation systems.
to minimize reflections and clock noise into the part proper
termination should be used. In PCB layout clock runs should
be kept short and have a minimum of loads. To guarantee
consistent results from board to board controlled impedance
PCBs should be used with a characteristic line impedance
ZO of 50.
To terminate the clock line, a shunt terminator to ground is
the most effective type at a 100MSPS clock rate. A typical
value for termination can be determined by the equation:
RT = ZO ,
Digital Inputs
The HI5731 is a TTL/CMOS compatible D/A. Data is latched
by a Master register. Once latched, data inputs D0 (LSB)
thru D11 (MSB) are internally translated from TTL to ECL.
The internal latch and switching current source controls are
implemented in ECL technology to maintain high switching
speeds and low noise characteristics.
for the termination resistor. For a controlled impedance
board with a ZO of 50, the RT = 50. Shunt termination is
best used at the receiving end of the transmission line or as
close to the HI5731 CLK pin as possible.
ZO = 50
Decoder/Driver
The architecture employs a split R/2R ladder and
Segmented Current source arrangement. Bits D0 (LSB) thru
D7 directly drive a typical R/2R network to create the binary
weighted current sources. Bits D8 thru D11 (MSB) pass thru
a “thermometer” decoder that converts the incoming data
into 15 individual segmented current source enables. This
split architecture helps to improve glitch, thus resulting in a
more constant glitch characteristic across the entire output
transfer function.
Clocks and Termination
The internal 12-bit register is updated on the rising edge of
the clock. Since the HI5731 clock rate can run to 100MSPS,
9
CLK
HI5731
DAC
RT = 50
FIGURE 21. CLOCK LINE TERMINATION
Rise and Fall times and propagation delay of the line will be
affected by the Shunt Terminator. The terminator should be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1F and 0.01F
ceramic capacitors placed as close to the body of the
HI5731
HI5731 as possible on the analog (AVEE ) and digital (DVEE )
supplies. The analog and digital ground returns should be
connected together back at the device to ensure proper
operation on power up. The VCC power pin should also be
decoupled with a 0.1F capacitor.
Reference
The internal reference of the HI5731 is a -1.23V (typical)
bandgap voltage reference with 175V/oC of temperature
drift (typical). The internal reference is connected to the
Control Amplifier which in turn drives the segmented current
cells. Reference Out (REF OUT) is internally connected to
the Control Amplifier. The Control Amplifier Output (CTRL
OUT) should be used to drive the Control Amplifier Input
(CTRL IN) and a 0.1F capacitor to analog VEE. This
improves settling time by providing an AC ground at the
current source base node. The Full Scale Output Current is
controlled by the REF OUT pin and the set resistor (RSET).
The ratio is:
IOUT (Full Scale) = (VREF OUT /RSET) x 16,
The internal reference (REF OUT) can be overdriven with a
more precise external reference to provide better
performance over temperature. Figure 22 illustrates a typical
external reference configuration.
required. The lower input bandwidth can be calculated using
the following formula:
1
C IN = -------------------------------------------.
 2    1400   f IN 
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 24.
HI5731
CTRL OUT
200
VIN
C1
C2
AVEE
CTRL IN
50
FIGURE 24. HIGH FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
The nominal input/output relationship is defined as:
V IN
I OUT = -------------- .
80
In order to prevent the full scale output current from
exceeding 20.48mA, the RSET resistor must be adjusted
according to the following equation:
16V REF
R SET = ----------------------------------------------------------------------------------------------- .
V IN  PEAK 
I OUT (FULL SCALE) –  -----------------------------

80 
HI5731
-1.25V
(26) REF OUT
R
-5.2V
The circuit in Figure 24 can be tuned to adjust the lower
cutoff frequency by adjusting capacitor values. Table 1 below
illustrates the relationship.
FIGURE 22. EXTERNAL REFERENCE CONFIGURATION
TABLE 1. CAPACITOR SELECTION
Multiplying Capability
The HI5731 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal
of up to 0.6VP-P can be applied directly to the REF OUT pin
as shown in Figure 23.
HI5731
CTRL OUT
CTRL IN
0.01F
C1
C2
100kHz
0.01F
1F
>1MHz
0.001F
0.1F
Also, the input signal must be limited to 1VP-P to avoid
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
Outputs
AVEE
REF OUT
VIN
fIN
CIN (OPTIONAL)
RSET
FIGURE 23. LOW FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
The signal must have a DC value such that the peak
negative voltage equals -1.25V. Alternately, a capacitor can
be placed in series with REF OUT if DC multiplying is not
10
The outputs IOUT and IOUT are complementary current
outputs. Current is steered to either IOUT or IOUT in
proportion to the digital input code. The sum of the two
currents is always equal to the full scale current minus one
LSB. The current output can be converted to a voltage by
using a load resistor. Both current outputs should have the
same load resistor (64 typically). By using a 64 load on
the output, a 50 effective output resistance (ROUT) is
achieved due to the 227 (15%) parallel resistance seen
looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50 output is needed for
matching the output with a 50 line. The load resistor should
HI5731
be chosen so that the effective output resistance (ROUT)
matches the line resistance. The output voltage is:
as glitch when changing the DAC output. Units are typically
specified in picoVolt-seconds (pV-s).
VOUT = IOUT x ROUT.
HI5731
IOUT is defined in the reference section. IOUT is not trimmed
to 12 bits, so it is not recommended that it be used in
conjunction with IOUT in a differential-to-single-ended
application. The compliance range of the output is from 1.25V to 0V, with a 1VP-P voltage swing allowed within this
range.
TABLE 2.
IOUT (mA)
IOUT (mA)
1111 1111 1111
-20.48
0
1000 0000 0000
-10.24
-10.24
0000 0000 0000
0
-20.48
Settling Time
SCOPE
64
INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D11-D0)
100MHz
LOW PASS
FILTER
(21) IOUT
50
FIGURE 25. GLITCH TEST CIRCUIT
a (mV)
The settling time of the HI5731 is measured as the time it
takes for the output of the DAC to settle to within a ± 1/2 LSB
error band of its final value during a full scale (code 0000...
to 1111.... or 1111... to 0000...) transition. All claims made by
Intersil with respect to the settling time performance of the
HI5731 have been fully verified by the National Institute of
Standards and Technology (NIST) and are fully traceable.
Glitch
The output glitch of the HI5731 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. In order to minimize this, the
Intersil HI5731 employes an internal register, just prior to the
current sources, which is updated on the clock edge. Lastly,
the worst case glitch on traditional D/A converters usually
occurs at the major transition (i.e., code 2047 to 2048).
However, due to the split architecture of the HI5731, the
glitch is moved to the 255 to 256 transition (and every
subsequent 256 code transitions thereafter). This split R/2R
segmented current source architecture, which decreases the
amount of current switching at any one time, makes the
glitch practically constant over the entire output range. By
making the glitch a constant size over the entire output
range this effectively integrates this error out of the end
application.
In measuring the output glitch of the HI5731 the output is
terminated into a 64 load. The glitch is measured at any
one of the current cell carry (code 255 to 256 transition or
any multiple thereof) throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 26 shows the area considered
11
GLITCH ENERGY = (a x t)/2
t (ns)
FIGURE 26. MEASURING GLITCH ENERGY
Applications
Bipolar Applications
To convert the output of the HI5731 to a bipolar 4V swing,
the following applications circuit is recommended. The
reference can only provide 125A of drive, so it must be
buffered to create the bipolar offset current needed to
generate the -2V output with all bits ‘off’. The output current
must be converted to a voltage and then gained up and
offset to produce the proper swing. Care must be taken to
compensate for the voltage swing and error.
5k
REF OUT
(26)
-
+
-
5k
1/ CA2904
2
+
1/ CA2904
2
0.1F
HI5731
60
240
240
50
IOUT
(21)
-
VOUT
+
HFA1100
FIGURE 27. BIPOLAR OUTPUT CONFIGURATION
HI5731
Interfacing to the HSP45106 NCO-16
The HSP45106 is a 16-bit, Numerically Controlled Oscillator
(NCO). The HSP45106 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 28 shows how to interface an HI5731 to
the HSP45106.
Interfacing to the HSP45102 NCO-12
The HSP45102 is a 12-bit, Numerically Controlled Oscillator
(NCO). The HSP45102 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 29 shows how to interface an HI5731 to
the HSP45102.
This high level block diagram is that of a basic PSK
modulator. In this example the encoder generates the PSK
waveform by driving the Phase Modulation Inputs (P1, P0) of
the HSP45102. The P1-0 inputs impart a phase shift to the
carrier wave as defined in Table 2.
TABLE 3. PHASE MODULATION INPUT CODING
P1
P0
PHASE SHIFT (DEGREES)
0
0
0
0
1
90
1
0
270
1
1
180
The data port of the HSP45102 drives the 12-bit HI5731
DAC which converts the NCO output into an analog
waveform. The output filter connected to the DAC can be
tailored to remove unwanted spurs for the desired carrier
frequency. The controller is used to load the desired center
frequency and control the HSP45102. The HI5731 coupled
with the HSP45102 make an inexpensive PSK modulator
with Spurious Free performance down to -76dBc.
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
error in step size between adjacent codes along the
converter’s transfer curve. Ideally, the step size is 1 LSB
from one code to the next, and the deviation from 1 LSB is
known as DNL. A DNL specification of greater than -1 LSB
guarantees monotonicity.
Feedthru, is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time, is the time
required from the 50% point on the clock input for a full scale
step to settle within an 1/2 LSB error band.
Output Voltage Small Scale Settling Time, is the time
required from the 50% point on the clock input for a 100mV
12
step to settle within an 1/2 LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
Glitch Area, GE, is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a picoVolt-time
specification (typically pV-s).
Differential Gain, AV, is the gain error from an ideal sine
wave with a normalized amplitude.
Differential Phase, , is the phase error from an ideal sine
wave.
Signal to Noise Ratio, SNR, is the ratio of a fundamental to
the noise floor of the analog output. The first 5 harmonics
are ignored, and an output filter of 1/2 the clock frequency is
used to eliminate alias products.
Total Harmonic Distortion, THD, is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The
first 5 harmonics are included, and an output filter of 1/2 the
clock frequency is used to eliminate alias products.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into the
D/A and the output filtered at 1/2 the clock frequency to
eliminate noise from clocking alias terms.
Intermodulation Distortion, IMD, is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
20Log (RMS of Sum and Difference Distortion Products)
IMD = ------------------------------------------------------------------------------------------------------------------------------------------------------- .
 RMS Amplitude of the Fundamental 
HI5731
U2
33MSPS
CLK
BASEBAND
BIT
STREAM
K9
C11
B11
ENCODER
C10
A11
F10
F9
F11
H11
G11
G9
J11
G10
D10
VCC
CONTROLLER
J10
K11
B8
A8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
B10
B9
A10
E11
E9
VCC H10
K2
J2
V
CC
CLK
MOD2
MOD1
U1
MOD0
PMSEL
DACSTRB
ENPOREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
INITPAC
INITTAC
TEST
PARSER
BINFMT
C15_MSB
C4
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
A2
A1
A0
CS
WR
FILTER
SIN15
SIN14
SIN13
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
SIN0
COS15
COS14
COS13
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
PACI
TICO
L1
K3
L2
L3
L4
J5
K5
L5
K6
J6
J7
L7
L6
L8
K8
L9
L10
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
K1
VCC
16
1
2
3
4
5
6
7
8
9
10
11
12
15
R4
50
DVCC
IOUT
D11 (MSB)
D10
IOUT
D9
D8
D7
CNTRL IN
D6
D5
D4 CNTRL OUT
D3
D2
D1
D0 (LSB)
REF OUT
CLK
RSET
28
DGND
17
DGND
ARET
R1
21
64
R2
20
64
24
25
0.1F
C1
0.01F
26
R3
23
976
19
18
AVEE
DVEE
22
-5.2V_A
HI5731
L1
-5.2V_D
10H
-5.2V_A
L2
10H
B2
OES
OEC
HSP45106
FIGURE 28. MODULATOR USING THE HI5731 AND THE HSP45106 16-BIT NCO
13
C2
AVSS 27
-5.2V_D
TO RF
UP-CONVERT
STAGE
-5.2V_A
-5.2V_A
HI5731
FILTER
U2
U1
BASEBAND
BIT
STREAM
40MSPS
I CLK
ENCODER
Q
16
19
20
18
17
12
9
CONTROLLER
CONTROL
BUS
14
13
10
11
VCC
CLK
P1
P0
LOAD#
TXFR#
ENPHAC#
SEL_L/M#
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
16
DVCC
IOUT
1
2
3
4
5
6
7
8
9
10
11
12
6
5
4
3
2
1
28
27
26
25
24
23
D11 (MSB)
D10
IOUT
D9
D8
D7
CNTRL IN
D6
D5
CNTRL OUT
D4
D3
D2
D1
D0 (LSB)
REF OUT
15
CLK
SCLK
R4
50
SD
28
DGND
17
DGND
SFTEN#
RSET
ARET
R1
21
64
R2
20
64
24
25
C2
0.1F
C1
0.01F
26
R3
23
976
19
AVSS 27
MSB/LSB#
HSP45102
-5.2V_D
18 DV
EE
L1
-5.2V_D
10H
AVEE
22
-5.2V_A
HI5731
L2
-5.2V_A
10H
FIGURE 29. PSK MODULATOR USING THE HI5731 AND THE HSP45102 12-BIT NCO
14
TO RF
UP-CONVERT
STAGE
-5.2V_A
-5.2V_A
HI5731
Die Characteristics
DIE DIMENSIONS
PASSIVATION
161.5 mils x 160.7 mils x 19 mils
Type: Sandwich Passivation
Undoped Silicon Glass (USG) + Nitride
Thickness: USG - 8kÅ, Nitride - 4.2kÅ
Total 12.2kÅ + 2kÅ
METALLIZATION
Type: AlSiCu
Thickness: M1 - 8kÅ, M2 - 17kÅ
SUBSTRATE POTENTIAL (POWERED UP)
VEED
Metallization Mask Layout
D9
D10
D11
DGND
REF OUT
D8
AGND
HI5731
CTRL OUT
D7
CTRL IN
D6
RSET
D5
AVEE
D4
IOUT
D3
IOUT
D2
ARTN
D1
D0
15
CLK
DVCC
DGND
DVEE
HI5731
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
October 2, 2015
FN4070.10
CHANGE
- Updated Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD M28.3 to latest revision changes are as follow:
Added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
16
HI5731
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
-C-
SEATING
PLANE
A2
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MAX
NOTES
-
0.250
-
6.35
4
0.015
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
D
1.380
1.565
D1
0.005
-
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
35.1
39.7
5
-
5
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
17
28
28
9
Rev. 1 12/00
HI5731
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45o
a
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
B S
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
-C-
MIN
0.05 BSC
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6

10.00
-
0.394
N
0.419
1.27 BSC
H
28
0o
10.65
-
28
8o
0o
7
8o
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
(1.50mm)
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
(1.27mm TYP)
(0.51mm TYP)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
18
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