DATASHEET

QLx111GRx
Features
The QLx111GRx is a settable single-channel receive-side
equalizer with extended functionality for advanced
protocols operating with line rates up to 11.1Gb/s such
as 10G Ethernet (10GBase-CR). The QLx111GRx
compensates for the frequency dependent attenuation of
copper twin-axial cables, extending the signal reach up
to at least 10m on 28AWG cable.
• Supports data rates up to 11.1Gb/s
The small form factor, highly-integrated design is ideal
for high-density data transmission applications including
active copper cable assemblies. The equalizing filter
within the QLx111GRx can be set to provide optimal
signal fidelity for a given media and length. The
compensation level for the filter is set by two external
control pins.
Operating on a single 1.2V power supply, the QLx111GRx
enables per channel throughputs of 10Gb/s to 11.1Gb/s
while supporting lower data rates including 8.5, 6.25, 5,
4.25, 3.125, and 2.5Gb/s. The QLx111GRx uses current
mode logic (CML) input/output and is packaged in a
3mmx3mm 16 lead QFN. LOS support is included for
module applications.
• Low power (<135mW)
• Low latency (<500ps)
• Single channel equalizer in a 3mmx3mm QFN
package for straight route-through architecture and
simplified routing
• Adjustable equalizer boost
• Supports 64b/66b encoded data – long run lengths
• Line silence preservation
• 1.2V supply voltage
• LOS support
Applications
• SFP+ active copper cable modules
• QSFP active copper cable modules
• 10G Ethernet (10GBase-CR)
• XFI
• 40G Ethernet (40GBase-CR4)
• Fibre Channel
• High-speed active cable assemblies
• High-speed printed circuit board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach greater than 3x
• Improved BER
Typical Application Circuit
October 26, 2009
FN6987.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
QLx111GRx
11.1Gb/s Lane Extender
QLx111GRx
Ordering Information
PART NUMBER
(Note)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
QLX111RIQT7
QL111
0 to +70
16 Ld QFN
7” Prod. Tape & Reel; Qty 1,000
L16.3x3B
QLX111RIQSR
QL111
0 to +70
16 Ld QFN
7” Sample Reel; Qty 100
L16.3x3B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Configuration
GND
DT
LOS
GND
QLx111GRx
(16 LD QFN)
TOP VIEW
16
15
14
13
VDD 1
12 VDD
IN[P] 2
11 OUT[P]
IN[N] 3
10 OUT[N]
VDD 4
6
7
CP[A]
CP[B]
VDD
8
GND
5
GND
9
Pin Descriptions
PIN NAME
PIN
NUMBER
VDD
1, 4, 12, 9
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to
ground is recommended for each of these pins for broad high-frequency noise suppression.
IN[P,N]
2, 3
Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
CP[A,B]
6, 7
Control pins for setting the equalizer. CMOS logic inputs. Pins are read as a 2-digit number to set
the boost level. Pins are internally pulled up and down through a 23kΩ resistor.
OUT[P,N]
11, 10
Equalizer differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
LOS
14
LOS indicator. High output when equalized In signal is below DT threshold. Open drain output
internally pulled up to VDD with a 10kΩ resistor.
DT
15
Detection Threshold. Reference DC voltage threshold for input signal power detection. Data output
OUT is muted when the power of the equalized version of IN falls below the threshold. Tie to ground
to disable electrical idle preservation and always enable the limiting amplifier.
GND
DESCRIPTION
5, 8, 13, 16 Ground
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QLx111GRx
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to GND)
Voltage at All Input Pins . . . .
ESD Rating
High Speed Pins . . . . . . . .
All Other Pins . . . . . . . . . .
Operating Ambient Temperature Range . . . . . . 0°C to +85°C
Storage Ambient Temperature Range . . . . -55°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
. . . . . . . . . . . . -0.3V to 1.3V
. . . . . . . -0.3V to VDD + 0.3V
. . . . . . . . . . . . . 1.5kV (HBM)
. . . . . . . . . . . . . . 2kV (HBM)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
Operating Conditions
PARAMETER
SYMBOL
Supply Voltage
Operating Ambient Temperature
MIN
TYP
MAX
UNITS
VDD
1.1
1.2
1.3
V
TA
0
25
70
°C
11.1
Gb/s
Bit Rate
CONDITION
NRZ data applied to any channel
2.5
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
0
350
mV
VDD
mV
250
mV
VDD
mV
100
µA
Input LOW Logic Level
VIL
DI, Clk, ENB
0
Input HIGH Logic Level
VIH
DI, Clk, ENB
750
Output LOW Logic Level
VOL
LOS, DO
0
Output HIGH Logic Level
VOH
LOS, DO
1000
Input Current
Current draw on digital pin, i.e., CP[A,B], DI, Clk, ENB
Electrical Specifications
PARAMETER
0
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +85°C.
SYMBOL
Supply Current
IDD
Cable Input
Amplitude Range
VIN
30
CONDITION
MIN
TYP
MAX
111
Measured differentially at data source
before encountering channel loss
UNITS
NOTES
mA
600
1200
1600
mVP-P
DC Differential
Input Resistance
Measured on input channel IN
80
100
120
Ω
DC Single-Ended
Input Resistance
Measured on input channel IN[P] or IN[N]
40
50
60
Ω
1
Input Return Loss
(Differential)
SDD11
100MHz to 7.5GHz
12
dB
2
Input Return Loss
(Common Mode)
SCC11
100MHz to 7.5GHz
7
dB
2
Input Return Loss
(Com. to Diff. Conversion)
SDC11
100MHz to 7.5GHz
35
dB
2
Output
Amplitude Range
VOUT
Differential
Output Impedance
Measured differentially at OUT[P] and
OUT[N] with 50Ω load on both output pins
500
650
800
mVP-P
Measured on OUT
80
100
120
Ω
Output Return Loss
(Differential)
SDD22
100MHz to 7.5GHz
10
dB
2
Output Return Loss
(Common Mode)
SCC22
100MHz to 7.5GHz
5
dB
2
3
FN6987.0
October 26, 2009
QLx111GRx
Electrical Specifications
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +85°C. (Continued)
PARAMETER
SYMBOL
Output Return Loss
(Com. to Diff. Conversion)
SDC22
CONDITION
100MHz to 7.5GHz
MIN
TYP
MAX
32
UNITS
NOTES
dB
2
Output Residual
Deterministic Jitter
DJ
10Gb/s; Up to 10m 28AWG standard
twin-axial cable (approx. -27dB @ 5GHz);
1200mVP-P ≤ VIN ≤ 1600mVP-P
0.15
UI
1, 3, 4
Output Residual
Deterministic Jitter
RJ
10Gb/s; Up to 10m 28AWG standard
twin-axial cable (approx. -27dB @ 5GHz);
1200mVP-P ≤ VIN ≤ 1600mVP-P
1.3
psRMS
1, 3, 4
20% to 80%
35
ps
5
tr, tf
Output Transition Time
Propagation Delay
From IN to OUT
500
ps
LOS Assert Time
Time to assert Loss-of-Signal (LOS)
indicator when transitioning from active
data mode to line silence mode
50
µs
6
LOS De-Assert Time
Time to de-assert Loss-of-Signal (LOS)
indicator when transitioning from line
silence mode to active data mode
50
µs
6
Data-to-Line Silence
Response Time
Time to transition from active data to line
silence (muted output) on 10m 28AWG
standard twin-axial cable at 10Gb/s
50
µs
6
Line Silence-to-Data
Response Time
Time to transition from line silence mode
(muted output) to active data on 10m
28AWG standard twin-axial cable at 10Gb/s
50
µs
6
NOTES:
1. After channel loss, differential amplitudes at QLx111GRx input must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 3.
2. Temperature = +25°C, VDD = 1.2V.
3. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJpp + 14.1 x RJRMS.
4. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
5. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
6. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less.
4
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QLx111GRx
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched
into the twin-ax cable using an SMA adapter card. The chip evaluation board is connected to the output of the cable
through another adapter card. The QLx111GRx output signal is then visualized on a scope to determine signal integrity
parameters such as jitter (Note 7).
Pattern
Generator
SMA
Adapter
Card
100O
Ω Twin-Axial
Cable
SMA
Adapter
Card
QLx111G Eval
Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION SET UP
FIGURE 2. JITTER vs CABLE LENGTH AT 10Gb/s
(BOOST LEVELS 0-3)
FIGURE 3. QLx111GRx 10Gb/s OUTPUT FOR A 10M
28AWG CABLE
NOTE:
7. Prior to the tapeout, the data in Figures 2 and 3 represents simulations approximating the conditions of setup in Figure 1, not
measured data.
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QLx111GRx
FIGURE 4. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx111GRx
Operation
The QLx111GRx is an advanced lane-extender for
high-speed interconnects. A functional diagram of
QLx111GRx is shown in Figure 4. In addition to a robust
equalization filter to compensate for channel loss and
restore signal fidelity, the QLx111GRx contains unique
integrated features to preserve special signaling
protocols typically broken by other equalizers. The signal
detect function is used to mute the channel output when
the equalized signal falls below the level determined by
the Detection Threshold (DT) pin voltage. This function is
intended to preserve periods of line silence (“quiescent
state” in InfiniBand contexts). Furthermore, the output of
the Signal Detect/DT comparator is used as a loss of
signal (LOS) indicator to indicate the absence of a
received signal.
As illustrated in Figure 4, the core of the high-speed
signal path in the QLx111GRx is a sophisticated equalizer
followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. The equalizer
is followed by a limiting amplification stage that provides
a clean output signal with full amplitude swing and fast
rise-fall times for reliable signal decoding in a subsequent
receiver.
Adjustable Equalization Boost
QLx111GRx features a settable equalizer for custom
signal restoration. The flexibility of this adjustable
compensation architecture enables signal fidelity to be
optimized on a channel-by-channel basis, providing
support for a wide variety of channel characteristics and
data rates ranging from 2.5Gb/s to 11.3Gb/s. Because
the boost level is externally set rather than internally
adapted, the QLx111GRx provides reliable
communication from the very first bit transmitted. There
is no time needed for adaptation and control loop
convergence. Furthermore, there are no pathological
data patterns that will cause the QLx111GRx to move to
an incorrect boost level.
6
FIGURE 5. GAIN PROFILE FOR VARIOUS BOOST
SETTINGS IN QLx111GRx
Control Pin Boost Setting
The connectivity of the CP pins are used to determine the
boost level of QLx111GRx. Table 1 defines the mapping
from the 2-bit CP word to the 5 available boost levels.
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND CPPIN CONNECTIVITY
CP[A]
CP[B]
BOOST LEVEL
No Connect
No Connect
0
No Connect
Gnd
1
No Connect
VDD
2
Gnd
No Connect
3
Gnd
Gnd
4
CML Input and Output Buffers
The input and output buffers for the high-speed data
channel in the QLx111GRx are implemented using CML.
Equivalent input and output circuits are shown in
Figures 6 and 7.
FN6987.0
October 26, 2009
QLx111GRx
Line Silence/Quiescent Mode
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx111GRx contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the
fidelity-enhancing benefits of limiting amplification during
active data transmission. Line silence is detected by
measuring the amplitude of the equalized signal and
comparing that to a threshold set by the voltage at the
DT pin. When the amplitude falls below the threshold,
the output driver stage is muted.
LOS Indicator
FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR
THE QLx111GRx
Pin LOS is used to output the state of the muting circuitry
to serve as a loss of signal indicator for the device. This
signal is directly derived from the muting signal off the
DT-threshold signal detector output. The LOS signal goes
HIGH when the power signal is below the DT threshold
and LOW when the power goes above the DT threshold.
This feature is meant to be used in optical systems (e.g.
SFP+) where there are no quiescent or electrical-idle
states. In these cases, the DT threshold is used to
determine the sensitivity of the LOS indicator.
Detection Threshold (DT) Pin Functionality
The QLx111GRx is capable of maintaining periods of line
silence by monitoring each channel for loss of signal
(LOS) conditions and subsequently muting the outputs of
a respective channel when such a condition is detected. A
reference voltage applied to the detection threshold (DT)
pin is used to set the LOS threshold of the internal signal
detection circuitry. Voltage control on the DT pin is done
via two external resistors. Both a pull-up and pull-down
resistor are tied to the DT pin, with suggested values
indicated in Figure 8. Other values of the resistors may
also be applicable; therefore customers are advised to
verify DT settings for their specific application.
FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx111GRx
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QLx111GRx
Typical Application Reference Design
1.2V
69Ω
2.5/3.3V
10kΩ
16
GND
LOS
1.2V
DT
GND
50Ω
15
14
1.2V
13
VDD
VDD
12
1
IN[P]
OUT[P]
3
10
IN[N]
1.2V
11
2
QLx111GRx
Lane
Extender
VDD
OUT[N]
VDD
1.2V
9
4
8
GND
7
CPB
6
CPA
GND
5
See Table 1 for
CP Boost Level
See setting
Table 6. for
setting CP
FIGURE 8. TYPICAL APPLICATION REFERENCE DESIGN
FIGURE 9. TYPICAL QLx111GRx APPLICATION SCHEMATIC
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October 26, 2009
QLx111GRx
ABOUT Q:ACTIVE®
Intersil has long realized that to enable the complex
server clusters of next generation datacenters, it is
critical to manage the signal integrity issues of electrical
interconnects. To address this, Intersil has developed its
groundbreaking Q:ACTIVE® product line. By integrating
its analog ICs inside cabling interconnects, Intersil is able
to achieve unsurpassed improvements in reach, power
consumption, latency, and cable gauge size as well as
increased airflow in tomorrow’s datacenters. This new
technology transforms passive cabling into intelligent
“roadways” that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing
cabling while reducing the need for thicker cables. This
significantly reduces cable weight and clutter, increases
airflow, and improves power consumption.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
9
FN6987.0
October 26, 2009
QLx111GRx
Package Outline Drawing
L16.3x3B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 4/07
4X 1.5
3.00
12X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
16
13
12
3.00
1
1 .70
4
9
(4X)
+ 0.10
- 0.15
0.15
5
8
0.10 M C A B
+ 0.07
TOP VIEW
4 16X 0.23 - 0.05
16X 0.40 ± 0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1
C
BASE PLANE
SEATING PLANE
0.08 C
( 2. 80 TYP )
(
SIDE VIEW
1. 70 )
( 12X 0 . 5 )
( 16X 0 . 23 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 16X 0 . 60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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FN6987.0
October 26, 2009
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