ESD5V3L1B-02LRH Data Sheet (1.6 MB, EN)

TVS Diode
Transient Voltage Suppressor Diodes
ESD5V3L1B Series
Bi-directional Low Capacitance ESD / Transient Protection Diode
ESD5V3L1B-02LRH
ESD5V3L1B-02LS
Data Sheet
Revision 1.1, 2012-10-15
Final
Power Management & Multimarket
Edition 2012-10-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
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ESD5V3L1B Series
Revision History Revision 1, 2011-08-04
Page or Item
Subjects (major changes since previous revision)
Revision 1.1, 2012-10-15
5
Table 2-1 updated
8/9
Figure 3-3 and Figure 3-4 updated
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of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2010-10-26
Final Data Sheet
3
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Bi-directional Low Capacitance ESD / Transient Protection Diode
1
Bi-directional Low Capacitance ESD / Transient Protection Diode
1.1
Features
•
•
•
•
•
ESD / transient protection of signal lines in low voltage applications according to:
– IEC61000-4-2 (ESD): ±20 kV (air / contact)
– IEC61000-4-4 (EFT): 40 A (5/50 ns)
Bi-directional, symmetrical working voltage up to VRWM = ±5.3 V
Low capacitance: CL = 5 pF (typical)
Low clamping voltage, low dynamic resistance down to: RDYN = 0.23 Ω (typical)
Pb-free (RoHS compliant) and halogen free package, very small form factor: 0.62 x 0.32 x 0.31 mm3
1.2
•
•
•
Application Examples
Keypad, touchpad, buttons, convenience keys
LCD displays, Camera, audio lines, mobile communication, Consumer products (E-Book, MP3, DVD, DSC...)
Notebooks tablets and desktop computers and their peripherals
1.3
Product Description
Pin 1
Pin 2
Pin 1 marking
(lasered)
Pin 1
TSLP-2
Pin 1
Pin 2
Pin 2
TSSLP-2
a) Pin configuration
b) Schematic diagram
P G-TS (S)LP -2_Dual_Diode_S erie_P inConf_and_S c hematic Diag. v s d
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1
Ordering Information
Type
Configuration
Marking code
ESD5V3L1B-02LRH PG-TSLP-2-17
1 line, bi-directional
4
ESD5V3L1B-02LS
1 line, bi-directional
C
Final Data Sheet
Package
PG-TSSLP-2-1
4
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Characteristics
2
Characteristics
Table 2-1
Maximum Ratings at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
VESD
–
–
20
kV
IPP
–
3
2.5
A
Peak pulse power (tp = 8/20 μs)
PPP
–
39
30
W
Operating temperature range
TOP
-40
–
125
°C
Storage temperature
1) VESD according to IEC61000-4-2
2) IPP according IEC61000-4-5
Tstg
-65
–
150
°C
ESD contact discharge
1)
Peak pulse current (tp = 8/20 μs)
2)
2)
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
2.1
Electrical Characteristics at TA = 25 °C, unless otherwise specified
!"#
Figure 2-1 Definitions of electrical characteristics
Final Data Sheet
5
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Characteristics
Table 2-2
DC Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
Reverse working voltage VRWM
-5.3
–
5.3
V
Breakdown voltage
VBR
6
–
10
V
IBR = 1 mA
Reverse current
IR
–
–
100
nA
VR = 5.3 V
Unit
Note /
Test Condition
Table 2-3
RF Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Min.
Typ.
Max.
Line capacitance
CL
4
–
7
pF
VR = 0 V, f = 1 MHz
Series inductance
LS
–
0.4
–
nH
PG-TSLP-2-17
–
0.2
–
Table 2-4
PG-TSSLP-2-1
ESD Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
1)
Clamping voltage
VCL
Values
Min.
Typ.
Max.
–
10.2
–
Unit
Note /
Test Condition
V
ITLP = 16 A,
from Pin 1 to Pin 2
–
13.2
–
ITLP = 30 A,
from Pin 1 to Pin 2
–
12.1
–
ITLP = 16 A,
from Pin 2 to Pin 1
–
17.2
–
ITLP = 30 A,
from Pin 2 to Pin 1
2)
Clamping voltage
–
8.5
–
IPP = 1 A,
from Pin 1 to Pin 2
–
9.8
–
IPP = 2.5 A,
from Pin 1 to Pin 2
–
8.5
–
IPP = 1 A,
from Pin 2 to Pin 1
–
10.4
–
IPP = 2.5 A,
from Pin 2 to Pin 1
Dynamic resistance
2)
RDYN
–
0.22
–
Ω
Pin 1 to Pin 2
–
0.37
–
Ω
Pin 2 to Pin 1
1) Please refer to Application Note AN210 [1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns
to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between IPP1 = 10 A and
IPP2 = 40 A.
2) IPP according to IEC61000-4-5 (tp = 8/20 μs)
Final Data Sheet
6
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
Typical Characteristics at TA = 25 °C, unless otherwise specified
3
10
-6
10
-7
IR [A]
10-8
10
-9
10-10
10
-11
10-12
-10
-8
-6
-4
-2
0
VR [V]
2
4
6
8
10
5
6
Figure 3-1 Reverse current: IR = f(VR)
7
6
CL [pF]
5
4
3
2
1
0
-6
-5
-4
-3
-2
-1
0
1
VR [V]
2
3
4
Figure 3-2 Line capacitance: CL = f(VR), f = 1MHz
Final Data Sheet
7
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
40
ESD5V3L1B-02xx
RDYN
20
30
15
20
10
10
5
0
0
-10
-5
-20
-10
Equivalent VIEC [kV]
ITLP [A]
RDYN = 0.23 Ω
RDYN = 0.36 Ω
-30
-15
-40
-20
-25
-20
-15
-10
-5
0
5
10
15
20
25
VTLP [V]
Figure 3-3 Clamping voltage (TLP): ITLP = f(VTLP) according ANSI/ESD STM5.5.1 - Electrostatic Discharge
Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 Ω,
tp = 100 ns, tr = 0.6 ns, ITLP and VTLP averaging window: t1 = ns to t2 = 60 ns, extraction of
dynamic resistance using squares fit to TLP characteristics between ITLP1 = 10 A and
ITLP2 = 40 mA. Please refer to Application Note AN210[1]
Final Data Sheet
8
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
4
ESD5V3L1B-02xx
RDYN
3
RDYN = 0.9 Ω
2
IPP [A]
1
0
-1
-2
RDYN = 1.4 Ω
-3
-4
-15
-10
-5
0
VCL [V]
5
10
15
Figure 3-4 Pulse current (IEC61000-4-5) versus clamping voltage: IPP = f(VCL)
Final Data Sheet
9
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
70
60
VCL [V]
50
VCL-max-peak = 45.0 [V]
40
VCL-30ns-peak = 10.7 [V]
30
20
10
0
-10
-100
0
100
200
300
400 500
tp [ns]
600
700
800
900
700
800
900
Figure 3-5 IEC61000-4-2: VCL = f(t), 8 kV positive pulse from pin 1 to pin 2
10
0
VCL [V]
-10
-20
-30
VCL-max-peak = -66.7 [V]
-40
VCL-30ns-peak = -9.7 [V]
-50
-60
-70
-100
0
100
200
300
400 500
tp [ns]
600
Figure 3-6 IEC61000-4-2: VCL = f(t), 8 kV negative pulse from pin 1 to pin 2
Final Data Sheet
10
Revision 1.1, 2012-10-15
ESD5V3L1B Series
VCL [V]
Typical Characteristics at TA = 25 °C, unless otherwise specified
110
100
90
80
70
60
50
40
30
20
10
0
-10
-20
-100
VCL-max-peak = 74.5 [V]
VCL-30ns-peak = 12.0 [V]
0
100
200
300
400 500
tp [ns]
600
700
800
900
700
800
900
VCL [V]
Figure 3-7 IEC61000-4-2: VCL = f(t), 15 kV positive pulse from pin 1 to pin 2
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-100
VCL-max-peak = -96.9 [V]
VCL-30ns-peak = -15.6 [V]
0
100
200
300
400 500
tp [ns]
600
Figure 3-8 IEC61000-4-2: VCL = f(t), 15 kV negative pulse from pin 1 to pin 2
Final Data Sheet
11
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Application Information
Application Information
Connector
4
Protected signal line
ESD
I/O sensitive
device
1
2
The protection diode should be placed very close to the location
where the ESD or other transients can occur to keep loops and
inductances as small as possible .
Pin 2 (or pin 1) should be connected directly to a ground plane on
the board .
A pplic ation_E S D5V3S 1B-02LS .v s d
Figure 4-1 Single line, bi-directional ESD / Transient protection
Final Data Sheet
12
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Ordering Information Scheme (Examples)
5
ESD
Ordering Information Scheme (Examples)
0P1
RF
- XX YY
Package
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
For Radio Frequency Applications
Line Capacitance CL in pF: (i.e.: 0P1 = 0.1pF)
ESD 5V3 U n U - XX YY
Package or Application
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
S = SOT363
U = SC74
XX = Application family:
LC = Low Clamp
HDMI
Uni- / Bi-directional or Rail to Rail protection
Number of protected lines (i.e.: 1 = 1 line; 4 = 4 lines)
Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF)
Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V)
Figure 5-1 Ordering information scheme
Final Data Sheet
13
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Package Information
6
Package Information
6.1
PG-TSLP-2-17 (mm) [2]
Top view
Bottom view
0.39 +0.01
-0.03
0.6 ±0.05
0.05 MAX.
1±0.05
0.65 ±0.05
2
0.25 ±0.035 1)
1
0.5 ±0.035 1)
Cathode
marking
1) Dimension applies to plated terminal
TSLP 2 7 PO V02
0.45
Copper
Solder mask
0.375
0.35
0.275
1
0.925
0.3
0.35
0.6
0.275
Figure 6-1 PG-TSLP-2-17: Package overview
Stencil apertures
TSLP-2-7-FP V01
Figure 6-2 PG-TSLP-2-17: Footprint
0.5
1.16
Orientation
marking
8
4
0.76
TSLP-2-7-TP V03
Figure 6-3 PG-TSLP-2-17: Packing
Type code
12
Cathode marking
Figure 6-4 PG-TSLP-2-17: Marking (example)
Final Data Sheet
14
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Package Information
PG-TSSLP-2-1 (mm) [2]
Top view
Bottom view
0.31 +0.01
-0.02
2
0.62 ±0.035
0.355 ±0.025
0.32 ±0.035
1
0.2 ±0.025 1)
6.2
0.26 ±0.025 1)
Cathode
marking
1) Dimension applies to plated terminal
TSSLP-2-1,-2-PO V05
Figure 6-5 PG-TSSLP-2-1: Package overview
0.19
0.24
Solder mask
0.19
0.57
0.14
0.62
Copper
0.19
0.27
0.24
0.32
Stencil apertures
TSSLP-2-1,-2-FP V02
Figure 6-6 PG-TSSLP-2-1: Footprint
a
Tape type
Ex Ey
Punched Tape
0.43 0.73
Embossed Tape 0.37 0.67
8
Ey
Cathode
marking
g
0.35
4
Deliveries can be both tape types (no selection possible).
Specification allows identical processing (pick & place) by users.
Ex
TSSLP-2-1,-2-TP V03
Figure 6-7 PG-TSSLP-2-1: Packing
Figure 6-8 PG-TSSLP-2-1: Marking (example)
Final Data Sheet
15
Revision 1.1, 2012-10-15
ESD5V3L1B Series
References
References
[1]
Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2]
Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
Final Data Sheet
16
Revision 1.1, 2012-10-15
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Published by Infineon Technologies AG
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