DATASHEET

HIP6601, HIP6603
CT
CT
RODU T PRODU
P
E
T
LE
MEN
OBSO EPLACE 03B
R
Data
Sheet
6
ED
IP 6
MEND P6601B, H
M
O
HI
REC
Synchronous-Rectified Buck MOSFET
Drivers
August 2004
Features
• Drives Two N-Channel MOSFETs
The HIP6601 and HIP6603 are high frequency, dual
MOSFET drivers specifically designed to drive two power
N-Channel MOSFETs in a synchronous-rectified buck
converter topology. These drivers combined with a HIP630x
Multi-Phase Buck PWM controller and Intersil UltraFETs™
form a complete core-voltage regulator solution for
advanced microprocessors.
The HIP6601 drives the lower gate in a synchronous-rectifier
bridge to 12V, while the upper gate can be independently
driven over a range from 5V to 12V. The HIP6603 drives
both upper and lower gates over a range of 5V to 12V. This
drive-voltage flexibility provides the advantage of optimizing
applications involving trade-offs between switching losses
and conduction losses.
The output drivers in the HIP6601 and HIP6603 have the
capacity to efficiently switch power MOSFETs at frequencies
up to 2MHz. Each driver is capable of driving a 3000pF load
with a 30ns propagation delay and 50ns transition time. Both
products implement bootstrapping on the upper gate with
only an external capacitor required. This reduces
implementation complexity and allows the use of higher
performance, cost effective, N-Channel MOSFETs. Adaptive
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
• Adaptive Shoot-Through Protection
• Internal Bootstrap Device
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 8 Lead SOIC Package
• Dual Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Bridge Shutdown
• Supply Under Voltage Protection
Applications
• Core Voltage Supplies for Intel Pentium® III, AMD®
Athlon™ Microprocessors
• High Frequency Low Profile DC-DC Converters
• High Current Low Voltage DC-DC Converters
Pinout
HIP6601CB/HIP6603CB
(SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG. NO.
HIP6601CB
0 to 85
8 Ld SOIC
M8.15
HIP6603CB
0 to 85
8 Ld SOIC
M8.15
FN4819.1
UGATE
1
8
PHASE
BOOT
2
7
PVCC
PWM
3
6
VCC
GND
4
5
LGATE
Block Diagram
PVCC
BOOT
UGATE
VCC
+5V
PHASE
SHOOTTHROUGH
PROTECTION
10K
† VCC FOR HIP6601
PVCC FOR HIP6603
†
PWM
CONTROL
LOGIC
LGATE
10K
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HIP6601, HIP6603
Typical Application
+12V
+5V
BOOT
VCC
PWM
PVCC
UGATE
DRIVE PHASE
HIP6601
LGATE
+12V
+5V
+5V
+VCORE
BOOT
VFB
COMP
PWM1
VSEN
PVCC
PWM
PWM2
PWM3
PGOOD
UGATE
VCC
VCC
DRIVE PHASE
HIP6601
LGATE
MAIN
CONTROL
HIP6301
VID
ISEN1
ISEN2
FS
+12V
ISEN3
GND
+5V
BOOT
PVCC
UGATE
VCC
PWM
DRIVE PHASE
HIP6601
LGATE
2
HIP6601, HIP6603
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (VBOOT - VPHASE) . . . . . . . . . . . . . . . . . . . . . . .15V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . .VPHASE - 5V(<400ns pulse width) to VBOOT + 0.3V
. . . . . . . . . . . VPHASE - 3.0V(>400ns pulse width) to VBOOT + 0.3V
LGATE . . . . . . . . . GND - 5V(<400ns pulse width) to VPVCC + 0.3V
. . . . . . . . . . . . . . GND - 3.0V(>400ns pulse width) to VPVCC + 0.3V
PHASE. . . . . . . . . . . . . . . . . .GND - 5V(<400ns pulse width) to 15V
. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V(>400ns pulse width) to 15V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V
Thermal Resistance
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 85oC
Maximum Operating Junction Temperature . . . . . . . . . . . . . 125oC
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HIP6601, fPWM = 1MHz, VPVCC = 12V
-
4.4
6.2
mA
HIP6603, fPWM = 1MHz, VPVCC = 12V
-
2.5
3.6
mA
HIP6601, fPWM = 1MHz, VPVCC = 12V
-
200
430
µA
HIP6603, fPWM = 1MHz, VPVCC = 12V
-
1.8
3.3
mA
VCC Rising Threshold
9.7
9.9
10.0
V
VCC Falling Threshold
9.0
9.1
9.2
V
-
500
-
µA
VCC SUPPLY CURRENT
Bias Supply Current
IVCC
Power Supply Current
IPVCC
POWER-ON RESET
PWM INPUT
Input Current
IPWM
VPWM = 0 or 5V (See Block Diagram)
PWM Rising Threshold
3.6
3.7
-
V
PWM Falling Threshold
-
1.3
1.4
V
UGATE Rise Time
TRUGATE
VPVCC = VVCC = 12V, 3nF load
-
20
-
ns
LGATE Rise Time
TRLGATE
VPVCC = VVCC = 12V, 3nF load
-
50
-
ns
UGATE Fall Time
TFUGATE
VPVCC = VVCC = 12V, 3nF load
-
20
-
ns
TFLGATE
LGATE Fall Time
VPVCC = VVCC = 12V, 3nF load
-
20
-
ns
UGATE Turn-Off Propagation Delay
TPDLUGATE VVCC = VPVCC = 12V, 3nF load
-
30
-
ns
LGATE Turn-Off Propagation Delay
TPDLLGATE VVCC = VPVCC = 12V, 3nF load
-
20
-
ns
1.5
-
3.6
V
-
230
-
ns
VVCC = 12V, VPVCC = 5V
-
2.5
3.0
Ω
VVCC = VPVCC = 12V
-
7.0
7.5
Ω
Shutdown Window
Shutdown Holdoff Time
OUTPUT
Upper Drive Source Impedance
RUGATE
Upper Drive Sink Impedance
RUGATE
Lower Drive Source Impedance
RLGATE
Lower Drive Sink Impedance
RLGATE
3
VVCC = 12V, VPVCC = 5V
-
2.3
2.8
Ω
VVCC = 12V, VPVCC = 12V
-
1.0
1.3
Ω
VVCC = 12V, VPVCC = 5V
-
4.5
5.0
Ω
VVCC = 12V, VPVCC = 12V
-
9.0
9.5
Ω
VVCC = VPVCC = 12V
-
1.5
2.9
Ω
HIP6601, HIP6603
Functional Pin Description
PVCC (Pin 7)
UGATE (Pin 1)
For the HIP6601, this pin supplies the upper gate drive bias.
Connect this pin from +12V down to +5V.
Upper gate drive output. Connect to gate of high-side power
N-Channel MOSFET.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFET. A resistor in series with boot
capacitor is required in certain applications to reduce ringing
on the BOOT pin. See the Internal Bootstrap Device section
under DESCRIPTION for guidance in choosing the
appropriate capacitor and resistor values.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
GND (Pin 4)
Bias and reference ground. All signals are referenced to this
node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low-side
power N-Channel MOSFET.
VCC (Pin 6)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND.
For the HIP6603, this pin supplies both the upper and lower
gate drive bias. Connect this pin to either +12V or +5V.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the
drain of the lower MOSFET. The PHASE voltage is
monitored for adaptive shoot-through protection. This pin
also provides a return path for the upper gate drive.
Description
Operation
Designed for versatility and speed, the HIP6601 and HIP6603
dual MOSFET drivers control both high-side and low-side NChannel FETs from one externally provided PWM signal.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [TPDLLGATE], the
lower gate begins to fall. Typical fall times [TFLGATE] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [TPDHUGATE] based
on how quickly the LGATE voltage drops below 1.0V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[TRUGATE] and the upper MOSFET turns on.
Timing Diagram
PWM
TPDHUGATE
TPDLUGATE
TRUGATE
TFUGATE
UGATE
LGATE
TRLGATE
TFLGATE
TPDLLGATE
TPDHLGATE
4
HIP6601, HIP6603
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [TPDLUGATE] is encountered before the
upper gate begins to fall [TFUGATE]. Again, the adaptive
shoot-through circuitry determines the lower gate delay time,
TPDHLGATE. The PHASE voltage is monitored and the lower
gate is allowed to rise after PHASE drops below 0.5V. The
lower gate then rises [TRLGATE], turning on the lower
MOSFET.
Three-State PWM Input
A unique feature of the HIP660X drivers is the addition of a
shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1.0V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 0.5V, the LGATE
is allowed to rise. PHASE continues to be monitored during
the lower gate rise time. If the PHASE voltage exceeds the
0.5V threshold during this period and remains high for longer
than 2µs, the LGATE transitions low. Both upper and lower
gates are then held low until the next rising edge of the PWM
signal.
Power-On Reset (POR) Function
During initial startup, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.9V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of
9.1V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.
Internal Bootstrap Device
The HIP6601 and HIP6603 drivers feature an internal
bootstrap device. Simply adding an external capacitor
across the BOOT and PHASE pins completes the bootstrap
circuit.
5
The bootstrap capacitor must have a maximum voltage
rating above VCC + 5V. The bootstrap capacitor can be
chosen from the following equation:
Q GATE
C BOOT ≥ -----------------------∆V BOOT
Where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The ∆VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose a HUF76139 is chosen as the
upper MOSFET. The gate charge, QGATE , from the data
sheet is 65nC for a 10V upper gate drive. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.325µF is required.
The next larger standard value capacitance is 0.33µF.
In applications which require down conversion from +12V or
higher and PVCC is connected to a +12V source, a boot
resistor in series with the boot capacitor is required. The
increased power density of these designs tend to lead to
increased ringing on the BOOT and PHASE nodes, due to
faster switching of larger currents across given circuit
parasitic elements. The addition of the boot resistor allows
for tuning of the circuit until the peak ringing on BOOT is
below 29V from BOOT to GND and 17V from BOOT to VCC.
A boot resistor value of 5Ω typically meets this criteria.
In some applications, a well tuned boot resistor reduces the
ringing on the BOOT pin, but the PHASE to GND peak
ringing exceeds 17V. A gate resistor placed in the UGATE
trace between the controller and upper MOSGET gate is
recommended to reduce the ringing on the PHASE node by
slowing down the upper MOSFET turn-on. A gate resistor
value between 2Ω to 10Ω typically reduces the PHASE to
GND peak ringing below 17V.
Gate Drive Voltage Versatility
The HIP6601 and HIP6603 provide the user total flexibility in
choosing the gate drive voltage. The HIP6601 lower gate
drive is fixed to VCC [+12V], but the upper drive rail can
range from 12V down to 5V depending on what voltage is
applied to PVCC. The HIP6603 ties the upper and lower
drive rails together. Simply applying a voltage from 5V up to
12V on PVCC will set both driver rail voltages.
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for
a desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level
will push the IC beyond the maximum recommended
operating junction temperature of 125oC. The maximum
allowable IC power dissipation for the SO8 package is
approximately 800mW. When designing the driver into an
application, it is recommended that the following calculation
HIP6601, HIP6603
be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated
by the driver is approximated as:
3
P = 1.05f sw  --- V U Q + V L Q  + I DDQ V
2
L
CC
U
Test Circuit
+5V OR +12V
+12V
where fsw is the switching frequency of the PWM signal. VU
and VL represent the upper and lower gate rail voltage. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IDDQ VCC product is the quiescent power
of the driver and is typically 30mW.
UGATE
Figure 2 shows the dissipation in the driver with 3nF loading
on both gates and each individually. Note the higher upper
gate power dissipation which is due to the bootstrap device
refresh cycle. Again PVCC and VCC are tied together and to
a +12V supply.
6
HIP660X
VCC
0.15µF
CU
PHASE
LGATE
PWM
100kΩ
2N7002
CL
GND
1000
PVCC = VCC = 12V
POWER (mW)
800
CU = CL = 3nF
600
400
CU = CL = 1nF
CU = CL = 2nF
200
CU = CL = 4nF
CU = CL = 5nF
0
500
1000
1500
2000
FREQUENCY (kHz)
where QLOSS is the total charge removed from the bootstrap
capacitor and provided to the upper gate load.
FIGURE 1. POWER DISSIPATION vs FREQUENCY
1000
PVCC = VCC = 12V
800
CU = CL = 3nF
POWER (mW)
In Figure 1, CU and CL values are the same and frequency
is varied from 50kHz to 2MHz. PVCC and VCC are tied
together to a +12V supply. Curves do exceed the 800mW
cutoff, but continuous operation above this point is not
recommended.
2N7002
0.15µF
1
1
V
= --- f SW Q V
P REFRESH = --- f SW Q
LOSS PVCC
U U
2
2
The 1.05 factor is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. CU and CL are the upper and lower gate load
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value is
0.01µF.
BOOT
PVCC
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
it’s body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the MOSFET.
0.01µF
600
CU = 3nF
CL = 3nF
400
200
0
500
1000
1500
2000
FREQUENCY (kHz)
FIGURE 2. 3nF LOADING PROFILE
The impact of loading on power dissipation is shown in
Figure 3. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 4 through 6
show the same characterization for the HIP6603 with a +5V
supply on PVCC and VCC tied to a +12V supply.
HIP6601, HIP6603
Since both upper and lower gate capacitance can vary, Figure 7 shows dissipation curves versus lower gate capacitance with
upper gate capacitance held constant at three different values. These curves apply only to the HIP6601 due to power supply
configuration.
600
400
PVCC = VCC = 12V
FREQUENCY = 800kHz
PVCC = 5V VCC = 12V
320
POWER (mW)
POWER (mW)
500
400
FREQUENCY = 500kHz
300
CU = CL = 5nF
CU = CL = 4nF
240
CU = CL = 3nF
160
200
CU = CL = 2nF
CU = CL = 1nF
80
FREQUENCY = 200kHz
100
1.0
2.0
3.0
4.0
0
5.0
500
GATE CAPACITANCE (CU = CL), (nF)
1000
FIGURE 3. POWER DISSIPATION vs LOADING
250
PVCC = 5V VCC = 12V
PVCC = 5V VCC = 12V
POWER (mW)
CU = 3nF
120
FREQUENCY = 800kHz
150
100
FREQUENCY = 500kHz
50
CL = 1nF
60
0
500
1000
FREQUENCY = 200kHz
1500
0
1.0
2000
FIGURE 5. 3nF LOADING PROFILE (HIP6603)
400
2.0
3.0
FIGURE 6. VARIABLE LOADING PROFILE (HIP6603)
CU = 5nF
PVCC = 5V VCC = 12V
350
300
CU = 3nF
200
CU = 1nF
150
100
1.0
2.0
3.0
4.0
5.0
FREQUENCY (kHz)
FIGURE 7. POWER DISSIPATION vs LOADING (HIP6601)
7
4.0
GATE CAPACITANCE (CU = CL), (nF)
FREQUENCY (kHz)
POWER (mW)
POWER (mW)
200
CU = CL = 3nF
180
2000
FIGURE 4. POWER DISSIPATION vs FREQUENCY (HIP6603)
300
240
1500
FREQUENCY (kHz)
5.0
HIP6601, HIP6603
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
INDEX
AREA
0.25(0.010) M
H
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
µα
A1
B
0.25(0.010) M
C
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
8
0o
8
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
8
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