DATASHEET

X5043, X5045
4K, 512 x 8 Bit
Data Sheet
September 23, 2015
FN8126.3
CPU Supervisor with 4K SPI EEPROM
Features
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
• Low VCC Detection and Reset Assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence.
- Reset signal valid to VCC = 1V
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor executes code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Four industry standard VTRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as 512 x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <10µA max standby current, watchdog off
• 4Kbits of EEPROM–1M Write Cycle Endurance
• Save Critical Data with Block Lock™ Memory
- Protect 1/4, 1/2, all or none of EEPROM array
• Built-in Inadvertent Write Protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time
- 16-byte page write mode
- 5ms write cycle time (typical)
• Available Packages
- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP
- 14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC
Copyright Intersil Americas LLC 2005, 2006, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5043, X5045
Typical Application
2.7-5.0V
VCC
uC
VCC
X5043
10K
RESET
CS
SCK
SI
SO
WP
RESET
SPI
VSS
VSS
Block Diagram
+
VCC
VTRIP
-
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
CS/WDI
SI
SO
SCK
WP
Command
Decode &
Control
Logic
Protect Logic
2
Watchdog
Timer
Reset
Status
Register
EEPROM
Array
4Kbits
RESET (X5043)
RESET (X5045)
X5043, X5045
STANDARD VTRIP LEVEL
SUFFIX
4.63V (+/-2.5%)
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 3. for
more details
For Custom Settings, call Intersil.
FN8126.3
September 23, 2015
X5043, X5045
Ordering Information
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
VCC
RANGE
VTRIP
RANGE
TEMP
RANGE
(°C)
PACKAGE
X5043P Z AL X5045PZ-4.5A (Note)
X5045P Z AL
4.5-5.5V
4.5-4.75
0 to 70
8 Ld PDIP (Pb-free)
X5043PIZ-4.5A (Note) X5043P Z AM X5045PIZ-4.5A (Note)
X5045P Z AM
PART NUMBER
RESET
(ACTIVE LOW)
X5043PZ-4.5A (Note)
PART
MARKING
-40 to 85
8 Ld PDIP (Pb-free)
0 to 70
8 Ld SOIC (Pb-free)
-40 to 85
8 Ld SOIC (Pb-free)
0 to 70
8 Ld MSOP (Pb-free)
-40 to 85
8 Ld MSOP (Pb-free)
0 to 70
8 Ld PDIP (Pb-free)
-40 to 85
8 Ld PDIP (Pb-free)
0 to 70
8 Ld SOIC (Pb-free)
-40 to 85
8 Ld SOIC (Pb-free)
0 to 70
8 Ld MSOP (Pb-free)
X5045M8IZ (Note) (No DBT
longer available,
recommended
replacement:
X5045S8IZ-2.7)
-40 to 85
8 Ld MSOP (Pb-free)
X5045V14IZ (Note) (No X5045V Z I
longer available or
supported)
-40 to 85
14 Ld TSSOP
(Pb-free)
X5043S8Z-4.5A (Note) X5043 Z AL
X5045S8Z-4.5A (Note) X5045 Z AL
X5043S8IZ-4.5A*
(Note)
X5043 Z AM
X5045S8IZ-4.5A*
(Note)
X5043M8Z-4.5A
(Note)
DBS
X5045M8Z-4.5A (Note) DCB
(No longer available,
recommended
replacement:
X5045S8Z-4.5A)
X5043M8IZ-4.5A
(Note)
DBM
X5045M8IZ-4.5A
(Note) (No longer
available,
recommended
replacement:
X5045S8IZ-4.5A)
DBX
X5043PZ (Note)
X5043P Z
X5045PZ (Note)
X5045P Z
X5043PIZ (Note)
X5043P Z I
X5045PIZ (Note)
X5045P Z I
X5043S8Z* (Note)
X5043 Z
X5045S8Z* (Note)
X5045 Z
X5043S8IZ* (Note)
X5043 Z I
X5045S8IZ* (Note)
X5045 Z I
X5043M8Z (Note)
DBN
X5045M8Z (Note) (No
longer available,
recommended
replacement:
X5045S8Z)
DBY
X5043M8IZ (Note)
DBJ
X5043V Z I
X5043V14IZ (Note)
(No longer available,
recommended
replacement:
X5043M8IZ)
3
X5045 Z AM
4.25-4.5
FN8126.3
September 23, 2015
X5043, X5045
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
VCC
RANGE
VTRIP
RANGE
TEMP
RANGE
(°C)
PACKAGE
X5043P Z AN X5045PZ-2.7A (Note)
X5045P Z AN
2.7-5.5V
2.85-3.0
0 to 70
8 Ld PDIP (Pb-free)
X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note)
X5045P Z AP
PART NUMBER
RESET
(ACTIVE LOW)
X5043PZ-2.7A (Note)
PART
MARKING
-40 to 85
8 Ld PDIP (Pb-free)
X5043S8Z-2.7A*
(Note)
X5043 Z AN
X5045S8Z-2.7A (Note) X5045 Z AN
0 to 70
8 Ld SOIC (Pb-free)
X5043S8IZ-2.7A*
(Note)
X5043 Z AP
X5045S8IZ-2.7A (Note) X5045 Z AP
-40 to 85
X5043M8Z-2.7A
(Note)
DBR
X5045M8Z-2.7A (Note) DCA
(No longer available,
recommended
replacement:
X5045S8Z-2.7A)
X5043M8IZ-2.7A*
(Note)
DBL
X5045M8IZ-2.7A
(Note) (No longer
available,
recommended
replacement:
X5045S8IZ-2.7A)
DBW
X5043PZ-2.7 (Note)
X5043P Z F
X5045PZ-2.7 (Note)
X5045P Z F
X5043PIZ-2.7 (Note)
X5043P Z G
X5045PIZ-2.7 (Note)
X5045P Z G
X5043S8Z-2.7* (Note) X5043 Z F
X5045S8Z-2.7* (Note)
X5045 Z F
X5043S8IZ-2.7* (Note) X5043 Z G
X5045S8IZ-2.7* (Note) X5045 Z G
X5043M8Z-2.7 (Note)
DBP
X5045M8Z-2.7 (Note)
(No longer available,
recommended
replacement:
X5045S8Z-2.7)
X5043M8IZ-2.7*
(Note)
DBK
X5045M8IZ-2.7 (Note)
(No longer available,
recommended
replacement:
X5045S8IZ-2.7)
2.55-2.7
8 Ld SOIC
(Pb-free)
0 to 70
8 Ld MSOP (Pb-free)
-40 to 85
8 Ld MSOP (Pb-free)
0 to 70
8 Ld PDIP (Pb-free)
-40 to 85
8 Ld PDIP (Pb-free)
0 to 70
8 Ld SOIC (Pb-free)
-40 to 85
8 Ld SOIC (Pb-free)
DBZ
0 to 70
8 Ld MSOP (Pb-free)
DBU
-40 to 85
8 Ld MSOP (Pb-free)
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4
FN8126.3
September 23, 2015
X5043, X5045
cycle has already been initiated, WP going low will have no
affect on a write.
Pin Configuration
8 Ld SOIC/PDIP/MSOP
CS/WDI
1
8
SO
2
WP
3
7
X5043, X5045
6
4
5
VSS
Reset (RESET, RESET)
VCC
RESET/RESET
SCK
SI
14 Ld TSSOP
CS
1
14
VCC
SO
2
13
RESET/RESET
NC
3
NC
4
12
X5043, X5045
11
NC
5
10
NC
WP
6
9
SCK
7
8
SI
NC
VSS
NC
Pin Descriptions
Serial Output (SO)
X5043, X5045, RESET/RESET is an active low/HIGH, open
drain output which goes active whenever VCC falls below the
minimum VCC sense level. It will remain active until VCC
rises above the minimum VCC sense level for 200ms.
RESET/RESET also goes active if the Watchdog timer is
enabled and CS remains either high or low longer than the
Watchdog time out period. A falling edge of CS will reset the
watchdog timer.
Pin Names
SYMBOL
DESCRIPTION
CS/WDI
Chip Select Input
SO
Serial Output
SI
Serial Input
SCK
Serial Clock Input
WP
Write Protect Input
VSS
Ground
VCC
Supply Voltage
RESET/RESET
Reset Output
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
Principles of Operation
Serial Input (SI)
Power-on Reset
SI is the serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input
and output. Opcodes, addresses, or data present on the SI
pin is latched on the rising edge of the clock input, while data
on the SO pin changes after the falling edge of the clock
input.
Chip Select (CS/WDI)
When CS is high, the X5043, X5045 are deselected and the
SO output pin is at high impedance and, unless an internal
write operation is underway, the X5043, X5045 will be in the
standby power mode. CS low enables the X5043, X5045,
placing it in the active power mode. It should be noted that
after power-up, a high to low transition on CS is required prior
to the start of any operation.
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043, X5045 are
disabled, but the part otherwise functions normally. When
WP is held high, all functions, including non volatile writes
operate normally. WP going low while CS is still low will
interrupt a write to the X5043, X5045. If the internal write
5
Application of power to the X5043, X5045 activate a Poweron Reset Circuit. This circuit pulls the RESET/RESET pin
active. RESET/RESET prevents the system microprocessor
from starting to operate with insufficient voltage or prior to
stabilization of the oscillator. When VCC exceeds the device
VTRIP value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin executing
code.
Low Voltage Monitoring
During operation, the X5043, X5045 monitor the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until VCC returns and exceeds VTRIP for 200ms.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent an active
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determines the watchdog timer period.
The microprocessor can change these watchdog bits. With
FN8126.3
September 23, 2015
X5043, X5045
address 03h. CS going HIGH on the write operation initiates
the VTRIP programming sequence. Bring WP LOW to
complete the operation.
no microprocessor action, the watchdog timer control bits
remain unchanged, even during total power failure.
VCC Threshold Reset Procedure
The X5043, X5045 are shipped with a standard VCC
threshold (VTRIP) voltage. This value will not change over
normal operating and storage conditions. However, in
applications where the standard VTRIP is not exactly right, or
if higher precision is needed in the VTRIP value, the X5043,
X5045 threshold may be adjusted. The procedure is
described below, and uses the application of a high voltage
control signal.
Note: This operation also writes 00h to array address 03h.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
VTRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it
is necessary to reset the trip point before setting the new
value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then send a WREN command,
followed by a write of Data 00h to address 01h. CS going
HIGH on the write operation initiates the VTRIP programming
sequence. Bring WP LOW to complete the operation.
Note: This operation also writes 00h to array address 01h.
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
VTRIP must be 4.0V, then the VTRIP must be reset. When
VTRIP is reset, the new VTRIP is something less than 1.7V.
This procedure must be used to set the voltage to a lower
value.
To reset the VTRIP voltage, apply at least 3V to the VCC pin
and tie the WP pin to the programming voltage VP. Then
send a WREN command, followed by a write of Data 00h to
VP = 15-18V
WP
CS
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
8 Bits
SI
06h
WREN
02h
Write
01h
Address
00h
Data
FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE.)
6
FN8126.3
September 23, 2015
X5043, X5045
VP = 15-18V
WP
CS
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
8 Bits
SI
06h
02h
WREN
Write
00h
03h
Address
Data
FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15–18V)
4.7K
VP
Adjust
VTRIP
Adj.
Run
1
2
3
4
8
X5043
X5045
µC
RESET
7
6
SCK
5
SI
SO
CS
FIGURE 3. SAMPLE VTRIP RESET CIRCUIT
7
FN8126.3
September 23, 2015
X5043, X5045
SPI Serial Memory
Execute
Reset VTRIP
Sequence
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The array
is internally organized as 512 x 8 bits. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
Set VCC = VCC Applied =
Desired VTRIP
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
VTRIP Programming
New VCC Applied
=
Old VCC Applied
- Error
Execute
Set VTRIP
Sequence
Apply 5V to VCC
New VCC Applied
=
Old VCC Applied
- Error
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC–10mV)
NO
RESET pin
goes active?
Measured VTRIP
-Desired VTRIP
The device contains an 8-bit instruction register that controls
the operation of the device. The instruction code is written to
the device via the SI input. There are two write operations
that requires only the instruction byte. There are two read
operations that use the instruction byte to initiate the output
of data. The remainder of the operations require an
instruction byte, an 8-bit address, then data bytes. All
instruction, address and data bits are clocked by the SCK
input. All instructions (Table 1), addresses and data are
transferred MSB first.
Clock and Data Timing
YES
Error -Emax
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
Error  Emax
-Emax < Error < Emax
Data input on the SI line is latched on the first rising edge of
SCK after CS goes LOW. Data is output on the SO line by
the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
where left off. CS must be LOW during the entire operation.
DONE
Emax = Maximum Desired Error
FIGURE 4. VTRIP PROGRAMMING SEQUENCE
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
INSTRUCTION FORMAT*
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
RSDR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register (Watchdog and Block Lock)
READ
0000 A8011
Read Data from Memory Array Beginning at Selected Address
WRITE
0000 A8010
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
Note:
OPERATION
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
8
FN8126.3
September 23, 2015
X5043, X5045
Write Enable Latch
The device contains a Write Enable Latch. This latch must be
SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will reset
the latch (Figure 5). This latch is automatically reset upon a
power-up condition and after the completion of a valid byte,
page, or status register write cycle. The latch is also reset if WP
is brought LOW.
When issuing a WREN, WRDI or RDSR commands, it is not
necessary to send a byte address or data.
1
2
3
4
5
6
7
ARRAY ADDRESSES PROTECTED
BL1
BL0
X5043, X5045
0
0
None
0
1
$180–$1FF
1
0
$100–$1FF
1
1
$000–$1FF
STATUS REGISTER BITS
SCK
SI
SO
STATUS REG BITS
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time-out Period. These nonvolatile bits are
programmed with the WRSR instruction.
CS
0
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.
High Impedance
FIGURE 5. WRITE ENABLE/DISABLE LATCH SEQUENCE
(WREN/WRDI INSTRUCTION)
Status Register
The Status Register contains four nonvolatile control bits and
two volatile status bits. The control bits set the operation of
the watchdog timer and the memory block lock protection.
The Status Register is formatted as shown in “Status
Register”.
WD1
WD0
WATCHDOG TIME OUT
(TYPICAL)
0
0
1.4 seconds
0
1
600 milliseconds
1
0
200 milliseconds
1
1
disabled (factory default)
Read Status Register
To read the Status Register, pull CS low to select the device,
then send the 8-bit RDSR instruction. Then the contents of
the Status Register are shifted out on the SO line, clocked by
CLK. Refer to the Read Status Register Sequence (Figure
6). The Status Register may be read at any time, even during
a Write Cycle.
Write Status Register
Status Register: (Default = 30H)
7
6
5
4
3
2
1
0
0
0
WD1
WD0
BL1
BL0
WEL
WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
Prior to any attempt to write data into the status register, the
“Write Enable” Latch (WEL) must be set by issuing the
WREN instruction (Figure 5). First pull CS LOW, then clock
the WREN instruction into the device and pull CS HIGH.
Then bring CS LOW again and enter the WRSR instruction
followed by 8 bits of data. These 8 bits of data correspond to
the contents of the status register. The operation ends with
CS going HIGH. If CS does not go HIGH between WREN
and WRSR, the WRSR instruction is ignored.
The Write Enable Latch (WEL) bit indicates the status of the
“write enable” latch. When WEL = 1, the latch is set and
when WEL = 0 the latch is reset. The WEL bit is a volatile,
read only bit. The WREN instruction sets the WEL bit and the
WRDS instruction resets the WEL bit.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
9
FN8126.3
September 23, 2015
X5043, X5045
TABLE 2. DEVICE PROTECT MATRIX
MEMORY BLOCK
STATUS REGISTER
WREN CMD
(WEL)
DEVICE PIN (WP)
PROTECTED AREA
UNPROTECTED AREA
(BL0, BL1, WD0, WD1)
0
x
Protected
Protected
Protected
x
0
Protected
Protected
Protected
1
1
Protected
Writable
Writable
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
6
SCK
Instruction
SI
Data Out
High Impedance
SO
5
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
6
SCK
Data Byte
Instruction
SI
5
4
3
2
1
0
High Impedance
SO
FIGURE 7. WRITE STATUS REGISTER SEQUENCE
10
FN8126.3
September 23, 2015
X5043, X5045
For the write operation (byte or page write) to be completed,
CS must be brought HIGH after bit 0 of the last complete
data byte to be written is clocked in. If it is brought HIGH at
any other time, the write operation will not be completed
(Figure 9).
Read Memory Array
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 8-bit address. Bit 3
of the READ instruction selects the upper or lower half of the
device. After the READ opcode and address are sent, the
data stored in the memory at the selected address is shifted
out on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address 000h allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS high. Refer to the Read EEPROM Array
Sequence (Figure 8).
While the write is in progress following a status register or
memory array write sequence, the Status Register may be
read to check the WIP bit. WIP is HIGH while the nonvolatile
write is in progress.
Write Memory Array
Prior to any attempt to write data into the memory array, the
“Write Enable” Latch (WEL) must be set by issuing the
WREN instruction (Figure 5). First pull CS LOW, then clock
the WREN instruction into the device and pull CS HIGH.
Then bring CS LOW again and enter the WRITE instruction
followed by the 8-bit address and then the data to be written.
Bit 3 of the WRITE instruction contains address bit A8, which
selects the upper or lower half of the array. If CS does not go
HIGH between WREN and WRITE, the WRITE instruction is
ignored.
The WRITE operation requires at least 16 clocks. CS must
go low and remain low for the duration of the operation. The
host may continue to write up to 16 bytes of data. The only
restriction is that the 16 bytes must reside within the same
page. A page address begins with address [x xxxx 0000] and
ends with [x xxxx 1111]. If the byte address reaches the last
byte on the page and the clock continues, the counter will roll
back to the first address of the page and overwrite any data
that has been previously written.
CS
0
1
2
3
4
5
6
7
8
9
7
6
10
12 13 14 15 16 17
18 19 20 21 22
SCK
Instruction
8 Bit Address
8
SI
5
3
2
1
0
9th Bit of Address
High Impedance
SO
Data Out
7
6
5
4
3
2
1
0
MSB
FIGURE 8. READ EEPROM ARRAY SEQUENCE
11
FN8126.3
September 23, 2015
X5043, X5045
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
8 Bit Address
5
3 2
12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
8
SI
1
0
7
6
5
Data Byte 1
4 3 2 1
0
9th Bit of Address
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
SI
7
6
Data Byte 2
5 4 3 2
1
0
7
6
Data Byte 3
5 4 3 2
1
0
6
5
Data Byte N
4 3 2 1
0
FIGURE 9. WRITE MEMORY SEQUENCE
Operational Notes
The device powers-up in the following state:
1. The device is in the low power standby state.
2. A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
3. SO pin is high impedance.
4. The Write Enable Latch is reset.
5. The Flag Bit is reset.
6. Reset Signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
• Block Protect bits provide additional level of write
protection for the memory array.
• The WP pin LOW blocks nonvolatile write operations.
12
FN8126.3
September 23, 2015
X5043, X5045
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with
respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300°C
Temperature:
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage:
-2.7, -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank, -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications
(Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS/COMMENTS
MIN
TYP(2)
MAX
UNIT
ICC1
VCC Write Current (Active)
SCK = 3.3MHz(3); SO, RESET, RESET = Open
3
mA
ICC2
VCC Read Current (Active)
SCK = 3.3MHz(3); SI = VSS, RESET, RESET =
Open
2
mA
ISB1
VCC Standby Current WDT = OFF CS = VCC, SCK, SI = VSS, VCC = 5.5V
10
µA
ISB2
VCC Standby Current WDT = ON
CS = VCC, SCK, SI = VSS, VCC = 5.5V
50
µA
ILI
Input Leakage Current
SCK, SI, WP = VSS to VCC
0.1
10
µA
ILO
0.1
10
µA
Output Leakage Current
SO, RESET, RESET = VSS to VCC
(1)
Input LOW Voltage
SCK, SI, WP, CS
-0.5
VCC x 0.3
V
(1)
Input HIGH Voltage
SCK, SI, WP, CS
VCC x 0.7
VCC + 0.5
V
VOL
Output LOW Voltage (SO)
IOL = 2mA @ VCC = 2.7V
IOL = 0.5mA @ VCC = 1.8V
0.4
V
VOH1
Output HIGH Voltage (SO)
VCC > 3.3V, IOH = –1.0mA
VCC - 0.8
V
VOH2
Output HIGH Voltage (SO)
2V < VCC  3.3V, IOH = –0.4mA
VCC - 0.4
V
VOH3
Output HIGH Voltage (SO)
VCC  2V, IOH = –0.25mA
VCC - 0.2
V
VOLRS
Output LOW Voltage (RESET,
RESET)
IOL = 1mA
VIL
VIH
Capacitance
COUT
CIN
(2)
V
TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
(2)
0.4
TEST
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
CONDITIONS
MAX
UNIT
VOUT = 0V
8
pF
VIN = 0V
6
pF
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
3. SCK frequency measured from VCC x 0.1/VCC x 0.9
13
FN8126.3
September 23, 2015
X5043, X5045
Equivalent A.C. Load Circuit at 5V VCC
5V
A.C. Test Conditions
5V
4.6k
1.64k
Output
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
RESET/RESET
1.64k
30pF
30pF
AC Electrical Specifications
(Over recommended operating conditions, unless otherwise specified)
2.7V–5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
0
3.3
MHz
DATA INPUT TIMING
fSCK
Clock Frequency
tCYC
Cycle Time
300
ns
tLEAD
CS Lead Time
150
ns
tLAG
CS Lag Time
150
ns
tWH
Clock HIGH Time
130
ns
tWL
Clock LOW Time
130
ns
tSU
Data Setup Time
30
ns
tH
Data Hold Time
30
ns
tRI(4)
Input Rise Time
2
µs
tFI(4)
Input Fall Time
2
µs
tCS
CS Deselect Time
tWC(5)
Write Cycle Time
100
ns
10
ms
MIN
MAX
UNIT
0
3.3
MHz
Data Output Timing
2.7–5.5V
SYMBOL
PARAMETER
fSCK
Clock Frequency
tDIS
Output Disable Time
150
ns
Output Valid from Clock Low
120
ns
tV
tHO
0
ns
Output Rise Time
50
ns
(4)
Output Fall Time
50
ns
tRO
tFO
Output Hold Time
(4)
NOTES:
4. This parameter is periodically sampled and not 100% tested.
5. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
14
FN8126.3
September 23, 2015
X5043, X5045
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
MSB Out
SO
SI
tHO
tWL
tDIS
MSB–1 Out
LSB Out
ADDR
LSB IN
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
MSB In
SI
SO
tRI
tFI
LSB In
High Impedance
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
15
FN8126.3
September 23, 2015
X5043, X5045
Power-Up and Power-Down Timing
VCC
VTRIP
VTRIP
tPURST
0 Volts
tPURST
tF
tR
tRPD
RESET (X5043)
RESET (X5045)
RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset Trip Point Voltage, (-4.5A)
Reset Trip Point Voltage, (Blank)
Reset Trip Point Voltage, (-2.7A)
Reset Trip Point Voltage, (-2.7)
4.5
4.25
2.85
2.55
4.62
4.38
2.92
2.62
4.75
4.5
3.0
2.7
V
tPURST
Power-up Reset Time Out
100
200
400
ms
500
ns
tRPD
tF
(6)
VCC Detect to Reset/Output
(6)
VCC Fall Time
10
µs
(6)
VCC Rise Time
0.1
ns
Reset Valid VCC
1
V
tR
VRVALID
NOTE:
6. This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
tCST
RESET
(5043)
tWDO
tRST
tWDO
tRST
RESET
(5045)
RESET/RESET Output Timing
SYMBOL
MIN
TYP
MAX
UNIT
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
OFF
200
600
1.4
300
800
2
ms
ms
sec
tCST
CS Pulse Width to Reset the Watchdog
400
tRST
Reset Time Out
100
tWDO
PARAMETER
16
ns
200
400
ms
FN8126.3
September 23, 2015
X5043, X5045
VTRIP Programming Timing Diagram
VCC
(VTRIP)
VTRIP
tTSU
tTHD
VP
WP
tVPS
tVPH
tPCS
CS
tVPO
tRP
SCK
SI
06h
02h
01h or
03h
VTRIP Programming Parameters
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tVPS
VTRIP Program Enable Voltage Setup time
1
µs
tVPH
VTRIP Program Enable Voltage Hold time
1
µs
tPCS
VTRIP Programming CS inactive time
1
µs
tTSU
VTRIP Setup time
1
µs
tTHD
VTRIP Hold (stable) time
10
ms
tWC
VTRIP Write Cycle Time
tVPO
VTRIP Program Enable Voltage Off time (Between successive adjustments)
0
µs
tRP
VTRIP Program Recovery Period (Between successive adjustments)
10
ms
VP
Programming Voltage
15
18
V
VTRIP Programmed Voltage Range
1.7
4.75
V
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
-25
+25
mV
VTRAN
Vtv
10
ms
VTRIP programming parameters are periodically sampled and are not 100% tested.
17
FN8126.3
September 23, 2015
X5043, X5045
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 23, 2015
FN8126.3
CHANGE
- Updated Ordering Information Table on page 3.
- Added Revision History.
- Added About Intersil Verbiage.
- Attached current POD.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN8126.3
September 23, 2015
X5043, X5045
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
19
FN8126.3
September 23, 2015
X5043, X5045
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
6. Dimensioning and tolerancing per ANSI Y14.5M-1994.
7. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
8. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
9. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
10. Terminal numbers are shown for reference only.
11. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
12. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
13. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
20
FN8126.3
September 23, 2015
X5043, X5045
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
21
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN8126.3
September 23, 2015
Similar pages