an1464

Description
Features
The ZL2005P is an innovative mixed-signal
power management and conversion IC that
combines a compact, efficient, synchronous buck
controller, adaptive drivers and key power and
thermal management functions in a single
package. The ZL2005PEV4 platform allows
evaluation of the features in the highlyconfigurable ZL2005P via the SMBus interface
using PMBus™ commands. The PMBus
command set is accessed by using Zilker Labs
evaluation software from a PC running Microsoft
Windows.
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•
•
•
•
•
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This evaluation board is meant to enable rapid
evaluation of the functionality of the ZL2005P in
a 10 Amp configuration. It has been optimized for
ease of evaluation across a wide range of input
and output conditions. This ZL2005PEV4
platform is provided as a reference design.
PMBus control via SMBus
Pin-strap selection for stand-alone operation
VOUT settable from +0.8V to +3.3V
RDS(ON) sensing
Convenient power connection
Onboard enable switch
Power good indicator
External temperature sensor
Target Specifications
This board has been designed for the following
conditions:
• VIN = 12V (Board range 4.5V to 13.2V)
• VOUT = 1.2V (Board range is 0.8V to 3.3V)
• IOUT = 0A - 10A
• FSW = 600kHz
• Output ripple: < 1%
• Dynamic response 3% (7.5A - 10A step load) @ 2.5V
• Temperature: 25°C
POWER IN
EN
ZL2005P
POWER OUT
Address
select
SMBus
Figure 1. Block Diagram
ZL2005PEV4
Functional Description
The ZL2005PEV4 provides the circuit required
to demonstrate the features of the ZL2005P in a
10Amp configuration. The ZL2005PEV4 has a
functionally-optimized layout that allows highlyefficient operation to its maximum output current
(See board picture in Figure 2). The input power
connection is provided through banana jack
terminals. Stand-alone operation of the ZL2005P
is achieved by factory installed pin-strap settings
and pre-configuration via PMBus commands.
PMBus protocol communication is performed
via a SMBus interface using an external USB to
SMBus adaptor. PMBus commands can be used
to modify the settings of the evaluation platform.
The ZL2005P SMBus address is set by the
jumper applied to J12. The SA1 pin is strapped
by an 11k resistor to ground. The J12 jumper
applies a different resistor to the SA0 pin to
achieve the indicated SMBus address settings.
Note that power must be cycled to set a new
address.
Refer to Figures 5 through 10 for component
placement and board layout. The board layout
has been optimized for two-sided component
area and thermal performance. For ZL2005P
circuit layout design considerations refer to
Zilker Labs Application Note AN10 (Reference
1 on page 21).
Figure 3 shows the ZL2005P circuit schematic.
The circuit consists of the ZL2005P power
conversion and management IC with its minimal
component count.
The input voltage connection is made at J1 which
is labeled VIN+/-. J2 is the output connector for
the output voltage, VOUT+/-. The VIN+/- and
VOUT+/- connections are rated to 10 A.
Figure 4 shows the ZL2005PEV4 interface
schematic. It contains various circuits that
interface to the ZL2005P’s circuit. The hardware
enable function is controlled by a toggle switch
(SW1) on the ZL2005PEV4 board. External
temperature is monitored from a 2N3904
transistor (Q3) connected to the XTEMP pin.
This external temperature is read with the
READ_TEMPERATURE_2 PMBus command.
The power good status is indicated by the PG
LED at D11. The PG LED indicates the correct
state of the power good signal when power is
applied to the ZL2005PEV4 board. The right
angle headers at opposite ends of the board (J10
and J11) are available to daisy chain multiple
boards. The SMBus and Enable signals are
passed between these connectors. All header pins
and switch positions are labeled on the
ZL2005PEV4 board’s silkscreen as shown in
Figure 5.
2
ZL2005PEV4DSr1.0
ZL2005PEV4
Operation
Stand-Alone Operation
The ZL2005PEV4 is easy to setup and operate. It
is configured, out of the box, to provide 1.2V at
10A from a 12V source. All input and output
connections should be made before turning the
input supply on.
When the input power supply is turned on, and
the enable switch is set to enable, the ZL2005P
will output the configured voltage. A load can
be applied to the output and the circuit can be
tested.
PMBus Operation
The ZL2005P utilizes the PMBus protocol. The
PMBus functionality can be accessed via USB
from a PC running the Zilker Labs Evaluation
software on a Windows-XP or Windows2000/NT operating system.
The enable switch can then be moved to
“ENABLE” and the ZL2005P can be tested.
Alternatively,
the
PMBus
commands
ON_OFF_CONFIG and OPERATION may be
used to manipulate the enable state.
Modifying the ZL2005PEV4
In order to design and test an alternative power
train circuit with the ZL2005P, choose a desired
operating conditions and power train. Enter the
selected power design parameters into Zilker
Labs’ PID calculation/simulation tool. The
results from the simulation tool provide
appropriate compensation values to configure the
new ZL2005P circuit. Apply the new power
train circuit to the evaluation board. Power the
board and invoke the evaluation software. Then
configure the new PID coefficients using the
“PMBus: Basic” command page or loading a
configuration text file with the new
compensation coefficients in it.
Install the Zilker Labs Evaluation software using
the CD included in the ZL2005PEV4 kit or
download
it
from
the
web
at
www.zilkerlabs.com.
For PMBus operation, connect a USB/SMBus
adaptor (J2) to the EVB (J10). Apply a USB
cable between the USB/SMBus adaptor and the
PC. Connect the output of the ZL2005PEV4 to
the desired load. Then connect an appropriate
power supply to the input. Place the enable
switch in “DISABLE” and turn on the power.
Invoke the ZL2005P interface software.
The Zilker Labs Evaluation software allows
modification of all ZL2005P PMBus parameters.
Manually configure the ZL2005P with the
interface software or load a predefined
configuration from a configuration text file.
Use the mouse-over pop-ups for help with the
Zilker Labs Evaluation software. Refer to the
Zilker Labs Application Note AN13 (Reference
3 on page 21) for PMBus details.
ZL2005PEV4DSr1.0
3
ZL2005PEV4
Quick Start Guide
Stand-alone Operation
1. Set enable switch (EN) to “DISABLE”
5. Connect supplied USB cable from computer
to EVB
a. Upon first time connection, the Found
New Hardware Wizard will appear.
Select “No, Not this time” and click
Next
2. Apply load to VOUT+/VOUT3. Connect power supply
(supply turned off)
to
VIN+/VIN-
4. Turn power supply on
b. Select “Install from a list or specific
location (Advanced)” and click Next
5. Set enable switch (EN) to “ENABLE”
c. Select “Search the best driver in these
locations” and only select the “Search
removable media” option, then click
Next
6. Test ZL2005P operation
PMBus Operation
1. Insert the Zilker Labs Eval Software CD
d. If you encounter a popup warning during
driver installation, click the “Continue
Anyway” button
2. Install the Eval Software by running
setup.exe from the ZL_Eval_Installer folder
on the CD.
3. Connect a USB/SMBus adaptor (J2) to the
EVB (J10)
4. Select a SMBus address with the jumper on
J12
6. Follow steps 1 - 4 under Stand-alone
Operation
7. Invoke “Zilker_Labs_Eval” from the Start
menu under Zilker Labs
8. Monitor and configure EVB using the
informative pages in the evaluation software
9. Test the ZL2005P operation
Connect input
voltage here
Connect load
here
Connect SMBus
controller here
PG LED
Connect other
eval boards here
EN Switch
Address select
Figure 2. ZL2005PEV4 Evaluation Board
4
ZL2005PEV4DSr1.0
VTRK
SCL
SDA
SALRT
SY NC
SA0
PG
EN
DGND
SY NC
SA0
SA1
ILIM0
ILIM1
SCL
SDA
SALRT
ZL2005P
34.8k
R5
VOUT max set
to 3.3V
16.2k
SMBus Address
set by J12
(page 2)
R4
11k
0.1uF
ISENA
ISENB
GL
BST
GH
SW
D1
BAT54
Optional
GND_SIGNAL
VSENSE
C12
0
4.7uF
R1
C4
0.1uF
4.7uF
27
26
25
24
23
22
21
20
19
C11
VDD
C3
V25
VDD
BST
GH
SW
PGND
GL
VR
ISENA
ISENB
R3
1
2
3
4
5
6
7
8
9
U1
Q3
2N3904
36
35
34
33
32
31
30
29
28
PG
DLY1
DLY0
EN
CFG
MGN
VADJ
XTEMP
V25
FC0
FC1
V0
V1
UVLO
SS0
SS1
VTRK
VSEN
10
11
12
13
14
15
16
17
18
SGND
37
1uF
C5
VIN
4
GND
Q2
BSZ035
C7
47uF
6.3V
C6
47uF
6.3V
22uF
22uF
L1
0.47uH
Q1
BSZ130
C2
C1
VIN
47uF
6.3V
C8
47uF
6.3V
C9
47uF
6.3V
C10
VOUT
VOUT
CON2_Banana
J2
VOUT
Size
A
Sheet
RSCH-ZL2005-016
Tuesday , October 23, 2007
Document Number
SCHEMATIC, 10A POINT OF LOAD
1
BUILDING A, SUITE 100
AUSTIN, TEXAS 78746
of
4 3 01 WE ST BA NK DRIVE
2
Rev
2.1
ZILKER LABS, INC. CONFIDENTIAL AND PROPRIETARY
Title
4
5
6
7
8
3
2
1
5
6
7
8
ZL2005PEV4DSr1.0
3
2
1
Temperature Measurement
place near low side FET
ZL2005PEV4
Schematics
Figure 3. ZL2005P Circuit
5
Addr
0x20
0x21
0x22
0x23
0x24
SDA
SALRT
SCL
19.6k
21.5k
23.7k
26.1k
28.7k
R17
R18
R19
R20
R21
SA0
SDA
SALRT
SCL
HEADER 5x2 PIN
2
4
6
8
10
R12
10.0K
J12
1
3
5
7
9
R11
10.0K
R14
470
PG
R15
10.0K
PG
VOUT
SY NC
VTRK
EN
VIN
1
R13
10.0K
VI
VO
U10
MIC2920A-3.3BS
C63
180uF
16V
C68
22uF
SW1
VIN
Enable
Monitor
Disable
CON2_Banana
J1
SW_SPDT
1
2
3
This regulator allows stand alone operation when not
using a USB dongle. When no USB dongle is applied,
this regualtor is supplying Vi2c current thus
efficiency measurements will be affected.
+Vi2c
+Vi2c
Sheet
RSCH-ZL2005-016
Tuesday , June 12, 2007
Document Number
SCHEMATIC, Interf ace
2
BUILDING A, SUITE 100
AUSTIN, TEXAS 78746
of
4301 WEST B ANK DRIV E
2
Rev
2
ZILKER LABS, INC. CONFIDENTIAL AND PROPRIETARY
3
D12
BAT54
D10
STPS20L45CG
D-2PAK
Enable on PG_0
Enable Open
Enable on Bus
Backside
C67
22uF
JP1
1
2
3
4
The ref erence designs contained in this document are f or ref erence and example purpose only .
THE REFERENCE DESIGNS ARE PROVIDED "AS IS" AND "WITH ALL FAULTS" AND ZILKER
Title
LABS DISCLAMES ALL WARRANTIES, WHETHER DIRECT, INDIRECT, CONSEQUENTIAL
(INCLUDING LOSS OF PROFITS), OR OTHERWISE, RESULTING FROM THE REFERENCE
DESIGNS OR ANY USE THEREOF.
Size
Any use of such ref erence designs is at y our own risk and y ou agree to indemnif y Zilker Labs
A
f or any damages resulting f rom such use.
Q10
2N7002/SOT
GRN
D11
+Vi2c
HEADER 5X2
To Next Rail
J11
2
1
4
3
EN_BUS
6
5
SY NC
8
7
10
9
HEADER 5X2
From Previous Rail
J10
2
1
4
3
EN_BUS
6
5
8
7
PG_0
10
9
G
2
R10
10.0K
+Vi2c
G
6
4
Place pullups near J11
ZL2005PEV4
Figure 4. ZL2005P Interface
ZL2005PEV4DSr1.0
ZL2005PEV4
Board Layout
Figure 5. PCB – Silk Screen Top
ZL2005PEV4DSr1.0
7
ZL2005PEV4
Figure 6. PCB – Top Layer
8
ZL2005PEV4DSr1.0
ZL2005PEV4
Figure 7. PCB – Inner Layer 1
ZL2005PEV4DSr1.0
9
ZL2005PEV4
Figure 8. PCB – Inner Layer 2
10
ZL2005PEV4DSr1.0
ZL2005PEV4
Figure 9. PCB – Bottom Layer (Top view)
ZL2005PEV4DSr1.0
11
ZL2005PEV4
Figure 10. PCB – Silk Screen Bottom (Top View - reversed)
12
ZL2005PEV4DSr1.0
ZL2005PEV4
Bill Of Materials
Item Quan Reference
1 4 C1,C2,C67,C68
2 2 C3,C4
3 1 C5
4 5 C6,C7,C8,C9,C10
5 2 C11,C12
6 1 C63
7 2 D1,D12
8 1 D10
9 1 D11
10 1 JP1
11 2 J1,J2
12 1 J10
13 1 J11
14 1 J12
15 1 L1
16 1 Q1
17 1 Q2
18 1 Q3
19 1 Q10
20 1 R1
21 1 R3
22 1 R4
23 1 R5
24 5 R10,R11,R12,R13,R15
25 1 R14
26 1 R17
27 1 R18
28 1 R19
29 1 R20
30 1 R21
31 1 SW1
32 1 U1
33 1 U10
34 1
35 2 J12-Addr22,JP1-ENbus
36 4
37 4
38 4 J1_2ea,J2_2ea
Value
Tolerance Rating
22uF
16V
4.7uF
6.3V
1uF
25V
47uF
20% 6.3V
0.1uF
10% 50V
180uF
16V
BAT54
30V
STPS20L45CG
GRN
2V
4 PIN
CON2_Banana
HEADER 5X2
HEADER 5X2
HEADER 5x2 PIN
0.47uH
17.5A
BSZ130
BSZ035
2N3904
40V
2N7002/SOT
60V
0
11k
1%
16.2k
1%
34.8k
1%
10.0K
1%
470
1%
19.6k
1%
21.5k
1%
23.7k
1%
26.1k
1%
28.7k
1%
SW_SPDT
ZL2005P
MIC2920A-3.3BS
PCB
CONN JUMPER SHORTING GOLD
SCREW MACHINE PHILLIPS 4-40X1/4
STANDOFF RD 4-40THR .750" ALUM
CAP_MOLDED.25ID_BLK
Type
X5R
X5R
X5R
X5R
X7R
ELECT POLY
Schottky
Powder
NPN
N-CH
PCB Footprint
SM1210
SM0603
SM0603
SM1206_A_REV1
SM0603
SM_CAP_8.3X8.3_PXA
SOD523
D-2PAK
led2-45x51
SIP4/100
JACK_F_NI_2P.750SP_.175PLUG
HDR10DUAL100X100
HDRF5DUALRA100X100
HDR10DUAL100X100
IHLP_2525BD_REV1
PP1212SP
PP1212SP
SOT-23
SOT-23
SM0603
SM0402
SM0402
SM0402
SM0402
SM0402
SM0402
SM0402
SM0402
SM0402
SM0402
SW_TOG_ULTRAMIN_SPDT
MLF36
SOT223_1234_FLD
CAP_MOLDED.25ID
Manufacturer
MURATA
Panasonic - ECG
TAIYO YUDEN
TDK
MURATA
United Chemi-Con
ON Semiconductor
STMicro
CHICAGO MINIATURE
SAMTEC
Emerson
SAMTEC
SAMTEC
SAMTEC
Vishay
INFINEON
INFINEON
ON SEMI
ON SEMI
PANASONIC-ECG
PANASONIC-ECG
PANASONIC-ECG
PANASONIC-ECG
VENKEL
Rohm
VISHAY
VISHAY
VISHAY
VENKEL
VISHAY
NKK
Zilker Labs
Micrel
Part Number
GRM32ER61C226KE20L
ECJ-1VB0J475M
TMK107BJ105KA-T
C3216X5R0J476M
GRM39X7R104K050AD
APXA160ARA181MHC0G
BAT54XV2T1OS
STPS20L45CG
CMD17-21VGC
TSW-104-07-T-S
108-0740-001
TSW-105-08-T-D-RA
SSQ-105-02-T-D-RA
TSW-105-07-T-D
IHLP2525CZERR47M01
BSZ130N03LS
BSZ035N03LS
MMBT3904LT3
2N7002LT1
ERJ-3GEY0R00V
ERJ-2RKF1102X
ERJ-2RKF1622X
ERJ-2RKF3482X
CR0402-16W-1002FT
MCR01MZPF4700
CRCW040219K6FKED
CRCW040221K5FKED
CRCW040223K7FKED
CR0402-16W-2612FT
CRCW040228K7FKED
G-13AP-RO
ZL2005P
MIC2920A-3.3WS
MPWB-ZL2005-016
SULLINS
SSC02SYAN
BUILDING FASTENERS
PMS 440 0025 PH
KEYSTONE ELECTRONICS 3481
CAPLUGS
VC-234-8
Table 1. ZL2005PEV4 Rev. 2 Bill of Materials
ZL2005PEV4DSr1.0
13
ZL2005PEV4
ZL2005P Characterization Data
The following data was acquired using a ZL2005PEV4 rev 2 evaluation board.
Test 1: Efficiency
Efficiency data was collected for several output voltages for input voltages of 5 V and 12 V. Note that this
data is for informational use only, as the board is optimized for 12 V input and 1.2 V output operation.
Efficiency VIN=5V
100
95
90
Eff in %
85
80
75
70
65
60
0
1
2
3
4
5
6
7
8
9
10
IOUT (Amp)
Vout=1V
Vout=1.2V
Vout=1.5V
Vout=1.8V
Vout=2.5V
Vout=3.3V
Figure 11. Efficiency Test, VIN = 12 V. fSW = 600 kHz
14
ZL2005PEV4DSr1.0
ZL2005PEV4
Efficiency VIN=12V
100
95
90
Eff in %
85
80
75
70
65
60
0
1
2
3
4
5
6
7
8
9
10
IOUT (Amp)
Vout=1V
Vout=1.2V
Vout=1.5V
Vout=1.8V
Vout=2.5V
Vout=3.3V
Figure 12. Efficiency Test, VIN = 5 V, fSW = 600 kHz
ZL2005PEV4DSr1.0
15
ZL2005PEV4
Test 2: Ramp-Up/Ramp-Down Characteristics
Ramp-up and ramp-down data was acquired based on a nominal output voltage of 1.5 V and a preset
ramp-up and ramp-down period of 10 ms.
Ramp up 10ms
VOUT=1.5V
2
1.75
VOUT in V
1.5
1.25
1
0.75
0.5
0.25
0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
Time in ms
VOUT in Volt
Figure 13. Ramp-Up Characteristic Test Results, Vin = 12 V, Vout = 1.5 V, Iout = 1 A
16
ZL2005PEV4DSr1.0
ZL2005PEV4
Ramp Down 10ms
VOUT=1.5V
2
1.75
VOUT in V
1.5
1.25
1
0.75
0.5
0.25
0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
Time in ms
Ramp Down Amplitude (Volts)
Figure 14. Ramp-Down Characteristic Test Results, Vin = 12 V, Vout = 1.5 V, Iout = 1 A
ZL2005PEV4DSr1.0
17
ZL2005PEV4
Test 3: Dynamic Load Response
For the dynamic load response test, the circuit was set to a nominal output voltage of 2.5 V and an input
voltage of 6 V. A 7.5 A to 10 A load step (rate of 2.5 A/µs) was applied and then released, and the
deviation from nominal output was captured in the charts below.
Transient L to H
0.03
0.02
Vout in Volt
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
0.0E+00
5.0E-05
1.0E-04
1.5E-04
2.0E-04
2.5E-04
3.0E-04
3.5E-04
4.0E-04
3.0E-04
3.5E-04
4.0E-04
Time in Sec
Dynamic Load Response (Volts)
Figure 15. Dynamic Load Test Results
Vout in Volt
Transient H to L
0.06
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
0.0E+00
5.0E-05
1.0E-04
1.5E-04
2.0E-04
2.5E-04
Time in Sec
VOUT in V
Figure 16. Dynamic Unload Test Results
18
ZL2005PEV4DSr1.0
ZL2005PEV4
Default Configuration Text
The following PMBus commands have been loaded and stored into the Default Store of the ZL2005P
device. Each PMBus can be accessed with the Zilker Labs Evaluation software. The # symbol is used for
a comment line.
# Configuration file for ZL2005PEV4, Rev 2
#syntax:
#PMBus Command <tab> Value
#Erase default and user store
RESTORE_FACTORY
STORE_DEFAULT_ALL
MFR_ID
ZilkerLabs
MFR_MODEL
ZL2005PEV4
MFR_REVISION
Rev_1.4
MFR_LOCATION
Austin_TX
VIN_OV_FAULT_LIMIT
13.5
VIN_OV_WARN_LIMIT
13.2
VIN_UV_FAULT_LIMIT
4.2
VIN_UV_WARN_LIMIT
4.5
VOUT_COMMAND
1.2
#V
FREQUENCY_SWITCH
600
#kHz
POWER_GOOD_DELAY
1
TON_DELAY
15
TON_RISE
5
TOFF_DELAY
15
TOFF_FALL
5
SEQUENCE
0x0000
#Use Rdson current sense method with internal temp sensor
MFR_CONFIG
0x7981
USER_CONFIG
0x0000
PID_TAPS
A=4163.75, B=-7518.75, C=3513.44
IOUT_OC_FAULT_LIMIT
20.
IOUT_AVG_OC_FAULT_LIMIT
15.
IOUT_UC_FAULT_LIMIT
-10.
IOUT_AVG_UC_FAULT_LIMIT
-8.
#low FET not enabled for output OV, output OV and UV count to 2
OVUV_CONFIG
ZL2005PEV4DSr1.0
0x01
19
ZL2005PEV4
IOUT_SCALE
3.65
IOUT_CAL_OFFSET
-0.7
#Set temperature compensation at 4000ppm/ C internal temp sensor
TEMPCO_CONFIG
0x28
#NLR_CONFIG Enable,2.5%,No Outer,3.0%,1,7,0
NLR_CONFIG
0xc530
#VOUT_DROOP
2
#mV/A
STORE_DEFAULT_ALL
RESTORE_DEFAULT_ALL
20
ZL2005PEV4DSr1.0
ZL2005PEV4
References
[1]
AN10 – ZL2005 Thermal and Layout
Guidelines for the ZL2005, Zilker Labs,
Inc., 2007.
[2]
ZL2005P Data Sheet, Zilker Labs, Inc.,
2007.
[3]
AN13 – ZL2005 and PMBus™, Zilker
Labs, Inc., 2007.
Revision History
Date
1-29-2008
ZL2005PEV4DSr1.0
Rev.
#
1.0 Initial Release
21
ZL2005PEV4
Zilker Labs, Inc.
4301 Westbank Drive
Building A-100
Austin, TX 78746
Tel: 512-382-8300
Fax: 512-382-8329
www.zilkerlabs.com
© 2008, Zilker Labs, Inc. All rights reserved. Zilker Labs, Digital-DC and the Zilker Labs Logo are trademarks
of Zilker Labs, Inc. All other products or brand names mentioned herein are trademarks of their respective holders.
Pricing, specifications and availability are subject to change without notice. Please see www.zilkerlabs.com for
updated information. This product is not intended for use in connection with any high-risk activity, including
without limitation, air travel, life critical medical operations, nuclear facilities or equipment, or the like.
The reference designs contained in this document are for reference and example purposes only. THE REFERENCE DESIGNS ARE PROVIDED "AS IS" AND "WITH ALL FAULTS" AND ZILKER LABS DISCLAIMS
ALL WARRANTIES, WHETHER EXPRESS OR IMPLIED. ZILKER LABS SHALL NOT BE LIABLE FOR
ANY DAMAGES, WHETHER DIRECT, INDIRECT, CONSEQUENTIAL (INCLUDING LOSS OF PROFITS), OR OTHERWISE, RESULTING FROM THE REFERENCE DESIGNS OR ANY USE THEREOF. Any
use of such reference designs is at your own risk and you agree to indemnify Zilker Labs for any damages resulting from such use.
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