DATASHEET

HM-65162/883
TM
2kx8 Asynchronous
CMOS Static RAM
March 1997
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HM-65162/883 is a CMOS 2048 x 8 Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle time and ease of use. The pinout is the
JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which
allows easy memory board layouts flexible to accommodate
a variety of industry standard PROMs, RAMs, ROMs and
EPROMs. The HM-65162/883 is ideally suited for use in
microprocessor based systems with its 8-bit word length
organization. The convenient output enable also simplifies
the bus interface by allowing the data outputs to be controlled independent of the chip enable. Gated inputs lower
operating current and also eliminate the need for pull-up or
pull-down resistors.
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . . 50μA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20μA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout (2716, 6116 Type)
• No Clocks or Strobes Required
• Wide Temperature Range . . . . . . . . . . -55oC to +125oC
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
Ordering Information
70ns/20μA
90ns/40μA
HM1-65162B/883
HM1-65162/883
HM4-65162B/883
HM4-65162/883
90ns/300μA
TEMP. RANGE
-55oC to 125oC
-55oC to 125oC
HM1-65162C/883
-
PACKAGE
PKG. NO.
CERDIP
F24.6
CLCC
J32.A
Pinouts
NC
NC
NC
VCC
NC
NC
HM-65162/883 (CLCC)
TOP VIEW
A7
HM-65162/883 (CERDIP)
TOP VIEW
4
3
2
1
32
31
30
PIN
A7
1
24 VCC
A6
2
23 A8
A6
5
29 A8
A5
3
22 A9
A5
6
A0 - A10
4
21 W
28 A9
A4
A3
5
20 G
A4
7
27 NC
E
A2
6
19 A10
A3
8
26 W
9
25 G
DQ0
9
16 DQ6
A0 11
23 E
DQ1 10
15 DQ5
NC 12
22 DQ7
DQ2 11
14 DQ4
13
21 DQ6
GND 12
13 DQ3
14
15 16
17
18
19
20
GND
DQ0
DQ5
24 A10
DQ4
A1 10
NC
17 DQ7
DQ3
18 E
8
DQ2
7
A0
DQ1
A1
A2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
188
NC
DESCRIPTION
No Connect
Address Input
Chip Enable/Power Down
VSS/GND
Ground
DQ0 - DQ7
Data In/Data Out
VCC
Power (+5V)
W
Write Enable
G
Output Enable
FN3001.1
HM-65162/883
Functional Diagram
A1
A
A2
A3
A4
A5
A6
A7
ROW
ADDRESS
BUFFER
7
A
ROW
DECODER
128
128 X 128
MEMORY ARRAY
7
1 OF 8
128
E
COLUMN DECODER
AND DATA
INPUT / OUTPUT (X8)
4
G
A
4
A
COLUMN
ADDRESS BUFFER
W
A0
189
A8 A9 A10
8
DQ0
THRU
DQ7
HM-65162/883
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . .1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
CERDIP Package . . . . . . . . . . . . . . . . 48oC/W
8oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W
12oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Chip Enable High/Low Time . . . . . . . . . . . . . . . . . . . . . . . 40ns (Min)
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to VCC
Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. 65162/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
(NOTE 1)
CONDITIONS
SYMBOL
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
2.4
-
V
VOH1
VCC = 4.5V, IO = -1.0mA
1, 2, 3
-55oC ≤ TA ≤ +125oC
Low Level Output
Voltage
VOL
VCC = 4.5V, IO = 4.0mA
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
0.4
V
High Impedance
Output Leakage
Current
IIOZ
VCC = 5.5V, G = 2.2V, or
E = 2.2V, VI/O = GND or VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-1.0
1.0
μA
VCC = 5.5V,
VI = GND or VCC
1, 2, 3
-55oC ≤ TA ≤ +125oC
-1.0
1.0
μA
HM-65162B/883, IO = 0mA,
VCC = 5.5V, E = VCC -0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
50
μA
HM-65162/883, IO = 0mA,
VCC = 5.5V, E = VCC - 0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
100
μA
HM-65162C/883, IO = 0mA,
VCC = 5.5V, E = VCC - 0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
900
μA
High Level Output Voltage
Input Leakage
Current
Standby Supply
Current
II
ICCSB1
Standby Supply
Current
ICCSB
VCC = 5.5V, IO = 0mA,
E = 2.2V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
8
mA
Operating Supply
Current
ICCOP
VCC = 5.5V, G = 5.5V,
(Note 2), f = 1MHz, E = 0.8V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
70
mA
Enable Supply
Current
ICCEN
VCC = 5.5V, IO = 0mA,
E = 0.8V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
70
mA
Data Retention
Supply Current
ICCDR
HM-65162B/883, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
20
μA
HM-65162/883, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
40
μA
HM-65162C/883, IO = 0mA,
VCC = 2.0V, E = VCC - 0.3V
1, 2, 3
-55oC ≤ TA ≤ +125oC
-
300
μA
7, 8A, 8B
-55oC ≤ TA ≤ +125oC
-
-
-
Functional Test
FT
VCC = 4.5V (Note 3)
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1
TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
190
HM-65162/883
TABLE 2. HM-65162/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested.
LIMITS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUBGROUPS
TEMPERATURE
HM-65162B
/883
HM-65162
/883
HM-65162C
/883
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Read/Write/
Cycle Time
(1) TAVAX
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
70
-
90
-
90
-
ns
Address
Access Time
(2) TAVQV
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
70
-
90
-
90
ns
Chip Enable
Access Time
(3) TELQV
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
70
-
90
-
90
ns
Output Enable
Access Time
(5) TGLQV
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
-
50
-
65
-
65
ns
Chip Selection
to End of Write
(11) TELWH
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
45
-
55
-
55
-
ns
Address Setup
Time
(12) TAVWL
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
10
-
10
-
10
-
ns
Write Enable
Pulse Write
(13) TWLWH
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
40
-
55
-
55
-
ns
Write Enable
Read Setup
Time
(14) TWHAX
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
10
-
10
-
10
-
ns
Data Setup
Time
(17) TDVWH
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
30
-
30
-
30
-
ns
Data Hold Time
(18) TWHDX
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
10
-
15
-
15
-
ns
Write Enable
Pulse Setup
Time
(20) TWLEH
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
40
-
55
-
55
-
ns
Chip Enable
Data Setup
Time
(21) TDVEH
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
30
-
30
-
30
-
ns
Address Valid
to End of Write
(22) TAVWH
VCC = 4.5V
and 5.5V
9, 10, 11
-55oC ≤ TA ≤ +125oC
50
-
65
-
65
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL
gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
191
HM-65162/883
TABLE 3. HM-65162/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC
LIMITS
PARAMETER
SYMBOL
Input
Capacitance
CIN
I/O
Capacitance
CI/O
HM65162B/883
HM65162/883
HM65162C/883
NOTES
TEMPERATURE
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VCC = Open,
F = 1MHz, All
Measurements
Referenced To
Device Ground
1, 2
+25oC
-
10
-
10
-
10
pF
1, 3
+25oC
-
8
-
8
-
8
pF
VCC = Open,
F = 1MHz, All
Measurements
Referenced To
Device Ground
1, 2
+25oC
-
12
-
12
-
12
pF
1, 3
+25oC
-
10
-
10
-
10
pF
CONDITIONS
Chip Enable to
Output ON
(4) TELQX
VCC = 4.5V and
5.5V
1
-55oC ≤ TA ≤
+125oC
5
-
0
-
5
-
ns
Output Enable
to Output ON
(6) TGLQX
VCC = 4.5V and
5.5V
1
-55oC ≤ TA ≤
+125oC
5
-
5
-
5
-
ns
Chip Enable
High to Output
In High Z
(7) TEHQZ
VCC = 4.5V and
5.5V
1
-55oC ≤ TA ≤
+125oC
-
35
-
50
-
50
ns
Output Disable
to Output in
High Z
(8) TGHQZ
VCC = 4.5V and
5.5V
1
-55oC ≤ TA ≤
+125oC
-
35
-
40
-
40
ns
Output Hold
from Address
Change
(9) TAVQX
VCC = 4.5V and
5.5V
1
-55oC ≤ TA ≤
+125oC
5
-
5
-
5
-
ns
Write Enable to
Output in High Z
(16) TWLQZ
VCC = 4.5V and
5.5V
1
-55oC ≤ TA ≤
+125oC
-
40
-
50
-
50
ns
Write Enable
High to Output
ON
(19) TWHQX
VCC = 4.5V and
5.5V
1
-55oC ≤ TA ≤
+125oC
0
-
0
-
0
-
ns
VCC = 4.5V,
IO = -100μA
1
-55oC ≤ TA ≤
+125oC
VCC
0.4V
-
VCC
0.4V
-
VCC
0.4V
-
V
Output High
Voltage
VOH2
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only.
3. Applies to LCC device types only.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 7, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
192
HM-65162/883
Timing Waveforms
(1) TAVAX
(2) TAVQV
ADDRESS
(8) TGHQZ
G
(5) TGLQV
E
(7) TEHQZ
(6) TGLQX
(3) TELQV
(9) TAVQX
Q
(4) TELQX
NOTE:
1. W is High for a Read Cycle.
FIGURE 1. READ CYCLE
Addresses must remain stable for the duration of the read
cycle. To read, G and E must be ≤ VIL and W ≥ VIH. The
output buffers can be controlled independently by G while E
is low. To execute consecutive read cycles, E may be tied
low continuously until all desired locations are accessed.
When E is low, addresses must be driven by stable logic
levels and must not be in the high impedance state.
(10) TAVAX
ADDRESS
(14) TWHAX
(11) TELWH
E
(12) TAVWL
(13) TWLWH
(20) TWLEH
W
(16) TWLQZ
(19) TWHQX
Q
(21)
TDVEH
D
(17) TDVWH
(18) TWHDX
(22) TAVWH
NOTE:
1. G is Low throughout Write Cycle.
FIGURE 2. WRITE CYCLE I
To write, addresses must be stable, E low and W falling low
for a period no shorter than TWLWH. Data in is referenced
with the rising edge of W, (TDVWH and TWHDX). While
addresses are changing, W must be high. When W falls low,
the I/O pins are still in the output state for a period of TWLQZ
and input data of the opposite phase to the outputs must not
be applied, (Bus contention). If E transitions low
simultaneously with the W line transitioning low or after the
W transition, the output will remain in a high impedance
state. G is held continuously low.
193
HM-65162/883
Timing Waveforms (Continued)
(10) TAVAX
ADDRESS
(22) TAVWH
G
(11) TELWH
(14)
TWHAX
E
(12) TAVWL
(13) TWLWH
W
TGHQZ
(15)
Q
(21) TDVEH
D
(17) TDVWH
(18) TWHDX
FIGURE 3. WRITE CYCLE II
In this write cycle G has control of the output after a period,
TGHQZ. G switching the output to a high impedance state
allows data in to be applied without bus contention after
TGHQZ. When W transitions high, the data in can change
after TWHDX to complete the write cycle.
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention; within
VCC -0.3V to VCC +0.3V.
2. On RAMs which have selects or output enables (e.g., S, G), one
of the selects or output enables should be held in the deselected
state to keep the RAM outputs high impedance, minimizing
power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept between
VCC +0.3V and 70% of VCC during the power up and down transitions.
4. The RAM can begin operation > 55ns after VCC reaches the minimum operating voltage (4.5V).
DATA
RETENTION
TIMING
VCC
4.5V
VCC ≥ 02.0V
4.5V
>55ns
E
VCC -0.3V TO VCC +0.3V
FIGURE 4. DATA RETENTION TIMING
194
HM-65162/883
Test Circuit
DUT
(NOTE 1) CL
+
-
IOH
1.5V
IOL
EQUIVALENT CIRCUIT
NOTE:
1. Test head capacitance includes stray and jig capacitance.
Burn-In Circuits
HM-65162/883
CERDIP
TOP VIEW
HM-65162/883
CLCC
TOP VIEW
F10
VCC
C
VCC
F2
DQ1
DQ2
5
6
20
19
W
G
A10
E
7
18
8
17
9
16
10
15
DQ5
11
14
DQ4
12
13
DQ7
DQ6
DQ3
NC
NC
NC
VCC
NC
A8
6
28
7
8
27 NC
26 W
9
25
10
24
F3
A0 11
23
F2
NC 12
DQ0 13
F7
F6
F5
F4
F2
F2
32 31 30
A5
F8
F2
1
29
F1
F0
2
5
F9
F13
3
4
A6
F12
F0
NC
A7
21
F11
A4
A3
A2
A1
22
21
14 15 16 17 18
F2
F2
F2
GND
4
A9
A9
G
A10
E
DQ7
DQ6
19 20
DQ5
F2
DQ0
22
F2
F2
A0
3
DQ4
F3
A1
A8
F2
F4
A2
23
F2
F5
A3
2
NC
DQ3
F6
A4
VCC
GND
F7
A5
24
F2
F8
A6
1
DQ2
F9
A7
DQ1
F10
C
NOTES:
NOTES:
All resistors 47kW ±5%.
All resistors 47kW ±5%.
F0 = 100kHz ±10%.
F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2.
VCC = 5.5V ±0.5V.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
VIL = -0.2V to +0.4V.
C = 0.01μF Min.
C = 0.01μF Min.
195
F11
F12
F1
F0
F13
F0
F2
F2
HM-65162/883
Die Characteristics
DIE DIMENSIONS:
180.3 x 194.9 x 19 ±1mils
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.7 x 105 A/cm2
Metallization Mask Layout
HM-65162/883
A3
A4
A5
A6
A7
VCC A8
A9
W
G
A10
A2
A1
E
A0
DQ7
DQ0
DQ1 DQ2 GND DQ3
DQ4
DQ5 DQ6
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
196
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