DATASHEET

DATASHEET
±16.5kV ESD Protected, 16Mbps, with Active Low Rx
EN, RS-485/422 Receiver
ISL3282EMRTEP
Features
The Intersil ISL3282EMRTEP is a ±16.5kV IEC61000 ESD
protected, 3.0V to 5.5V powered, single receiver that meets
both the RS-485 and RS-422 standards for balanced
communication. This receiver has very low bus currents
(+125µA/-100µA), so it presents a true “1/8 unit load” to the
RS-485 bus. This allows up to 256 receivers on the network
without violating the RS-485 specification’s 32 unit load
maximum and without using repeaters.
• Specifications per DSCC VID V62/10601-01XB
Receiver inputs feature a “Full Fail-Safe” design, which ensures
a logic high Rx output if Rx inputs are floating, shorted, or
terminated but undriven.
• Full traceability through assembly and test by date/trace
code assignment
The ISL3282EMRTEP includes an active low enable pin and is
offered in the Military Temperature range (-55°C to +125°C).
• Enhanced obsolescence management
A 26% smaller footprint is available with the TDFN package.
This device also features a logic supply pin (VL) that sets the
VOH level of the RO output (and the switching points of the
RE/RE input) to be compatible with another supply voltage in
mixed voltage systems.
Device Information
The specifications for an Enhanced Product (EP) device are
defined in a Vendor Item Drawing (VID), which is controlled by
the Defense Supply Center in Columbus (DSCC). “Hot-links” to
the applicable VID and other supporting application
information are provided on our website.
Applications
• Full military temperature electrical performance from
-55°C to +125°C
• Controlled baseline with one wafer fabrication site and one
assembly/test site
• Full homogeneous lot processing in wafer fab
• No combination of wafer fabrication lots in assembly
• Enhanced process change notification
• Eliminates need for up-screening a COTS component
• ±16.5kV IEC61000 ESD protection on RS-485 inputs
• Class 3 ESD level on all other pins. . . . . . . . . . . . . .>5kV HBM
• Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V
• Specified for +125°C operation
• Logic supply pin (VL) eases operation in mixed supply
systems
• Full fail-safe (open, short, terminated/undriven)
• True 1/8 unit load allows up to 256 devices on the bus
• High data rates. . . . . . . . . . . . . . . . . . . . . . . . . . up to 16Mbps
• Low quiescent supply current. . . . . . . . . . 500µA (maximum)
• Very low shutdown supply current . . . . . . . 20µA (maximum)
• Clock distribution
• -7V to +12V common-mode input voltage range
• High node count systems
• Tri-statable Rx available (active low or high EN input)
• Space constrained systems
• 5V tolerant logic inputs when VCC  5V
• Security camera networks
• Building environmental control/lighting systems
• Industrial/process control networks
TABLE 1. SUMMARY OF FEATURES
PART NUMBER
FUNCTION
DATA RATE
(Mbps)
# DEVICES ON
BUS
RX
ENABLE?
VL PIN?
QUIESCENT ICC
(µA)
LOW POWER
SHUTDOWN?
LEAD
COUNT
ISL3282EMRTEP
1 Rx
16
256
ACTIVE LOW
YES
350
YES
8-TDFN
June 17, 2016
FN7595.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2010, 2011, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL3282EMRTEP
Ordering Information
PART NUMBER
(Notes 1, 2)
VENDOR ITEM
DRAWING
ISL3282EMRTEP-TK
V62/10601-01XB
PART MARKING
282
TEMP. RANGE
(°C)
TAPE AND REEL
(UNITS)
-55 to +125
1k
PKG.
DWG. #
PACKAGE
8 Ld TDFN
L8.2x3A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL3282EMRTEP. For more information on MSL please see techbrief
TB363.
Pin Configuration
Truth Table
ISL3282EMRTEP
(8 LD TDFN)
TOP VIEW
RECEIVING
INPUTS
OUTPUT
RE
A-B
RO
0
≥ -0.05V
RO
1
1
GND
2
0
≤ -0.2V
0
NC
0
Inputs Open/Shorted
1
VCC
1
X
High-Z*
8
B
7
RE
3
6
VL
4
5
A
R
Pin Descriptions
PIN
PIN
NUMBER NAME
FUNCTION
1
RO
Receiver output: If A - B ≥ -50mV, RO is high; If A - B ≤ -200mV, RO is low; RO = High if A and B are unconnected (floating) or shorted.
7
RE
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. If the Rx enable function is not used,
connect RE directly to GND. RE is internally pulled high.
2
GND Ground connection. This is also the potential of the TDFN thermal pad.
5
A
±16.5kV IEC61000 ESD Protected RS-485, RS-422 level, noninverting receiver input.
8
B
±16.5kV IEC61000 ESD Protected RS-485, RS-422 level, inverting receiver input.
4
VCC
System power supply input (3.0V to 5.5V). On devices with a VL pin, power-up VCC first.
6
VL
Logic-level supply, which sets the VIL/VIH levels for the RE pin, and sets the VOH level of the RO output. Power-up this supply after VCC,
and keep VL ≤ VCC.
3
NC
No Connection
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ISL3282EMRTEP
Typical Operating Circuits
+3.3V TO 5V
1.8V
+3.3V
+
4
VCC
6
VL
VCC
0.1µF
0.1µF
8
1 RO
R
1
VCC
ISL3282EMRTEP
LOGIC
DEVICE
(µP, ASIC,
UART)
2.5V
+
VCC
VL
ISL3298EMRTEP
A
5
B
8
RT
6
Y
7
Z
D
7 RE
LOGIC
DEVICE
(mP, ASIC,
UART)
DI 3
DE 2
GND
2
GND
4, 5
FIGURE 1. NETWORK WITH VL PIN FOR INTERFACE TO LOWER VOLTAGE LOGIC DEVICES
Test Circuits and Waveforms
RE
VCC
GND
B
R
A
+1V
B
RE
0V
15pF
RO
0V
-1V
A
tPHL
tPLH
VCC OR VL
SIGNAL
GENERATORS
50%
RO
50%
0V
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. RECEIVER PROPAGATION DELAY AND DATA RATE
RE
GND
3V
B
A
1kΩ
RO
R
VCC OR VL
SW
SIGNAL
GENERATOR
RE
1.5V
0V
GND
tZH
15pF
OUTPUT HIGH
PARAMETER
A (V)
SW
tHZ
+1.5
GND
tLZ
-1.5
VCC OR VL
tZH
+1.5
GND
tZL
-1.5
VCC OR VL
tHZ
VOH - 0.25V
50%
RO
FIGURE 3A. TEST CIRCUIT
1.5V
VOH
0V
tZL
RO
tLZ
VCC OR VL
50%
OUTPUT LOW
VOL + 0.25V V
OL
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. RECEIVER ENABLE AND DISABLE TIMES
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ISL3282EMRTEP
Application Information
VCC = +3.3V TO 5V
RS-485 and RS-422 are differential (balanced) data transmission
standards for use in long haul or noisy environments. RS-422 is a
subset of RS-485, so RS-485 transceivers are also RS-422
compliant. RS-422 is a point-to-multipoint (multidrop) standard,
which allows only one driver and up to 10 (assuming one unit load
devices) receivers on each bus. RS-485 is a true multipoint
standard, which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus.
Another important advantage of RS-485 is the extended
Common-Mode Range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as long as
4000’, so the wide CMR is necessary to handle ground potential
differences, as well as voltages induced in the cable by external
fields.
Receiver Features
This device utilizes a differential input receiver for maximum noise
immunity and common-mode rejection. Input sensitivity is better
than ±200mV, as required by the RS-422 and RS-485
specifications.
Receiver input resistance of 96kΩ surpasses the RS-422
specification of 4kΩ and is eight times the RS-485 “Unit Load
(UL)” requirement of 12kΩ minimum. Thus, these products are
known as “one-eighth UL” transceivers and there can be up to
256 of these devices on a network while still complying with the
RS-485 loading specification.
Receiver inputs function with common-mode voltages as great as
+9V/-7V outside the power supplies (i.e., +12V and -7V), making
them ideal for long networks where induced voltages, and ground
potential differences are realistic concerns.
The ISL3282EMRTEP includes a “full fail-safe” function that
guarantees a high level receiver output if the receiver inputs are
unconnected (floating), shorted together, or connected to a
terminated, however, undriven bus. Fail-safe with shorted inputs is
achieved by setting the Rx upper switching point to -50mV, thereby
ensuring that the Rx sees 0V differential as a high input level.
The receiver can easily support a 16Mbps data rate, and its
output is tri-statable via the active low RE input.
TABLE 2. VIH, VIL AND DATA RATE vs VL FOR VCC = 3.3V OR 5V
VL
(V)
VIH
(V)
VIL
(V)
DATA RATE
(Mbps)
1.35
0.55
0.5
11
1.6
0.7
0.6
16
1.8
0.8
0.7
23
2.3
1
0.9
27
2.7
1.1
1
30
3.3
1.3
1.2
30
5.5 (i.e., VCC)
2
1.8
24
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VCC = +2V
VL
RO
RE
VOH = 2V
RXD
VIH = 1V
GND
ISL3282EMRTEP
VOH  2V
ESD
DIODE
RXEN
GND
UART/PROCESSOR
FIGURE 4. USING VL PIN TO ADJUST LOGIC LEVELS
Wide Supply Range
The ISL3282EMRTEP is designed to operate with a wide range of
supply voltages from 3.0V to 5.5V. This device meets the RS-422
and RS-485 specifications over this full range.
Logic Supply (VL Pin)
Note: Power-up VCC before powering up the VL supply.
The ISL3282EMRTEP includes a VL pin that powers the logic
input (RE) and/or the Rx output. These pins interface with “logic”
devices such as UARTs, ASICs and microcontrollers. Today, most
of these devices use power supplies significantly lower than 3.3V,
thus, a 3.3V output level from a 3.3V powered RS-485 IC might
seriously overdrive and damage the logic device input. Similarly,
the logic device’s low VOH might not exceed the VIH of a 3.3V or
5V powered RE input. Connecting the VL pin to the power supply
of the logic device (as shown in Figure 4) limits the
ISL3282EMRTEP’s Rx output VOH to VL (see Figures 7 through
11), and reduces the RE input switching point to a value
compatible with the logic device’s output levels. Tailoring the
logic pin input switching point and output levels to the supply
voltage of the UART, ASIC, or microcontroller eliminates the need
for a level shifter/translator between the two ICs.
VL can be anywhere from VCC down to 1.35V, however, the input
switching points may not provide enough noise margin when
VL < 1.6V. Table 2 indicates typical VIH, VIL, and data rate values
for various VL settings so the user can ascertain whether or not a
particular VL voltage meets his/her needs.
The quiescent, RO unloaded, VL supply current (IL) is typically less
than 60µA for VL  3.3V, as shown in Figure 6 on page 6.
ESD Protection
All pins on the device include Class 3 (>4kV) Human Body Model
(HBM) ESD protection structures, however, the RS-485 pins
(receiver inputs) incorporate advanced structures allowing them
to survive ESD events in excess of ±16.5kV HBM and ±16.5kV
IEC61000. The RS-485 pins are particularly vulnerable to ESD
damage because they typically connect to an exposed port on
the exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that might
destroy unprotected ICs. These new ESD structures protect the
device whether or not it is powered up, and without degrading the
RS-485 common-mode range of -7V to +12V. This built-in ESD
FN7595.2
June 17, 2016
ISL3282EMRTEP
protection eliminates the need for board level protection
structures (e.g., transient suppression diodes), and the
associated, undesirable capacitive load they present.
IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment, rather
than to an individual IC. Therefore, the pins most likely to suffer
an ESD event are those that are exposed to the outside world (the
RS-485 pins in this case) and the IC is tested in its typical
application configuration (power applied) rather than testing
each pin-to-pin combination. The lower current limiting resistor
coupled with the larger charge storage capacitor yields a test
that is much more severe than the HBM test. The extra ESD
protection built into this device’s RS-485 pins allows the design
of equipment meeting level 4 criteria without the need for
additional board level protection on the RS-485 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the IC pin
until the voltage arcs to it. The current waveform delivered to the
IC pin depends on approach speed, humidity, temperature, etc.,
so it is difficult to obtain repeatable results. The A and B RS-485
pins withstand ±16.5kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the tested
pin before the probe tip is energized, thereby eliminating the
variables associated with the air-gap discharge. The result is a
more repeatable and predictable test, however, equipment limits
prevent testing devices at voltages higher than ±9kV. The
ISL3282EMRTEP can survive ±9kV contact discharges on the
RS-485 pins.
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Data Rate, Cables, and Terminations
RS-485, RS-422 are intended for network lengths up to 4000’,
however, the maximum system data rate decreases as the
transmission length increases. Networks operating at 16Mbps
are limited to lengths less than 100’, while a 250kbps network
that uses slew rate limited transmitters can operate at that data
rate over lengths of several thousand feet.
Twisted pair is the cable of choice for RS-485, RS-422 networks.
Twisted pair cables tend to pick up noise and other
electromagnetically induced voltages as common-mode signals,
which are effectively rejected by the differential receiver in these
ICs.
To minimize reflections, proper termination is imperative for high
data rate networks. Short networks using slew rate limited
transmitters need not be terminated, however, terminations are
recommended unless power dissipation is an overriding concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120Ω) at the end farthest
from the driver. In multireceiver applications, stubs connecting
receivers to the main cable should be kept as short as possible.
Multipoint (multidriver) systems require that the main cable be
terminated in its characteristic impedance at both ends. Stubs
connecting a transmitter or receiver to the main cable should be
kept as short as possible.
Low Power Shutdown Mode
This BiCMOS receiver uses a fraction of the power required by its
bipolar counterparts, and include a shutdown feature that
reduces the already low quiescent ICC to a 20µA trickle. They
enter shutdown whenever the receiver is disabled (RE = VCC).
FN7595.2
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ISL3282EMRTEP
Typical Performance Curves CL = 15pF, TA = +25°C; unless otherwise specified.
440
250
VCC = 5V OR 3.3V
VCC = VL = 5.5V
430
200
420
IL (mA)
ICC (µA)
410
400
150
VL = 5V, VCC = 5V ONLY
100
VCC = VL = 3.3V
390
VL  1.8V
50
380
VL = 3.3V
370
-55
-35
-15
5
25
45
65
85
105
0
125
VL = 2.5V
0
1
2
3
TEMPERATURE (°C)
FIGURE 5. SUPPLY CURRENT vs TEMPERATURE
VOL, +25°C
VOH, +25°C
40
VOL, +85°C
VOL, +125°C
VOH, +125°C
30
VOH, +85°C
20
10
0
VOL, +25°C
25
VOL, +125°C
20
15
VOH, +85°C
VOH, +125°C
10
5
VCC = 5V OR 3.3V, VL = 3.3V
0
1
2
3
4
0
5
0
9
VCC = 5V OR 3.3V, VL = 2.5V
18
VOL, +25°C
VOL, +85°C
16
14
VOL, +125°C
12 VOH, +25°C
10
8
VOH, +125°C
6
VOH, +85°C
4
2
0
0.5
1.0
1.5
2.0
2.5
RECEIVER OUTPUT VOLTAGE (V)
FIGURE 9. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT
VOLTAGE
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1.0
1.5
2.0
2.5
3.0 3.3
FIGURE 8. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT
VOLTAGE
RECEIVER OUTPUT CURRENT (mA)
20
0.5
RECEIVER OUTPUT VOLTAGE (V)
FIGURE 7. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT
VOLTAGE
RECEIVER OUTPUT CURRENT (mA)
VOL, +85°C
VOH, +25°C
RECEIVER OUTPUT VOLTAGE (V)
0
7 7.5
30
VCC = VL = 5V
50
6
5
FIGURE 6. VL SUPPLY CURRENT vs ENABLE PIN VOLTAGE
RECEIVER OUTPUT CURRENT (mA)
RECEIVER OUTPUT CURRENT (mA)
60
4
RE VOLTAGE (V)
VCC = 5V OR 3.3V, VL = 1.8V
8
VOL, +25°C
VOL, +85°C
7
VOL, +125°C
6
5
4
VOH, +25°C
VOH, +85°C
3
VOH, +125°C
2
1
0
0
0.5
1.0
1.5
1.8
RECEIVER OUTPUT VOLTAGE (V)
FIGURE 10. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT
VOLTAGE
FN7595.2
June 17, 2016
ISL3282EMRTEP
Typical Performance Curves CL = 15pF, TA = +25°C; unless otherwise specified. (Continued)
45
VCC = 5V or 3.3V, VL = 1.5V
4.5
VOL, +85°C
4.0
VOL, +25°C
PROPAGATION DELAY (ns)
RECEIVER OUTPUT CURRENT (mA)
5.0
VOL, +125°C
3.5
3.0
2.5
2.0
VOH, +85°C
VOH, +25°C
1.5
VOH, +125°C
1.0
40
35
VCC = 5.5V, TPLH
30
VCC = 5.5V, TPHL
25
0.5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
20
1.4 1.5
-55
-35
-15
RECEIVER OUTPUT VOLTAGE (V)
FIGURE 11. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT
VOLTAGE
PROPAGATION DELAY (ns)
1.0
0.5
125
45
40
VCC = 3.3V, TPLH
35
VCC = 3.3V, TPHL
30
25
-55
-35
-15
5
25
45
65
TEMPERATURE (°C)
85
105
RECEIVER INPUT (V)
3.50
3.00
VCC = 5.0V, SKEW
2.50
2.00
1.50
1.00
0.50
-35
-15
5
25
45
65
TEMPERATURE (°C)
85
105
FIGURE 15. RECEIVER SKEW vs TEMPERATURE
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-55
-35
-15
5
25
45
65
TEMPERATURE (°C)
85
105
125
FIGURE 14. RECEIVER PROPAGATION DELAY vs TEMPERATURE
4.00
-55
20
125
125
RECEIVER OUTPUT (V)
PROPAGATION DELAY (ns)
VCC = 3.3V, SKEW
1.5
FIGURE 13. RECEIVER SKEW vs TEMPERATURE
PROPAGATION DELAY (ns)
105
50
2.0
0.00
85
FIGURE 12. RECEIVER PROPAGATION DELAY vs TEMPERATURE
2.5
0.0
5
25
45
65
TEMPERATURE (°C)
VCC = 5V
2.0
0
-2.0
5.0
A-B
VL = 5V
4.0
3.0
VL = 2.5V
2.0
1.0
0
VL = 1.5V
TIME (20ns/DIV)
FIGURE 16. RECEIVER WAVEFORMS
FN7595.2
June 17, 2016
ISL3282EMRTEP
RECEIVER OUTPUT (V)
RECEIVER INPUT (V)
Typical Performance Curves CL = 15pF, TA = +25°C; unless otherwise specified. (Continued)
Die Characteristics
VCC = 3.3V
2.0
0
A-B
-2.0
SUBSTRATE AND TDFN THERMAL PAD POTENTIAL
(POWERED UP):
GND
TRANSISTOR COUNT:
4.0
140
VL = 3.3V
3.0
PROCESS:
VL = 2.5V
2.0
VL = 1.5V
1.0
Si Gate BiCMOS
0
TIME (20ns/DIV)
FIGURE 17. RECEIVER WAVEFORMS
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please go to web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
June 17, 2016
FN7595.2
Updated title to fit 100 character limit.
Removed Pb-Free bullet under Features section.
Updated Ordering Information table by removing Pb-Free notes and obsolete parts. Added Tape and
Reel Quantity and PKG DWG columns.
Replaced Products section with About Intersil.
Added the applicable POD.
January 27, 2011
FN7595.1
In Figure 5 on page 6, corrected units of y axis from mA to µA.
February 26, 2010
FN7595.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7595.2
June 17, 2016
ISL3282EMRTEP
Package Outline Drawing
L8.2x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE WITH E-PAD
Rev 2, 05/15
0.25
0.50
2.20
6
PIN 1
INDEX AREA
(4X)
6
PIN #1 INDEX AREA
B
3.00
A
1.80 +0.1/ -0.15
2.00
0.15
(8x0.40)
1.65 +0.1/ -0.15
TOP VIEW
BOTTOM VIEW
(8x0.25)
PACKAGE
OUTLINE
(6x0.50)
0.75
SEE DETAIL "X"
SIDE VIEW
1.80
3.00
0.05
(8x0.40)
1.65
C
0.20 REF
C
BASE PLANE
SEATING PLANE
0.08 C
5
(8x0.20)
0.05
2.00
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.20mm and 0.32mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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FN7595.2
June 17, 2016
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