DATASHEET

DATASHEET
Radiation Hardened High Speed Dual Voltage
Comparators
ISL7119RH, ISL7119EH
Features
The ISL7119RH, ISL7119EH are radiation hardened, high
speed, dual voltage comparators fabricated on a single
monolithic chip. They are designed to operate over a wide dual
supply voltage range as well as a single 5V logic supply and
ground. The open collector output stage facilitates interfacing
with a variety of logic devices and has the ability to drive relays
and lamps at output currents up to 25mA.
• Electrically screened to DLA SMD # 5962-07215
The ISL7119RH, ISL7119EH are fabricated on our dielectrically
isolated Radiation Hardened Silicon Gate (RSG) process, which
provides immunity to Single Event Latch-Up (SEL) and highly
reliable performance in the natural space environment.
• QML qualified per MIL-PRF-38535 requirements
• Radiation environment
- Total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 x 105 rad(Si)
- SEL/SEB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Immune
• Input offset voltage (VIO). . . . . . . . . . . . . . . . . . . . . 8mV (max)
• Input bias current (IBIAS). . . . . . . . . . . . . . . . . . 1000nA (max)
• Input offset current (IIO) . . . . . . . . . . . . . . . . . . . 150nA (max)
• Saturation voltage at ISINK = 3.2mA (VSAT) . . . . 0.65V (max)
• Saturation voltage at ISINK = 25mA (VSAT). . . . . . 1.8V (max)
Pin Configuration
• Response time (tPD) . . . . . . . . . . . . . . . . . . . . . . . 160ns (max)
ISL7119RH, ISL7119EH
(10 LD FLATPACK GDFP1-F10 OR CDFP2-F10)
TOP VIEW
Applications
• Window detector
OUT 1
1
10
+VS
• Level shifter
GND 1
2
9
-IN 2
• Relay driver
+IN 1
3
8
+IN 2
-IN 1
4
7
GND 2
-VS
5
6
OUT 2
• Lamp driver
Ordering Information
SMD/ORDERING
NUMBER (Note 2)
INTERNAL
MKT. NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962F0721501QXC
ISL7119RHQF (Note 1)
Q 5962F07 21501QXC
-55 to +125
10 Lead Ceramic Metal Seal Flatpack
K10.A
5962F0721501VXC
ISL7119RHVF (Note 1)
Q 5962F07 21501VXC
-55 to +125
10 Lead Ceramic Metal Seal Flatpack
K10.A
5962F0721502VXC
ISL7119EHVF (Note 1)
Q 5962F07 21502VXC
-55 to +125
10 Lead Ceramic Metal Seal Flatpack
K10.A
5962F0721501V9A
ISL7119RHVX
-55 to +125
Die
5962F0721502V9A
ISL7119EHVX
-55 to +125
Die
ISL7119RHF/PROTO
ISL7119RHF/PROTO
(Note 1)
-55 to +125
10 Lead Ceramic Metal Seal Flatpack
ISL7119RHX/SAMPLE
ISL7119RHX/SAMPLE
-55 to +125
Die
ISL7 119RHF /PROTO
K10.A
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
April 15, 2016
FN6607.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 200, 2008, 2011, 2013, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL7119RH, ISL7119EH
Die Characteristics
Backside Finish:
Silicon
DIE DIMENSIONS:
ASSEMBLY RELATED INFORMATION:
2030µm x 2030µm (~80 mils x 80 mils)
Thickness: 483µm  25.4µm (19 mils 1 mil)
Substrate Potential:
Unbiased (DI)
INTERFACE MATERIAL:
ADDITIONAL INFORMATION:
Glassivation:
Worst Case Current Density:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ 1.0kÅ
<2.0 x 105 A/cm2
Top Metallization:
Transistor Count:
Type: AlSiCu
Thickness: 16.0kÅ 2kÅ
66
Metallization Mask Layout
Substrate:
Radiation Hardened Silicon Gate, Dielectric Isolation
ISL7119RH, ISL7119EH
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL7119RH, ISL7119EH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
April 15, 2016
FN6607.5
CHANGE
Updated package info in ordering information for parts ending in X from 10 Lead Ceramic Metal Seal
Flatpack to Die.
Added Revision History and About Intersil sections.
Added POD K10.A.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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ISL7119RH, ISL7119EH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
e
A
INCHES
A
-A-
D
-BPIN NO. 1
ID AREA
b
E1
0.004 M
H A-B S
Q
D S
S1
0.036 M
H A-B S
D S
C
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
(c)
b1
M
M
(b)
SECTION A-A
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.290
-
7.37
3
E
0.240
0.260
6.10
6.60
-
E1
-
0.280
-
7.11
3
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
2
e
LEAD FINISH
BASE
METAL
SYMBOL
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
10
10
Rev. 0 3/07
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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