DATASHEET

HI-506A, HI-507A, HI-508A, HI-509A
®
Data Sheet
October 30, 2007
FN3143.6
16-Channel, 8-Channel, Differential
8-Channel and Differential 4-Channel,
CMOS Analog MUXs with Active
Overvoltage Protection
Features
The HI-506A, HI-507A, HI-508A and HI-509A are analog
multiplexers with active overvoltage protection. Analog input
levels may greatly exceed either power supply without
damaging the device or disturbing the signal path of other
channels. Active protection circuitry assures that signal
fidelity is maintained even under fault conditions that would
destroy other multiplexers. Analog inputs can withstand
constant 70VP-P levels with ±15V supplies. Digital inputs will
also sustain continuous faults up to 4V greater than either
supply. In addition, signal sources are protected from short
circuiting should multiplexer supply loss occur. Each input
presents 1kΩ of resistance under this condition. These
features make the HI-506A, HI-507A, HI-508A and HI-509A
ideal for use in systems where the analog inputs originate
from external equipment, or separately powered circuitry. All
devices are fabricated with 44V dielectrically isolated CMOS
technology. The HI-506A is a single 16-channel multiplexer,
the HI-507A is an 8-channel differential multiplexer, the
HI-508A is a single 8-channel multiplexer and the HI-509A is
a differential 4-channel multiplexer. If input overvoltage
protection is not needed the HI-506/507/508/509
multiplexers are recommended. For further information see
Application Note AN520.
• Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V
1
• Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70VP-P
• No Channel Interaction During Overvoltage
• Fail Safe with Power Loss (No Latch-Up)
• Break-Before-Make Switching
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns
• Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW
• Pb-Free Available (RoHS Compliant)
Applications
• Data Acquisition Systems
• Industrial Controls
• Telemetry
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved
HI-506A, HI-507A, HI-508A, HI-509A
Ordering Information
PART
NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
HI1-0506A-2
HI1-506A-2
-55 to +125
28 Ld CERDIP
F28.6
HI1-0506A-5
HI1-506A-5
0 to +75
28 Ld CERDIP
F28.6
HI1-0506A-8
HI1-506A-8
-55 to +125
+ 160 Hour Burn-In
28 Ld CERDIP
F28.6
HI3-0506A-5
HI3-506A-5
0 to +75
28 Ld PDIP
E28.6
HI3-0506A-5Z (Note 1)
HI3-506A-5Z
0 to +75
28 Ld PDIP (Note 2) (Pb-free)
E28.6
HI3-0507A-5
HI3-507A-5
0 to +75
28 Ld PDIP
E28.6
HI3-0507A-5Z (Note 1)
HI3-507A-5Z
0 to +75
28 Ld PDIP (Note 2) (Pb-free)
E28.6
HI1-0508A-8
HI1-508A-8
-55 to +125
+ 160 Hour Burn-In
16 Ld CERDIP
F16.3
HI3-0508A-5
HI3-508A-5
0 to +75
16 Ld PDIP
E16.3
HI3-0508A-5Z (Note 1)
HI3-508A-5Z
0 to +75
16 Ld PDIP (Note 2) (Pb-free)
E16.3
HI1-0509A-2
HI1-509A-2
-55 to +125
16 Ld CERDIP
F16.3
HI1-0509A-5
HI1-509A-5
0 to +75
16 Ld CERDIP
F16.3
HI1-0509A-8
HI1-509A-8
-55 to +125
+ 160 Hour Burn-In
16 Ld CERDIP
F16.3
HI3-0509A-5
HI3-509A-5
0 to +75
16 Ld PDIP
E16.3
HI3-0509A-5Z (Note 1)
HI3-509A-5Z
0 to +75
16 Ld PDIP (Note 2) (Pb-free)
E16.3
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte
tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
2
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Pinouts
HI-506A (CERDIP, PDIP)
TOP VIEW
28 OUT
+VSUPPLY 1
HI-507A (PDIP)
TOP VIEW
+VSUPPLY 1
27 -VSUPPLY
NC 3
26 IN 8
NC 3
26 IN 8A
IN 16 4
25 IN 7
IN 8B 4
25 IN 7A
IN 15 5
24 IN 6
IN 7B 5
24 IN 6A
IN 14 6
23 IN 5
IN 6B 6
23 IN 5A
IN 13 7
22 IN 4
IN 5B 7
22 IN 4A
IN 12 8
21 IN 3
IN 4B 8
21 IN 3A
IN 11 9
20 IN 2
IN 3B 9
20 IN 2A
IN 10 10
19 IN 1
IN 2B 10
19 IN 1A
18 ENABLE
IN 1B 11
18 ENABLE
IN 9 11
OUT B 2
28 OUT A
NC 2
27 -VSUPPLY
GND 12
17 ADDRESS A0
GND 12
17 ADDRESS A0
VREF 13
16 ADDRESS A1
VREF 13
16 ADDRESS A1
ADDRESS A3 14
15 ADDRESS A2
NC 14
15 ADDRESS A2
HI-508A (CERDIP, PDIP)
TOP VIEW
A0 1
16 A1
ENABLE 2
15 A2
14 GND
-VSUPPLY 3
HI-509A (CERDIP, PDIP)
TOP VIEW
A0 1
ENABLE 2
-VSUPPLY 3
16 A1
15 GND
14 +VSUPPLY
IN 1 4
13 +VSUPPLY
IN 1A 4
13 IN 1B
IN 2 5
12 IN 5
IN 2A 5
12 IN 2B
IN 3 6
11 IN 6
IN 3A 6
11 IN 3B
IN 4 7
10 IN 7
IN 4A 7
10 IN 4B
OUT 8
9 IN 8
OUT A 8
3
9 OUT B
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Truth Tables
HI-506A
HI-508A
A3
A2
A1
A0
EN
“ON” CHANNEL
A2
A1
A0
EN
“ON” CHANNEL
X
X
X
X
L
None
X
X
X
L
None
L
L
L
L
H
1
L
L
L
H
1
L
L
L
H
H
2
L
L
H
H
2
L
L
H
L
H
3
L
H
L
H
3
L
L
H
H
H
4
L
H
H
H
4
L
H
L
L
H
5
H
L
L
H
5
L
H
L
H
H
6
H
L
H
H
6
L
H
H
L
H
7
H
H
L
H
7
L
H
H
H
H
8
H
H
H
H
8
H
L
L
L
H
9
H
L
L
H
H
10
H
L
H
L
H
11
A1
A0
EN
“ON” CHANNEL PAIR
H
L
H
H
H
12
X
X
L
None
H
H
L
L
H
13
L
L
H
1
H
H
L
H
H
14
L
H
H
2
H
H
H
L
H
15
H
L
H
3
H
H
H
H
H
16
H
H
H
4
HI-509A
HI-507A
A2
A1
A0
EN
“ON” CHANNEL PAIR
X
X
X
L
None
L
L
L
H
1
L
L
H
H
2
L
H
L
H
3
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
4
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Functional Diagrams
HI-506A
IN 1
HI-507A
OUT
1k
IN 1A
1k
IN 2
IN 8A
OUT
A
1k
1k
OUT
B
1k
DECODER/
DRIVER
IN 1B
1k
IN 16
1k
DECODER/
DRIVER
IN 8B
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
5V
REF
LEVEL
SHIFT
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
† † † † †
5V
REF
† DIGITAL INPUT
PROTECTION
†
VREF A0 A1 A2 A3 EN
† DIGITAL INPUT
VREF A0
PROTECTION
HI-508A
IN 1
LEVEL
SHIFT
†
†
†
A1
A2
EN
HI-509A
OUT
1k
IN 1A
1k
IN 2
IN 4A
OUT
A
1k
1k
OUT
B
1k
DECODER/
DRIVER
IN 1B
1k
IN 8
1k
DECODER/
DRIVER
IN 4B
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
5V
REF
LEVEL
SHIFT
†
†
†
†
A0
A1
A2
EN
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
† DIGITAL INPUT
PROTECTION
† DIGITAL INPUT
PROTECTION
5
5V
REF
LEVEL
SHIFT
†
†
†
A0
A1
EN
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Schematic Diagrams
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
TTL REFERENCE
CIRCUIT
V+
R10
R9
Q1
VREF
Q4
D3
GND
LEVEL SHIFTER
V+
OVERVOLTAGE
PROTECTION
P
P
P
N
R2
P
P
P
P
R5
V+
P
LEVEL
SHIFTED
ADDRESS
TO
DECODE
R7
R6
N
D1
P
R4
R3
D2
R1
200
Ω
P
N
N
R8
N
N
N
N
N
N
V-
V-
GND
ADD
IN
ADDRESS DECODER
V+
P
P
P
P
A0 OR A0
A1 OR A1
A2 OR A2
A3 OR A3
P
P
P
N
N
N
TO P-CHANNEL
DEVICE OF
THE SWITCH
N
N
TO N-CHANNEL
DEVICE OF
THE SWITCH
N
N
ENABLE
DELETE A3 OR A3 INPUT
FOR HI-507A, HI-508A, HI-509A
DELETE A2 OR A2 INPUT FOR HI-509A
6
V-
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Schematic Diagrams
(Continued)
MULTIPLEX SWITCH
FROM DECODE
OVERVOLTAGE PROTECTION
N
V+
Q5
P
R11
1k
D7
D6
D4
D5
N
IN
OUT
N
Q6
VP
FROM DECODE
7
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V
Digital Input Voltage (VEN , VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V
or 20mA, Whichever Occurs First
Analog Signal (VIN, VOUT) . . . . . . . . . . . . . . (V-) -20V to (V+) +20V
Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, IN or OUT, Pulsed 1ms, 10% Duty Cycle (Max) . . 40mA
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
θJC (°C/W)
28 Ld CERDIP Package. . . . . . . . . . . .
55
18
16 Ld CERDIP Package. . . . . . . . . . . .
75
22
28 Ld PDIP Package . . . . . . . . . . . . . .
60
N/A
16 Ld PDIP Package . . . . . . . . . . . . . .
90
N/A
Maximum Junction Temperature
CERDIP Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Ranges
HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . .-55°C to +125°C
HI-506A/507A/508A/509A-5. . . . . . . . . . . . . . . . . . . 0°C to +75°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V,
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section.
-2, -8
TEST
CONDITIONS
PARAMETER
TEMP
(°C)
-5
MIN
MAX
MIN
MAX
(Note 12) TYP (Note 12) (Note 12) TYP (Note 12) UNITS
DYNAMIC CHARACTERISTICS
Access Time, tA
Note 4
Break-Before-Make Delay, tOPEN
Note 4
Enable Delay (ON), tON(EN)
Note 4
25
-
0.5
-
-
0.5
-
μs
Full
-
-
1.0
-
-
1.0
μs
25
25
80
-
25
80
-
ns
25
-
300
500
-
300
-
ns
Full
-
-
1000
-
-
1000
ns
25
-
300
500
-
300
-
ns
Full
-
-
1000
-
-
1000
ns
To 0.1%
25
-
1.2
-
-
1.2
-
μs
To 0.01%
25
-
3.5
-
-
3.5
-
μs
To 0.1%
25
-
1.2
-
-
1.2
-
μs
To 0.01%
25
-
3.5
-
-
3.5
-
μs
Note 9
25
-
68
-
-
68
-
dB
25
-
10
-
-
10
-
pF
HI-506A
25
-
52
-
-
52
-
pF
HI-507A
25
-
30
-
-
30
-
pF
HI-508A
25
-
25
-
-
25
-
pF
Note 4
Enable Delay (OFF), tOFF(EN)
Settling Time, tS
HI-506A and HI-507A
HI-508A and HI-509A
Off Isolation
Channel Input Capacitance, CS(OFF)
Channel Output Capacitance, CD(OFF)
HI-509A
25
-
12
-
-
12
-
pF
Digital Input Capacitance, CA
25
-
10
-
-
10
-
pF
Input to Output Capacitance, CDS(OFF)
25
-
0.1
-
-
0.1
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, TTL Drive, VAL
Note 4
Full
-
-
0.8
-
-
0.8
V
Input High Threshold, VAH (Note 11)
Note 4
Full
4.0
-
-
4.0
-
-
V
8
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Electrical Specifications
Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V,
Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. (Continued)
-2, -8
TEST
CONDITIONS
PARAMETER
TEMP
(°C)
-5
MIN
MAX
MIN
MAX
(Note 12) TYP (Note 12) (Note 12) TYP (Note 12) UNITS
Input Leakage Current (High or Low), IA
Notes 4, 8
Full
-
-
1.0
-
-
1.0
μA
MOS Drive, VAL , HI-506A/HI-507A
VREF = +10V
25
-
-
0.8
-
-
0.8
V
MOS Drive, VAH , HI-506A/HI-507A
VREF = +10V
25
6.0
-
-
6.0
-
-
V
Analog Signal Range, VIN
Note 4
Full
-15
-
+15
-15
-
+15
V
On Resistance, rON
Notes 4, 5
25
-
1.2
1.5
-
1.5
1.8
kΩ
Full
-
1.5
1.8
-
1.8
2.0
kΩ
25
-
0.03
-
-
0.03
-
nA
Full
-
-
50
-
-
50
nA
25
-
0.1
-
-
0.1
-
nA
HI-506A
Full
-
-
300
-
-
300
nA
HI-507A
Full
-
-
200
-
-
200
nA
HI-508A
Full
-
-
200
-
-
200
nA
HI-509A
Full
-
-
100
-
-
100
nA
25
-
4.0
-
-
4.0
-
nA
ANALOG CHANNEL CHARACTERISTICS
Off Input Leakage Current, IS(OFF)
Off Output Leakage Current, ID(OFF)
Notes 4, 6
Notes 4, 6
ID(OFF) With Input Overvoltage Applied
Note 7
On Channel Leakage Current, ID(ON)
Notes 4, 6
Full
-
-
2.0
-
-
-
μA
25
-
0.1
-
-
0.1
-
nA
HI-506A
Full
-
-
300
-
-
300
nA
HI-507A
Full
-
-
200
-
-
200
nA
HI-508A
Full
-
-
200
-
-
200
nA
Full
-
-
100
-
-
100
nA
Full
-
-
50
-
-
50
nA
HI-509A
Differential Off Output Leakage Current, IDIFF,
(HI-507A, HI-509A Only)
POWER SUPPLY CHARACTERISTICS
Current, I+
Notes 4, 10
Full
-
0.5
2.0
-
0.5
2.0
mA
Current, I-
Notes 4, 10
Full
-
0.02
1.0
-
0.02
1.0
mA
Full
-
7.5
-
-
7.5
-
mW
Power Dissipation, PD
NOTES:
4. 100% tested for Dash 8. Leakage currents not tested at -55°C.
5. VOUT = ±10V, IOUT = +100μA.
6. 10nA is the practical lower limit for high speed measurement in the production test environment.
7. Analog Overvoltage = ±33V.
8. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at +25°C.
9. VEN = 0.8V, RL = 1k, CL = 15pF, VS = 7VRMS , f = 100kHz.
10. VEN , VA = 0V or 4V.
11. To drive from DTL/TTL Circuits, 1kΩ pull-up resistors to +5V supply are recommended.
12. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
9
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Test Circuits and Waveforms
TA = +25°C, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open,
Unless Otherwise Specified
100μA
V2
IN
OUT
VIN
rON =
V2
100μA
FIGURE 1A. TEST CIRCUIT
+125°C
1.2
1.1
+25°C
1.0
-55°C
0.9
0.8
0.7
0.6
-10
-55°C TO +125°C
VIN = +5V
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
-8
-6
-4
-2
0
2
4
ANALOG INPUT (V)
6
8
10
5
6
7
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE (±V)
FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY
VOLTAGE
FIGURE 1. ON RESISTANCE
100nA
LEAKAGE CURRENT
10nA
ON LEAKAGE
CURRENT
ID(ON)
OFF OUTPUT
CURRENT
ID(OFF)
+0.8V
EN
OUT
1nA
A
10pA
±10V
OFF INPUT
LEAKAGE CURRENT
IS(OFF)
100pA
25
50
75
100
ID(OFF)
±
ON RESISTANCE (kΩ)
1.3
NORMALIZED RESISTANCE
(REFERRED TO VALUE AT ±15V)
1.4
10V
125
TEMPERATURE (°C)
FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE
10
FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 13)
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Test Circuits and Waveforms
TA = +25°C, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open,
Unless Otherwise Specified (Continued)
OUT
OUT
A
IS(OFF)
A
+0.8V
EN
A0
±
±10V
A1
ID(ON)
EN
±10V
10V
10V
±
4V
FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 13)
FIGURE 2D. ID(On) TEST CIRCUIT (NOTE 13)
NOTE:
13. Two measurements per channel: ±10V and +10V. (Two measurements per device for ID(OFF) ±10V and +10V.)
FIGURE 2. LEAKAGE CURRENTS
ANALOG INPUT CURRENT (mA)
18
6
ANALOG INPUT
CURRENT (IIN)
15
5
12
4
9
3
6
2
OUTPUT OFF LEAKAGE
CURRENT ID(OFF)
3
1
0
OUTPUT OFF LEAKAGE CURRENT (nA)
7
A
A
IIN
ID(OFF)
±VIN
0
15
18
21
24
27
30
33
36
ANALOG INPUT OVERVOLTAGE (±V)
FIGURE 3A. ANALOG INPUT OVERVOLTAGE
CHARACTERISTICS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS
±14
-55°C
+25°C
SWITCH CURRENT (mA)
±12
±10
+125°C
±8
±6
±VIN
±4
A
±2
0
0
2
4
6
8
10
12
14
VOLTAGE ACROSS SWITCH (±V)
FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE
FIGURE 4B. TEST CIRCUIT
FIGURE 4. ON CHANNEL CURRENT
11
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Test Circuits and Waveforms
TA = +25°C, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open,
Unless Otherwise Specified (Continued)
+15V/+10V
8
+ISUPPLY
V+
6
VA
50Ω
VSUPPLY = ±10V
2
HI-506A†
A1
IN 2
THRU
IN 7/IN 15
A0
IN 8/IN 16
EN
+4V
GND
0
1k
10k
100k
TOGGLE FREQUENCY (Hz)
1M
±
A2
VSUPPLY = ±15V
4
±10V/±5V
IN 1
A3
OUT
V-
10V/
10
MΩ
±
SUPPLY CURRENT (mA)
A
5V
14
pF
A -ISUPPLY
10M
-15V/-10V
FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY
† Similar connection for HI-507A/HI-508A/HI-509A
FIGURE 5B. TEST CIRCUIT
FIGURE 5. DYNAMIC SUPPLY CURRENT
+15V
900
ACCESS TIME (ns)
VREF
A3
700
A2
VA
600
50Ω
A1
HI-506A†
10V
IN 16
EN
+4V
GND
400
±10V
IN 2 THRU
IN 7/IN 15
A0
500
V+
IN 1
±
VREF = OPEN FOR LOGIC HIGH LEVEL ≤ 6V
VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V
800
OUT
V-
10
kΩ
50
pF
300
3
4
5
6
7
8
9 10 11 12
LOGIC LEVEL (HIGH) (V)
13
14
FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH)
15
-15V
† Similar connection for HI-507A/HI-580A/HI-509A
FIGURE 6B. TEST CIRCUIT
VAH = 4.0V
VA INPUT
2V/DIV.
ADDRESS
DRIVE (VA)
S1 ON
1/ V
2 AH
0V
+10V
OUTPUT
5V/DIV.
OUTPUT
10%
-10V
S16 ON
tA
200ns/DIV.
FIGURE 6C. MEASUREMENT POINTS
FIGURE 6D. WAVEFORMS
FIGURE 6. ACCESS TIME
12
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Test Circuits and Waveforms
A3
TA = +25°C, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open,
Unless Otherwise Specified (Continued)
HI-506A †
A2
+5V
IN 1
VAH = 4.0V
IN 2 THRU
VA
50Ω
+4.0V
A1
IN 7/IN 15
A0
IN 8/IN 16
EN
OUT
GND
ADDRESS
DRIVE (VA)
0V
VOUT
OUTPUT
1kΩ
50pF
50%
50%
tOPEN
† Similar connection for HI-507A/HI-508A/HI-509A
FIGURE 7B. MEASUREMENT POINTS
FIGURE 7A. TEST CIRCUIT
VA INPUT
2V/DIV.
S1 ON
S16 ON
OUTPUT
0.5V/DIV.
100ns/DIV.
FIGURE 7C. WAVEFORMS
FIGURE 7. BREAK-BEFORE-MAKE DELAY
13
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Test Circuits and Waveforms
A3
TA = +25°C, VSUPPLY = ±15V, VAH = 4V, VAL = 0.8V, VREF = Open,
Unless Otherwise Specified (Continued)
HI-506A †
A2
IN 1
A1
IN 2 THRU
IN 7/IN 15
IN 8 /IN 16
+10V
VAH = 4.0V
50%
50%
ENABLE DRIVE
(VA)
0V
A0
EN
VA
50Ω
VOUT
OUT
GND
1kΩ
90%
OUTPUT
10%
0V
50pF
tON(EN)
tOFF(EN)
† Similar connection for HI-507A//HI-508A/HI-509A
FIGURE 8B. MEASUREMENT POINTS
FIGURE 8A. TEST CIRCUIT
ENABLE DRIVE
2V/DIV.
DISABLED
ENABLED
(S1 ON)
OUTPUT
2V/DIV.
100ns/DIV.
FIGURE 8C. WAVEFORMS
FIGURE 8. ENABLE DELAYS
14
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Die Characteristics
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
159 mils x 83.9 mils
TRANSISTOR COUNT:
METALLIZATION:
485
Type: CuAl
Thickness: 16kÅ ±2kÅ
PROCESS:
SUBSTRATE POTENTIAL (NOTE):
CMOS-DI
-VSUPPLY
PASSIVATION:
Silox: 12kÅ ±2kÅ
Nitride: 3.5kÅ ±1kÅ
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
conductor at -VSUPPLY potential.
Metallization Mask Layouts
HI-506A
EN
(18)
A0
(17)
A1 A2
(16) (15)
HI-507A
A3 VREF
(14) (13)
GND
(12)
EN
(18)
A0
(17)
A1 A2
(16) (15)
NC VREF
(14) (13)
GND
(12)
IN 1
(19)
IN 9
(11)
IN 1A
(19)
IN 2
(20)
IN 10
(10)
IN 2A
(20)
IN 3
(21)
IN 11
(9)
IN 3A
(21)
IN 3B
(9)
IN 4
(22)
IN 12
(8)
IN 4A
(22)
IN 4B
(8)
IN 5
(23)
IN 6
(24)
IN 13
(7)
IN 14
(6)
IN 5A
(23)
IN 6A
(24)
IN 5B
(7)
IN 6B
(6)
IN 7
(25)
IN 15
(5)
IN 7A
(25)
IN 7B
(5)
IN 8
(26)
IN 16
(4)
IN 8A
(26)
IN 8B
(4)
V- (27)
OUT (28)
+V (1)
15
NC (2)
V- (27)
IN 1B
(11)
IN 2B
(10)
OUT A (28)
+V (1)
OUT B(2)
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Die Characteristics
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
108 mils x 83 mils
TRANSISTOR COUNT:
METALLIZATION:
253
Type: CuAl
Thickness: 16kÅ ±2kÅ
PROCESS:
SUBSTRATE POTENTIAL (NOTE):
CMOS-DI
-VSUPPLY
PASSIVATION:
Silox: 12kÅ ±2kÅ
Nitride: 3.5kÅ ±1kÅ
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
conductor at -VSUPPLY potential.
Metallization Mask Layouts
HI-508A
IN 6
(11)
IN 7 IN 8
(10) (9)
HI-509A
OUT
(8)
IN 4 IN 3
(7)
(6)
IN 3B IN 4B OUT B
(11) (10)
(9)
OUT A
(8)
IN 4A IN 3A
(7)
(6)
IN 5
(12)
IN 2
(5)
IN 2B
(12)
IN 2A
(5)
+V
(13)
IN 1
(4)
IN 1B
(13)
IN 1A
(4)
GND
(14)
-V
(3)
+V
(14)
-V
(3)
A2
(15)
A1
(16)
A0
(1)
16
EN
(2)
GND
(15)
A1
(16)
A0
(1)
EN
(2)
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.232
-
5.92
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
1.490
-
37.85
5
E
0.500
0.610
15.49
5
eA
ccc M
C A-B S
e
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
12.70
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
-
eA/2
0.300 BSC
7.62 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
N
28
28
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
17
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
-C-
A2
SEATING
PLANE
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MAX
NOTES
-
0.250
-
6.35
4
0.015
-
0.39
-
4
A2
0.125
0.195
3.18
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
0.204
0.381
-
A
L
D1
MIN
A
E
BASE
PLANE
MAX
A1
-AD
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
D
1.380
1.565
D1
0.005
-
35.1
0.13
39.7
5
-
5
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
e
0.100 BSC
2.54 BSC
-
eA
0.600 BSC
15.24 BSC
6
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
N
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
28
28
9
Rev. 1 12/00
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
18
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
eA
ccc M
C A-B S
e
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
N
16
16
8
Rev. 0 4/94
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
19
FN3143.6
October 30, 2007
HI-506A, HI-507A, HI-508A, HI-509A
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.735
0.775
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.204
0.355
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
L
0.115
N
2.54 BSC
-
7.62 BSC
0.430
-
0.150
2.93
16
6
10.92
7
3.81
4
16
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN3143.6
October 30, 2007
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