DATASHEET

HI-518
®
Data Sheet
January 23, 2006
8-Channel/Differential 4-Channel, CMOS
High Speed Analog Multiplexer
The Hl-518 is a monolithic, dielectrically isolated, high
speed, high performance CMOS analog multiplexer. It offers
unique built-in channel selection decoding plus an inhibit
input for disabling all channels. The dual function of address
input A2 enables the Hl-518 to be user programmed either
as a single ended 8-Channel multiplexer by connecting ‘Out
A’ to ‘Out B’ and using A2 as a digital address input, or as a
4-Channel differential multiplexer by connecting A2 to the Vsupply. The substrate leakages and parasitic capacitances
are reduced substantially by using the Intersil Dielectric
Isolation process to achieve optimum performance in both
high and low level signal applications. The low output
leakage current (lD(OFF) < 100pA at 25oC) and fast settling
(tSETTLE = 800ns to 0.01%) characteristics of the device
make it an ideal choice for high speed data acquisition
systems, precision instrumentation, and industrial process
control.
Ordering Information
PART
NUMBER
HI3-0518-5
PART
TEMP.
MARKING RANGE (oC)
HI3-518-5
HI3-0518-5Z HI3-518-5Z
(See Note)
HI1-0518-8
PACKAGE
PKG.
DWG. #
18 Ld PDIP
E18.3
0 to 75
18 Ld PDIP*
(Pb-free)
E18.3
18 Ld CERDIP F18.3
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
Features
• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . 130ns
• Settling Time . . . . . . . . . . . . . . . . . . . . . . . . 250ns (0.1%)
• Low Leakage (Typical)
- IS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pA
- ID(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15pA
• Low Capacitance (Max)
- CS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5pF
- CD(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pF
• Off Isolation at 500kHz . . . . . . . . . . . . . . . . . . 45dB (Min)
• Low Charge Injection Error . . . . . . . . . . . . . . . . . . . 25mV
• Single Ended to Differential Selectable (SDS)
• Logic Level Selectable (LLS)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Data Acquisition Systems
0 to 75
-55 to 125
FN3147.4
• Precision Instrumentation
• Industrial Control
Pinout
HI-518 (CERDIP, PDIP)
TOP VIEW
V+ 1
18 OUT A
OUT B 2
17 V-
IN8/4B 3
16 IN4/4A
IN7/3B 4
15 IN3/3A
IN6/2B 5
14 IN2/2A
IN5/1B 6
13 IN1/1A
GND 7
12 ENABLE
VDD/LLS 8
11 A0
A2/SDS 9
10 A1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-518
Truth Tables
TABLE 2. HI-518 USED AS A DIFFERENTIAL 4-CHANNEL
MULTIPLEXER
TABLE 1. HI-518 USED AS AN 8-CHANNEL MULTIPLEXER
OR DUAL 4-CHANNEL MULTIPLEXER (NOTE 1)
USE A2 AS DIGITAL ADDRESS INPUT
ON CHANNEL TO
ENABLE
A2
A1
A0
OUT A
OUT B
L
X
X
X
None
None
H
L
L
L
1A
None
H
L
L
H
2A
H
L
H
L
H
L
H
H
H
H
L
L
None
1B
H
H
L
H
None
2B
H
H
H
L
None
3B
H
H
H
H
None
4B
A2 CONNECTED TO V- SUPPLY
ENABLE
A1
A0
OUT A
OUT B
L
X
X
None
None
None
H
L
L
1A
1B
3A
None
H
L
H
2A
2B
4A
None
H
H
L
3A
3B
H
H
H
4A
4B
NOTE:
1. For 8-Channel single ended function, tie “Out A” to “Out B”; for
dual 4-Channel function, use the A2 address pin to select
between Mux A and Mux B, where Mux A is selected with A2 low.
Functional Block Diagram
VDD /LLS
IN 1A
N
P
EN
OUT A
A0
DECODER
A1
IN 4A
N
A2
P
Q
A2
DECODER
IN 1B
Q
N
P
OUT B
DECODER
IN 4B
N
INPUT BUFFER AND DECODERS
P
MULTIPLEXER
SWITCHES
A2 DECODE
2
ON CHANNEL TO
A2
Q
Q
H
H
mL
L
L
H
V-
L
L
HI-518
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33V
Analog (VIN, VOUT) . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
Digital Input Voltage:
TTL Levels Selected (VDD/LLS Pin = GND or Open)
VA0-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V
VA2/SDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
CMOS Levels Selected (VDD /LLS Pin = VDD)
VA0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V
Thermal Resistance (Typical, Note 2). . . . θJA (oC/W)
θJC (oC/W)
PDIP Package*. . . . . . . . . . . . . . . . . . .
90
N/A
CERDIP Package. . . . . . . . . . . . . . . . .
70
18
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Ranges
HI-518-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-518-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND
(Note 3), Unless Otherwise Specified
TEST
CONDITIONS
PARAMETER
-8
-5
TEMP
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
25
-
130
175
-
130
175
ns
Full
-
-
225
-
-
225
ns
Break-Before-Make Delay, tOPEN
25
10
20
-
10
20
-
ns
Enable Delay (ON), tON(EN)
25
-
120
175
120
175
ns
ns
Access Time, tA
25
-
140
175
140
175
To 0.1%
25
-
250
-
-
250
-
ns
To 0.01%
25
-
800
-
-
800
-
ns
Enable Delay (OFF), tOFF(EN)
Settling Time
Charge Injection Error
Note 6
25
-
-
25
-
-
25
mV
Off Isolation
Note 7
25
45
-
-
45
-
-
dB
Channel Input Capacitance, CS(OFF)
25
-
-
5
-
-
5
pF
Channel Output Capacitance, CD(OFF)
25
-
-
10
-
-
10
pF
Digital Input Capacitance, CA
25
-
-
5
-
-
5
pF
Input to Output Capacitance, CDS(OFF)
25
-
0.02
-
-
0.02
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, VAL (TTL)
Note 3
Full
-
-
0.8
-
-
0.8
V
Input High Threshold, VAH (TTL)
Note 3
Full
2.4
-
-
2.4
-
-
V
Input Low Threshold, VAL (CMOS)
Note 3
Full
-
-
0.3VDD
-
-
0.3VDD
V
Input High Threshold, VAH (CMOS)
Note 3
Full
0.7VDD
-
-
0.7VDD
-
-
V
Input Leakage Current, IAH (High)
Full
-
-
1
-
-
1
µA
Input Leakage Current, IAL (Low)
Full
-
-
20
-
-
20
µA
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, VIN
Note 4
Full
-14
-
+14
-15
-
+15
V
On Resistance, rON
Note 5
25
-
480
750
-
480
750
Ω
Off Input Leakage Current, lS(OFF)
Off Output Leakage Current, ID(OFF)
On Channel Leakage Current, ID(ON)
Full
-
-
1,000
-
-
1,000
Ω
25
-
0.01
-
-
0.01
-
nA
Full
-
-
50
-
-
50
nA
25
-
0.015
-
-
0.015
-
nA
Full
-
-
50
-
-
50
nA
25
-
0.015
-
-
0.015
-
nA
Full
-
-
50
-
-
50
nA
Full
-
-
450
-
-
540
mW
POWER SUPPLY CHARACTERISTICS
Power Dissipation, PD
3
HI-518
Electrical Specifications
Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND
(Note 3), Unless Otherwise Specified (Continued)
TEST
CONDITIONS
PARAMETER
I+, Current
VEN = 2.4V
I-, Current
-8
-5
TEMP
(oC)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Full
-
-
15
-
-
18
mA
Full
-
-
15
-
-
18
mA
NOTES:
3. VDD /LLS pin = open or grounded for TTL compatibility. VDD /LLS pin = VDD for CMOS compatibility.
4. At temperatures above 90oC, care must be taken to assure VIN remains at least 1.0V below the VSUPPLY for proper operation.
5. VIN = ±10V, IOUT = -100µA.
6. VIN = 0V, CL = 100pF, enable input pulse = 3V, f = 500kHz.
7. CL = 40pF, RL = 1K, VEN = 0.8V, VIN = 3VRMS , f = 500kHz. Due to the pin to pin capacitance between IN 8/4B and OUT B, channel 8/4B
exhibits 60dB of OFF isolation under the above test conditions.
Test Circuits and Waveforms
VDD /LLS = GND, Unless Otherwise Specified
IOUT 100µA
0.8V
EN
V2
OUT
IN
VIN
V2
±10V
±
±10V
A ID(OFF)
OUT
rON =
100µA
10V
FIGURE 2. ID(OFF) TEST CIRCUIT (NOTE 8)
FIGURE 1. ON RESISTANCE TEST CIRCUIT
OUT
OUT
IS(OFF) A
EN
EN
A2
10V
±
±10V
0.8V
A ID(ON)
A0
±10V
10V
±
2.4V
FIGURE 3. IS(OFF) TEST CIRCUIT (NOTE 8)
FIGURE 4. ID(ON) TEST CIRCUIT (NOTE 8)
+15V
V+
ADDRESS
DRIVE (VA)
IN 1
50%
A2 /SDS
0V
VA
50Ω
+10V
OUTPUT
10%
2.4V
tA
IN 2-7
A1
A0
IN 8
OUTA
EN
OUTB
VDD/LLS
-10V
±10V
±
3.5V
V-
GND
-15V
FIGURE 5A. MEASUREMENT POINTS
FIGURE 5B. TEST CIRCUIT
FIGURE 5. ACCESS TIME
NOTE:
8. Two measurements per channel: ±10V and 10V. (Two measurements per device for ID(OFF) ±10V and 10V.)
4
10V
10
kΩ
50
pF
HI-518
Test Circuits and Waveforms
VDD /LLS = GND, Unless Otherwise Specified (Continued)
+15V
3.5V
V+
IN 2-7
0V
VA
50Ω
OUTPUT
S1 ON 50%
+5V
IN 1
A2 /SDS
ADDRESS
DRIVE (VA)
50% S8 ON
2.4V
A1
IN 8
A0
OUTA
EN
OUTB
VDD /LLS
tOPEN
V-
VOUT
800
Ω
12.5pF
GND
-15V
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6B. TEST CIRCUIT
FIGURE 6. BREAK-BEFORE-MAKE DELAY
+15V
3.5V
V+
50%
50%
ENABLE
DRIVE (VA)
OUTPUT
90%
+10V
IN 1
A2 /SDS
0V
IN 2-8
A1
A0
10%
0V
tON(EN)
VA
tOFF(EN)
EN
VDD /LLS
50
Ω
OUTA
V-
GND
800
Ω
12.5pF
-15V
FIGURE 7A. MEASUREMENT POINTS
FIGURE 7B. TEST CIRCUIT
FIGURE 7. ENABLE DELAY
+15V
2.4V
V+
A0 , A 1 ,
A2 /SDS
3V
0V
VA
OUT
∆VO
VOUT
IN
VOUT
A OR B
CL = 100pF
EN
VA
GND
VDD /LLS
V-
-15V
FIGURE 8A. MEASUREMENT POINTS
∆VO is the measured voltage error due to charge injection. The error
in coulombs is Q = CL x ∆VO .
FIGURE 8. CHARGE INJECTION
5
FIGURE 8B. TEST CIRCUIT
HI-518
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
89 mils x 93 mils
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1.0kÅ
Silox Thickness: 12kÅ ±2.0kÅ
METALLIZATION:
Type: AlCu
Thickness: 16kÅ ±2kÅ
WORST CASE CURRENT DENSITY:
1.43 x 105 A/cm2
SUBSTRATE POTENTIAL (NOTE):
TRANSISTOR COUNT:
-VSUPPLY
356
PROCESS:
CMOS-DI
NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a
conductor at -VSUPPLY potential.
Metallization Mask Layout
HI-518
EN
A0
A1
A2/SDS
VDD /LLS
GND
IN 1/1A
IN 5/1B
IN 2/2A
IN 6/2B
IN 3/3A
IN 7/3B
IN 4/4A
IN 8/4B
V-
6
OUT A
V+
OUT B
HI-518
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F18.3 MIL-STD-1835 GDIP1-T18 (D-6, CONFIGURATION A)
18 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
LEAD FINISH
c1
-D-
-A-
BASE
METAL
E
M
-Bbbb S
C A-B S
-C-
S1
0.200
-
5.08
-
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.960
-
24.38
5
E
0.220
0.310
5.59
7.87
5
eA
ccc M
C A-B S
e
eA/2
c
aaa M C A - B S D S
D S
NOTES
-
b2
b
MAX
0.014
α
A A
MIN
b
A
L
MILLIMETERS
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
SYMBOL
b1
SECTION A-A
D S
INCHES
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.070
0.38
1.78
6
S1
0.005
-
0.13
-
7
105o
90o
105o
-
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
α
90o
aaa
-
0.015
-
0.38
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
7
N
18
18
8
Rev. 0 4/94
HI-518
Dual-In-Line Plastic Packages (PDIP)
E18.3 (JEDEC MS-001-BC ISSUE D)
N
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
C
D
0.845
0.880
21.47
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.204
0.355
22.35
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
eB
-
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
L
0.115
N
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
18
10.92
3.81
18
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7
4
9
Rev. 2 11/03
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3
may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
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