DATASHEET

CD4049UBMS
®
Data Sheet
March 6, 2007
FN3315.1
CMOS Hex Buffer/Converter
Features
The CD4049UBMS is an inverting hex buffer and features
logic level conversion using only one supply (voltage (VCC).
The input signal high level (VIH) can exceed the VCC supply
voltage when this device is used for logic level conversions.
This device is intended for use as CMOS to DTL/TTL
converters and can drive directly two DTL/TTL loads.
(VCC = 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.
• High Voltage Type (20V Rating)
The CD4049UBMS is designated as replacement for
CD4009UB. Because the CD4049UBMS requires only one
power supply, it is preferred over the CD4009UB and
CD4010B and should be used in place of the CD4009UB in
all inverter, current driver, or logic level conversion
applications. In these applications the CD4049UBMS is pin
compatible with the CD4009UB, and can be substituted for
this device in existing as well as in new designs. Terminal
No. 16 is not connected internally on the CD4049UBMS,
therefore, connection to this terminal is of no consequence
to circuit operation. For applications not requiring high sink
current or voltage conversion, the CD4069UB Hex Inverter is
recommended.
• Maximum Input Current of 1mA at 18V Over Full Package
Temperature Range; 100nA at 18V and +25°C
• Inverting Type
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
Applications
• CMOS to DTL/TTL Hex Converter
• CMOS Current “Sink” or “Source” Driver
• CMOS High-to-Low Logic Level Converter
Pinout
CD4049UBMS
TOP VIEW
The CD4049UBMS is supplied in these 16 lead outline
packages:
VCC
1
16 NC
G=A
2
15 L = F
Braze Seal DIP
H4S
A
3
14 F
Frit Seal DIP
H1E
H=B
4
13 NC
Ceramic Flatpack H3X
B
5
12 K = E
I=C
6
11 E
C
7
10 J = D
VSS
8
Functional Diagram
3
2
5
4
7
6
9
10
11
12
A
B
9 D
G=A
H=B
Schematic
VCC
C
D
VCC
VSS
NC = 13
NC = 16
I=C
J=D
1
8
P
E
F
14
15
K=E
L=F
R
IN
OUT
N
VSS
FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CD4049UBMS
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
PKG.
DWG. #
CD4049UBDMSR
Q 5962R96 63601VEC
-55 to +125
16 Ld SBDIP, Solder Seal
D16.3
CD4049UBKMSR
Q 5962R96 63601VXC
-55 to +125
16 Ld Flatpack, Solder Seal
K16.A
CD4049UBKNSR
Q 5962R96 63602VXC
-55 to +125
16 Ld Flatpack, Solder Seal
K16.A
2
FN3315.1
March 6, 2007
CD4049UBMS
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . . . . . . -0.5V to 20.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Temperature Range . . . . . . . . . . . . . . . .-55°C to +125°C
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . .-65°C to +150°C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . +265°C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance (Typical)
θJA (°C/W)
θJC (°C/W)
Ceramic DIP and FRIT Package . . . . .
80
20
Flatpack Package. . . . . . . . . . . . . . . . .
70
20
Maximum Package Power Dissipation (PD) at +125°C
For TA = -55°C to +100°C (Package Type D, F, K) . . . . . .500mW
For TA = +100°C to +125°C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/°C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . .100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
DC Electrical Specifications
PARAMETER
Supply Current
Input Leakage
Current
Input Leakage
Current
CONDITIONS
(Note 1)
TEMP (°C)
MIN
MAX
UNITS
1
+25
-
2
μA
2
+125
-
200
μA
VDD = 18V, VIN = VDD or GND
3
+55
-
2
μA
VIN = VDD or GND
1
+25
-100
-
nA
2
+125
-1000
-
nA
VDD = 18V
3
-55
-100
-
nA
VDD = 20
1
+25
-
100
nA
2
+125
-
1000
nA
3
+55
-
100
nA
SYMBOL
IDD
IIL
IIH
LIMITS
GROUP A
SUBGROUPS
VDD = 20V, VIN = VDD or GND
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25, +125, -55
-
50
mV
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25, +125, -55
14.95
-
V
Output Current
(Sink)
IOL4
VDD = 4.5V, VOUT = 0.4V
1
+25
2.6
-
mA
Output Current
(Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25
3.2
-
mA
Output Current
(Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25
8.0
-
mA
Output Current
(Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25
24
-
mA
Output Current
(Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25
-
-0.8
mA
Output Current
(Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25
-
-3.2
mA
Output Current
(Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25
-
-1.8
mA
Output Current
(Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25
-
-6.0
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10μA
1
+25
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10μA
1
+25
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25
VDD = 20V, VIN = VDD or GND
7
+25
VDD = 18V, VIN = VDD or GND
8A
+125
VDD = 3V, VIN = VDD or GND
8B
-55
Functional
F
3
VOH > VDD/2 VOL < VDD/2
V
FN3315.1
March 6, 2007
CD4049UBMS
DC Electrical Specifications
PARAMETER
CONDITIONS
(Note 1)
SYMBOL
LIMITS
GROUP A
SUBGROUPS
TEMP (°C)
MIN
MAX
UNITS
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25, +125, -55
-
1.0
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25, +125, -55
4.0
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V, VOL < 1.5V
1, 2, 3
+25, +125, -55
-
2.5
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V, VOL < 1.5V
1, 2, 3
+25, +125, -55
12.5
-
V
NOTES:
1. All voltages referenced to device GND, 100% testing being implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
AC Electrical Specifications
PARAMETER
SYMBOL
Propagation Delay
tPHL
Propagation Delay
tPLH
Transition Time
tTHL
Transition Time
tTLH
CONDITIONS
(Notes 4, 5)
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
VDD = 5V, VIN = VDD or GND
LIMITS
GROUP A
SUBGROUPS
TEMP (°C)
MIN
MAX
UNITS
9
+25
-
65
ns
10, 11
+125, -55
-
88
ns
9
+25
-
120
ns
10, 11
+125, -55
-
162
ns
9
+25
-
60
ns
10, 11
+125, -55
-
81
ns
9
+25
-
160
ns
10, 11
+125, -55
-
216
ns
NOTES:
4. CL = 50pF, RL = 200k, Input tR, tF < 20ns.
5. -55°C and +125°C limits guaranteed, 100% testing being implemented.
Post Irradiation Electrical Performance Characteristics
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
NOTES
TEMP (°C)
MIN
MAX
UNITS
6, 7
-55, +25
-
1
μA
+125
-
30
μA
-55, +25
-
2
μA
+125
-
60
μA
-55, +25
-
2
μA
+125
-
120
μA
6, 7
6, 7
Output Voltage
VOL
VDD = 5V, No Load
6, 7
+25, +125, -55
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
6, 7
+25, +125, -55
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
6, 7
+25, +125, -55
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
6, 7
+25, +125, -55
9.95
-
V
4
FN3315.1
March 6, 2007
CD4049UBMS
Post Irradiation Electrical Performance Characteristics
LIMITS
PARAMETER
SYMBOL
Output Current (Sink)
IOL4
Output Current (Sink)
IOL5
Output Current (Sink)
IOL10
Output Current (Sink)
IOL15
Output Current (Source)
IOH5A
Output Current (Source)
IOH5B
Output Current (Source)
IOH10
Output Current (Source)
IOH15
CONDITIONS
VDD = 4.5V, VOUT = 0.4V
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
NOTES
TEMP (°C)
MIN
MAX
UNITS
6, 7
+125
1.8
-
mA
-55
3.3
-
mA
+125
2.4
-
mA
-55
4.0
-
mA
+125
5.6
-
mA
-55
10
-
mA
+125
18
-
mA
-55
26
-
mA
+125
-
-0.48
mA
-55
-
-0.81
mA
+125
-
-1.55
mA
-55
-
-2.6
mA
+125
-
-1.18
mA
-55
-
-2.0
mA
+125
-
-3.1
mA
-55
-
-5.2
mA
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
6, 7
+25, +125, -55
-
2
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
6, 7
+25, +125, -55
8
-
V
Propagation Delay
tPHL
VIN = 10V, VDD = 5V
6, 7, 8
+25
-
30
ns
VIN = 10V, VDD = 10V
6, 7, 8
+25
-
40
ns
VIN = 10V, VDD = 5V
6, 7, 8
+25
-
90
ns
VIN = 10V, VDD = 10V
6, 7, 8
+25
-
65
ns
VIN = 15V, VDD = 5V
6, 7, 8
+25
-
20
ns
VIN = 15V, VDD = 15V
6, 7, 8
+25
-
30
ns
VIN = 15V, VDD = 5V
6, 7, 8
+25
-
90
ns
VIN = 15V, VDD = 15V
6, 7, 8
+25
-
50
ns
VDD = 10V, VIN = VDD OR GND
6, 7, 8
+25
-
40
ns
VDD = 15V, VIN = VDD OR GND
6, 7, 8
+25
-
30
ns
VDD = 10V, VIN = VDD OR GND
6, 7, 8
+25
-
80
ns
VDD = 15V, VIN = VDD OR GND
6, 7, 8
+25
-
60
ns
6, 7
+25
-
22.5
pF
Propagation Delay
tPLH
Propagation Delay
tPHL
Propagation Delay
tPLH
Transition Time
tTHL
Transition Time
tTLH
Input Capacitance
CIN
Any Input
NOTES:
6. All voltages referenced to device GND.
7. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
8. CL = 50pF, RL = 200k, Input tR, tF < 20ns.
5
FN3315.1
March 6, 2007
CD4049UBMS
Post Irradiation Electrical Performance Characteristics
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMP (°C)
MIN
MAX
UNITS
IDD
VDD = 20V, VIN = VDD or GND
9, 12
+25
-
7.5
μA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10μA
9, 12
+25
-2.8
-0.2
V
N Threshold Voltage
Delta
ΔVTND
VDD = 10V, ISS = -10μA
9, 12
+25
-
±1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10μA
9, 12
+25
0.2
2.8
V
P Threshold Voltage
Delta
ΔVTPD
VSS = 0V, IDD = 10μA
9, 12
+25
-
±1
V
9
+25
9, 10, 11, 12
+25
Functional
F
VDD = 18V, VIN = VDD or GND
VOH > VDD/2 VOL < VDD/2
V
VDD = 3V, VIN = VDD or GND
tPHL
tPLH
Propagation Delay
Time
VDD = 5V
-
1.35 x +25
Limit
ns
NOTES:
9. All voltages referenced to device GND.
10. CL = 50pF, RL = 200k, Input tR, tF < 20ns.
11. See Table 2 for +25°C limit.
12. Read and Record
TABLE 1. BURN-IN AND LIFE TEST DELTA PARAMETERS +25°C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD
± 0.2μA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 2. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
CONFORMANCE GROUP
PDA (Note 13)
Interim Test 3 (Post Burn-In)
PDA (Note 13)
Group B
Group D
READ AND RECORD
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTES:
13. 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
6
FN3315.1
March 6, 2007
CD4049UBMS
TABLE 3. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
Group E Subgroup 2
TABLE 4. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1 (Note 14)
2, 4, 6, 10, 12, 13, 15
3, 5, 7-9, 11-14
1, 16
Static Burn-In 2 (Note 14)
2, 4, 6, 10, 12, 13, 15
8
1, 3, 5, 7, 9, 11, 14, 16
13
8
1, 16
2, 4, 6, 10, 12, 13, 15, 16
8
1, 3, 5, 7, 9, 11, 14
Dynamic Burn-In
(Note 16)
Irradiation (Note 15)
9V ± -0.5V
50kHz
2, 4, 6, 10, 12, 15
3, 5, 7, 9, 11, 14
25kHz
NOTES:
14. Each pin except pin 1, pin 16, and GND will have a series resistor of 10k ± 5%, VDD = 18V ± 0.5V
15. Each pin except pin 1, pin 16, and GND will have a series resistor of 47k ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
16. Each pin except pin 1, pin 16, and GND will have a series resistor of 4.75k ± 5%, VDD = 18V ± 0.5V
Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT VOLTAGE (VO) (V)
AMBIENT TEMPERATURE (TA) = +25°C
SUPPLY VOLTAGE (VCC) = 5V
5
4
MINIMUM
MAXIMUM
3
2
AMBIENT TEMPERATURE (TA) = +25°C
70
15V
10V
60
50
40
30
GATE-TO-SOURCE VOLTAGE (VGS) = 5V
20
10
1
0
1
2
3
INPUT VOLTAGE (VI) (V)
4
FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER
CHARACTERISTICS
7
0
1
2
3
4
5
6
7
8
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FN3315.1
March 6, 2007
CD4049UBMS
Typical Performance Characteristics (Continued)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
AMBIENT TEMPERATURE (TA) = +25°C
-7
-6
-5
-4
-3
-2
0
-1
AMBIENT TEMPERATURE (TA) = +25°C
-5
70
15V
10V
-10
GATE-TO-SOURCE VOLTAGE (VGS) = 5V
60
50
-15
40
-20
-25
30
-10V
-30
20
GATE-TO-SOURCE VOLTAGE (VGS) = 5V
-35
10
-15V
0
1
2
3
4
5
6
7
OUTPUT HIGH (SINK) CURRENT (IOH) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
-8
8
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN
CHARACTERISTICS
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-6
-5
-4
-3
-2
-1
0
AMBIENT TEMPERATURE (TA) = +25°C
-5
GATE-TO-SOURCE VOLTAGE (VGS) = 5V
-10
-10V
-15
-15V
-20
-25
-30
-35
10
OUTPUT VOLTAGE (VO) (V)
-7
OUTPUT HIGH (SINK) CURRENT (IOH) (mA)
-8
SUPPLY VOLTAGE (VCC) = 10V
9
AMBIENT TEMPERATURE (TA) = -55°C
8
+125°C
7
6
VCC = 5V
-55°C
5
4
+125°C
3
2
1
0
1
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE (VI) (V)
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
8
FIGURE 7. TYPICAL VOLTAGE TRANSFER
CHARACTERISTICS AS A FUNCTION OF
TEMPERATURE
FN3315.1
March 6, 2007
CD4049UBMS
105
AMBIENT TEMPERATURE (TA)
8 = +25oC
6
4
2
SUPPLY VOLTAGE
104
(VDD) = 15V
8
6
4
10V
2
103
8
10V
6
4
5V
2
102
8
6
LOAD CAPACITANCE (CL) = 50pF
4
(11pF FIXTURE + 39pF EXT)
2
CL = 15pF (11pF FIXTURE + 4pF EXT
10
2 4 68
2 4 6 8
2 4 68
2 4 68
10
103
104
105
102
INPUT FREQUENCY (f) (kHz)
FIGURE 8. TYPICAL POWER DISSIPATION vs FREQUENCY
CHARACTERISTICS
POWER DISSIPATION PER INVERTER (PD) (μW)
POWER DISSIPATION PER INVERTER (mW)
Typical Performance Characteristics (Continued)
106
AMBIENT TEMPERATURE (TA) = +25oC
105
15V; 1MHz
104
15V; 100KHz
10V; 100KHz
103
15V; 10KHz
102
10
1
10
10V; 10KHz
15V; 1KHz
SUPPLY VOLTAGE (VCC) = 5V
FREQUENCY (f) = 10KHz
102
103
104
105
106
107
INPUT RISE AND FALL TIME (tr, tf) (ns)
108
FIGURE 9. TYPICAL POWER DISSIPATION vs INPUT RISE
AND FALL TIMES PER INVERTER
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived
from the basic inch dimensions as indicated. Grid
graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ,
AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches
9
FN3315.1
March 6, 2007
CD4049UBMS
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
LEAD FINISH
c1
-A-
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-DBASE
METAL
E
b1
M
(b)
M
-Bbbb S C A - B S
(c)
SECTION A-A
D S
D
BASE
PLANE
Q
S2
-C-
SEATING
PLANE
A
L
S1
eA
A A
b2
b
e
eA/2
c
aaa M C A - B S D S
ccc M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
INCHES
SYMBOL
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2
N
16
16
8
Rev. 0 4/94
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN3315.1
March 6, 2007
CD4049UBMS
Ceramic Metal Seal Flatpack Packages (Flatpack)
K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B)
A
e
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
INCHES
PIN NO. 1
ID AREA
SYMBOL
-A-
D
-B-
S1
b
E1
0.004 M
H A-B S
Q
D S
0.036 M
H A-B S
D S
C
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
BASE
METAL
(c)
b1
M
M
(b)
SECTION A-A
NOTES:
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.440
-
11.18
3
E
0.245
0.285
6.22
7.24
-
E1
-
0.315
-
8.00
3
E2
0.130
-
3.30
-
-
E3
0.030
-
0.76
-
7
2
e
LEAD FINISH
MIN
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
16
16
Rev. 1 2-20-95
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH
11
FN3315.1
March 6, 2007
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