CD4050BMS TM Data Sheet December 1992 FN3193 CMOS Hex Buffer/Converter Features The CD4050BMS is an non-inverting hex buffer and features logic level conversion using only one supply voltage (VCC). The input signal high level (VIH) can exceed the VCC supply voltage when this device is used for logic level conversions. This device is intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (VCC = 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA. • High Voltage Type (20V Rating) The CD4050BMS is designated as replacement for CD4010B. Because the CD4050BMS requires only one power supply, it is preferred over the CD4010B and should be used in place of the CD4010B in all inverter, current driver, or logic level conversion applications. In these applications the CD4050BMS is pin compatible with the CD4010B, and can be substituted for this device in existing as well as in new designs. Terminal No. 16 is not connected internally on the CD4050BMS, therefore, connection to this terminal is of no consequence to circuit operation. For applications not requiring high sink current or voltage conversion, the CD4069UB Hex Inverter is recommended. • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC The CD4050BMS is supplied in these 16 lead outline packages: CD4050BMS TOP VIEW • Non-Inverting Type • High Sink Current for Driving 2 TTL Loads • High-to-Low Level Logic Conversion • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings Applications • CMOS to DTL/TTL Hex Converter • CMOS Current “Sink” or “Source” Driver • CMOS High-to-Low Logic Level Converter Pinout Braze Seal DIP H4T VCC 1 16 NC Frit Seal DIP H1E G=A 2 15 L = F A 3 14 F H=B 4 13 NC B 5 12 K = E I=C 6 11 E C 7 10 J = D VSS 8 Ceramic Flatpack H3X Functional Diagram 9 D Schematic Diagram A B 3 2 5 4 7 6 VCC G=A H=B P C 9 10 11 12 D VCC VSS NC = 13 NC = 16 I=C P R OUT IN N N J=D 1 8 E F 14 4-1 15 K=E VSS FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS L=F CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved TM 4-2 CD4050BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . .+265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W Flatpack Package. . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 2 µA 2 +125oC - 200 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 2 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 20 VIN = VDD or GND 3 -55oC - 100 nA Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V 1 +25oC 2.6 - mA VDD = 18V Output Current (Sink) IOL4 VDD = 4.5V, VOUT = 0.4V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 3.2 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 8.0 - mA 1 +25oC 24 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.8 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -3.2 mA 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -6.0 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V VOH > VDD/2 VOL < VDD/2 V P Threshold Voltage Functional VPTH F VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 4-3 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. CD4050BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Propagation Delay Transition Time Transition Time SYMBOL TPHL TPLH TTHL TTLH CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9 +25oC - 110 ns 10, 11 +125oC, -55oC - 149 ns 9 +25oC - 140 ns 10, 11 +125oC, -55oC - 189 ns 9 +25oC - 60 ns 10, 11 +125oC, -55oC - 81 ns 9 +25oC - 160 ns 10, 11 +125oC, -55oC - 216 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 2 -55oC, +25oC µA 1, 2 1, 2 - 1 +125oC - 30 µA -55oC, +25oC - 2 µA +125oC - 60 µA -55oC, +25oC - 2 µA +125oC - 120 µA - 50 mV Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, 55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC 9.95 - V Output Current (Sink) IOL4 VDD = 4.5V, VOUT = 0.4V 1, 2 +125oC 1.8 - mA -55oC 3.3 - mA +125oC 2.4 - mA -55oC 4.0 - mA +125oC 5.6 - mA -55oC 10 - mA +125oC 18 - mA -55oC 26 - mA +125oC - -0.48 mA -55oC - -0.81 mA +125oC - -1.55 mA -55oC mA Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 4-4 VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 - -2.6 +125oC - -1.18 mA -55oC - -2.0 mA +125oC - -3.1 mA -55oC - -5.2 mA CD4050BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS NOTES TEMPERATURE MIN MAX UNITS Input Voltage Low PARAMETER SYMBOL VIL VDD = 10V, VOH > 9V, VOL < 1V CONDITIONS 1, 2 +25oC, +125oC, 55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 55oC +7 - V Propagation Delay TPHL 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 55 ns VIN = 10V, VDD = 5V 1, 2, 3 +25oC - 90 ns VIN = 10V, VDD = 10V 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC - 100 ns VIN = 15V, VDD = 15V 1, 2, 3 +25oC - 30 ns VIN = 15V, VDD = 5V 1, 2, 3 +25oC - 80 ns VIN = 15V, VDD = 15V 1, 2, 3 +25oC - 60 ns VDD = 10V, VIN = VDD OR GND 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC - 30 ns VDD = 10V, VIN = VDD OR GND 1, 2, 3 +25oC - 80 ns VDD = 15V, VIN = VDD OR GND 1, 2, 3 +25oC - 60 ns 1, 2 +25oC - 7.5 pF VIN = 10V, VDD = 5V VIN = 10V, VDD = 10V Propagation Delay Propagation Delay Propagation Delay Transition Time TPLH TPHL TPLH TTHL VIN = 15V, VDD = 5V VDD = 15V, VIN = VDD OR GND Transition Time Input Capacitance TTLH CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage SYMBOL IDD CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 7.5 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VDD = 20V, VIN = VDD or GND VNTH VDD = 10V, ISS = -10µA N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 4-5 CD4050BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD CONFORMANCE GROUP GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Final Test Group A Group B IDD, IOL5, IOH5A Group D Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parametric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 2, 4, 6, 10, 12, 13, 15 3, 5, 7-9, 11-14 1, 16 Static Burn-In 2 (Note 1) 2, 4, 6, 10, 12, 13, 15 8 1, 3, 5, 7, 9, 11, 14, 16 Dynamic Burn-In (Note 3) 13 8 1, 16 2, 4, 6, 10, 12, 13, 15, 16 8 1, 3, 5, 7, 9, 11, 14 Irradiation (Note 2) 9V ± -0.5V 50kHz 2, 4, 6, 10, 12, 15 3, 5, 7, 9, 11, 14 25kHz NOTES: 1. Each pin except pin 1, pin 16, and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except pin 1, pin 16, and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 3. Each pin except pin 1, pin 16, and GND will have a series resistor of 4.75K ± 5%, VDD = 10V ± 0.5V Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT VOLTAGE (VO) (V) AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VCC) = 5V 5 4 MAXIMUM MINIMUM 3 2 AMBIENT TEMPERATURE (TA) = +25oC 70 15V 10V 60 50 40 30 GATE-TO-SOURCE VOLTAGE (VGS) = 5V 20 10 1 0 1 2 3 4 INPUT VOLTAGE (VI) (V) FIGURE 2. MINIMUM AND MAXIMUM VOLTAGE TRANSFER CHARACTERISTICS 4-6 0 1 2 3 4 5 6 7 8 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS CD4050BMS Typical Performance Characteristics (Continued) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -8 70 15V -7 -6 -5 -4 -3 -2 -1 0 AMBIENT TEMPERATURE (TA) = +25oC 10V 60 -5 50 -10 GATE-TO-SOURCE VOLTAGE (VGS) = 5V 40 -15 30 -20 -25 20 GATE-TO-SOURCE VOLTAGE (VGS) = 5V -10V -30 10 0 1 -35 2 3 4 5 6 7 8 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15V FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT DRAIN CHARACTERISTICS FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -7 -6 -5 -4 -3 -2 SUPPLY VOLTAGE (VCC) = 10V -1 0 -5 GATE-TO-SOURCE VOLTAGE (VGS) = 5V -10 -10V -15 -15V -20 -25 -30 -35 AMBIENT TEMP (TA) = -55oC 10 OUTPUT HIGH (SINK) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT VOLTAGE (VO) (V) -8 OUTPUT HIGH (SINK) CURRENT (IOH) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC 9 +125 oC 8 7 VCC = 5V 6 5 -55oC 4 +125oC 3 2 1 0 1 2 3 4 5 6 7 8 9 10 INPUT VOLTAGE (VI) (V) 10 5 8 6 4 FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AS A FUNCTION OF TEMPERATURE AMBIENT TEMPERATURE (TA) = +25 oC 2 SUPPLY VOLTAGE (VDD) = 15V 10 4 8 6 4 10 3 10V 2 8 6 4 10V 5V 2 10 2 8 6 4 LOAD CAPACITANCE (CL) = 50pF (11pF FIXTURE + 39pF EXT) CL = 15pF (11pF FIXTURE + 4pF EXT 2 10 2 10 4 6 8 2 4 6 8 102 10 3 2 4 6 8 104 2 4 6 8 10 5 POWER DISSIPATION PER INVERTER (PD) (µW) POWER DISSIPATION PER INVERTER (µW) FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 106 AMBIENT TEMPERATURE (T ) = +25 oC A 105 15V; 1MHz 104 15V; 100KHz 103 10V; 100KHz 15V; 10KHz 102 10 1 10 10V; 10KHz 15V; 1KHz SUPPLY VOLTAGE (VCC) = 5V FREQUENCY (f) = 10KHz 103 10 4 105 106 107 102 INPUT RISE AND FALL TIME (tr, tf) (ns) 10 8 INPUT FREQUENCY (f) (kHz) FIGURE 8. TYPICAL POWER DISSIPATION vs FREQUENCY CHARACTERISTICS 4-7 FIGURE 9. TYPICAL POWER DISSIPATION vs INPUT RISE AND FALL TIMES PER INVERTER CD4050BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 4-8