DATASHEET

HCS163MS
Radiation Hardened
Synchronous Presettable Counter
September 1995
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x
1012
RAD (Si)/s
• Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
MR 1
16 VCC
CP 2
15 TC
P0 3
14 Q0
P1 4
13 Q1
P2 5
12 Q2
P3 6
11 Q3
PE 7
10 TE
9
GND 8
SPE
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC
- VIH = 70% of VCC
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
MR
1
16
VCC
The Intersil HCS163MS is a Radiation Hardened synchronous
presettable binary counter that features lookahead carry logic for
use in high speed counting applications. Counting and parallel
load, and presetting are all accomplished synchronously with the
positive transition of the clock.
CP
2
15
TC
P0
3
14
Q0
P1
4
13
Q1
P2
5
12
Q2
P3
6
11
Q3
The HCS163MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
PE
7
10
TE
GND
8
9
SPE
The HCS163MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCS163DMSR
-55oC to +125oC
Intersil Class S Equivalent
16 Lead SBDIP
HCS163KMSR
-55oC to +125oC
Intersil Class S Equivalent
16 Lead Ceramic Flatpack
+25oC
Sample
16 Lead SBDIP
HCS163K/Sample
+25oC
Sample
16 Lead Ceramic Flatpack
HCS163HMSR
+25oC
Die
Die
DB NA
HCS163D/Sample
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
220
Spec Number
File Number
518835
3087.1
HCS163MS
Functional Block Diagram
P0
P1
3
4
Q0 Q1
P3
P2
Q2 Q3
6
5
7
PE
10
TE
TE
TE
9
SPE
P
1
D0
T0
MR
VCC
P
Q0
MR
CP
D1
Q1
P
D2
P
Q2
D3
T1
T2
T3
MR
CP
MR
CP
MR
CP
Q3
2
CP
14
13
Q1
Q0
12
15
TC
11
Q2
Q3
TRUTH TABLE
INPUTS
OPERATING MODE
MR
CP
OUTPUTS
PE
TE
SPE
PN
QN
TC
Reset (clear)
l
X
X
X
X
L
L
Parallel Load
h (Note 3)
X
X
l
l
L
L
h (Note 3)
X
X
l
h
H
(Note 1)
Count
h (Note 3)
h
h
h (Note 3)
X
Count
(Note 1)
Inhibit
h (Note 3)
X
l (Note 2)
X
h (Note 3)
X
Qn
(Note 1)
h (Note 3)
X
X
l (Note 2)
h (Note 3)
X
Qn
L
H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial
q = Lower case letter indicate the state of the referenced output prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
NOTES:
1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HLLH for 162 and HHHH for 163)
2. The HIGH-to-LOW transition of PE or TE on the 54/74163 and 54/74160 should only occur while CP is high for conventional operation
3. The LOW-to-HIGH transition of SPE or MR on the 54/74163 should only occur while CP is high for conventional operation
Spec Number
221
518835
Specifications HCS163MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA
θJC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
73oC/W
24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W
29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5 VCC (TR, TF) . . . . . . . .100ns Max
Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
Output Current
(Sink)
Output Current
(Source)
Output Voltage Low
Output Voltage High
Input Leakage
Current
Noise Immunity
Functional Test
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
40
µA
2, 3
+125oC, -55oC
-
750
µA
1
+25oC
4.8
-
mA
2, 3
+125oC, -55oC
4.0
-
mA
1
+25oC
-4.8
-
mA
2, 3
+125oC, -55oC
-4.0
-
mA
VCC = 4.5V, VIH = 3.15V,
IOL = 50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 5.5V, VIH = 3.85V,
IOL = 50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
-
0.1
V
VCC = 4.5V, VIH = 3.15V,
IOH = -50µA, VIL = 1.35V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 3.85V,
IOH = -50µA, VIL = 1.65V
1, 2, 3
+25oC, +125oC, -55oC
VCC
-0.1
-
V
VCC = 5.5V, VIN = VCC or
GND
1
+25oC
-
±0.5
µA
2, 3
+125oC, -55oC
-
±5.0
µA
7, 8A, 8B
+25oC, +125oC, -55oC
-
-
-
(NOTE 1)
CONDITIONS
SYMBOL
ICC
IOL
IOH
VOL
VOH
IIN
FN
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V ,
(Note 2)
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V, (Note 2)
VCC = 4.5V, VIH = 3.15V,
VIL = 1.35V, (Note 3)
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. Force/Measure functions may be interchanged.
3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
Spec Number
222
518835
Specifications HCS163MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
Propagation Delay
CP to Qn
Propagation Delay
CP to TC
Propagation Delay
TE to TC
TPHL,
TPLH
TPHL,
TPLH
TPHL,
TPLH
GROUP
A SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
9
+25oC
2
26
ns
10, 11
+125oC, -55oC
2
31
ns
9
+25oC
2
29
ns
10, 11
+125oC, -55oC
2
34
ns
9
+25oC
2
21
ns
10, 11
+125oC, -55oC
2
23
ns
VCC = 4.5V
VCC = 4.5V
VCC = 4.5V
LIMITS
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Capacitance Power Dissipation
Input Capacitance
Pulse Width Time CP(L)
Pulse Width Time MR
Setup Time SPE, Pn to CP
Setup Time PE, TE to CP
Setup Time MR to CP
Hold Time Pn to CP
Hold Time TE, PE, SPE to CP
Removal Time
MR to CP
Maximum
Frequency
SYMBOL
CPD
CIN
TW
TW
TSU
TSU
TSU
TH
TH
TREM
FMAX
(NOTE 1)
CONDITIONS
VCC = 5.0V, VIH = 5.0V,
VIL = 0.0V, f = 1MHz
VCC = 5.0V, VIH = 5.0V,
VIL = 0.0V, f = 1MHz
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
VCC = 4.5V, VIH = 4.5V,
VIL = 0.0V
LIMITS
TEMPERATURE
MIN
MAX
UNITS
+25oC
-
68
pF
-
83
pF
-
10
pF
-
10
pF
16
-
ns
24
-
ns
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
20
ns
30
ns
12
ns
18
ns
10
ns
15
ns
13
ns
20
ns
3
-
ns
3
-
ns
0
-
ns
0
-
ns
15
-
ns
22
-
ns
30
-
MHz
24
-
MHz
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
223
518835
Specifications HCS163MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
200K RAD
LIMITS
PARAMETER
(NOTES 1, 2)
CONDITIONS
SYMBOL
TEMPERATURE
MIN
MAX
UNITS
Supply Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25oC
-
0.75
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25oC
4.0
-
mA
Output Current
(Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25oC
-4.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V , VIH = 3.15,
VIL = 1.35V, IOL = 50µA
+25oC
-
0.1
V
VCC = 5.5V, VIH = 3.85,
VIL = 1.65V, IOL = 50µA
+25oC
-
0.1
V
VCC = 4.5V, VIH = 3.15V,
VIL =1.35V, IOH = -50µA
+25oC
VCC
-0.1
-
V
VCC = 5.5V, VIH = 3.85V,
VIL =1.65V, IOH = -50µA
+25oC
VCC
-0.1
-
V
Output Voltage High
VOH
Input Leakage Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25oC
-
±5
µA
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 3.15V, VIL = 1.35V,
(Note 3)
+25oC
-
-
-
Propagation Delay
CP to Qn
TPHL
TPLH
VCC = 4.5V
+25oC
2
31
ns
Propagation Delay
CP to TC
TPLH
TPLH
VCC = 4.5V
+25oC
2
34
ns
Propagation Delay
TE to TC
TPHL
VCC = 4.5V
+25oC
2
23
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
12µA
IOL/IOH
5
-15% of 0 Hour
PARAMETER
Spec Number
224
518835
Specifications HCS163MS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
GROUP A SUBGROUPS
Initial Test (Preburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZ./H
Interim Test I (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZ./H
Interim Test II (Postburn-In)
100%/5004
1, 7, 9
ICC, IOL/H, IOZ./H
PDA
100%/5004
1, 7, 9, Deltas
Interim Test III (Postburn-In)
100%/5004
1, 7, 9
PDA
100%/5004
1, 7, 9, Deltas
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample/5005
1, 7, 9
Sample/5005
1, 7, 9
Group A (Note 1)
Group B
Group D
READ AND RECORD
ICC, IOL/H, IOZ./H
Subgroups 1, 2, 3, 9, 10, 11
NOTE:
1. Alternate group A testing in accordance with method 5005 of MIL-STD-883 may be exercised.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE
GROUPS
READ AND RECORD
METHOD
PRE RAD
POST RAD
PRE RAD
POST RAD
5005
1, 7, 9
Table 4
1, 9
Table 4 (Note 1)
Group E Subgroup 2
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS
OSCILLATOR
OPEN
GROUND
1/2 VCC = 3V ± 0.5V
VCC = 6V ± 0.5V
50kHz
25kHz
-
16
-
-
-
1 - 7, 9, 10, 16
-
-
11 - 15
1, 3, 5, 7, 9, 10, 16
2
-
STATIC BURN-IN I TEST CONNECTIONS (Note 1)
11 - 15
1 - 10
STATIC BURN-IN II TEST CONNECTIONS (Note 1)
11 - 15
8
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)
-
4, 6, 8
NOTES:
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in
2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in
TABLE 9. IRRADIATION TEST CONNECTIONS
OPEN
GROUND
VCC = 5V ± 0.5V
11 - 15
8
1 - 7, 9, 10, 16
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.
Spec Number
225
518835
HCS163MS
Intersil Space Level Product Flow - ‘MS’
Wafer Lot Acceptance (All Lots) Method 5007
(Includes SEM)
100% Interim Electrical Test 1 (T1)
GAMMA Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% Nondestructive Bond Pull, Method 2023
100% Interim Electrical Test 2 (T2)
Sample - Wire Bond Pull Monitor, Method 2011
100% Delta Calculation (T0-T2)
Sample - Die Shear Monitor, Method 2019 or 2027
100% PDA 1, Method 5004 (Notes 1and 2)
100% Internal Visual Inspection, Method 2010, Condition A
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or
Equivalent, Method 1015
100% Delta Calculation (T0-T1)
100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Interim Electrical Test 3 (T3)
100% Constant Acceleration, Method 2001, Condition per
Method 5004
100% Delta Calculation (T0-T3)
100% PDA 2, Method 5004 (Note 2)
100% PIND, Method 2020, Condition A
100% Final Electrical Test
100% External Visual
100% Fine/Gross Leak, Method 1014
100% Serialization
100% Radiographic, Method 2012 (Note 3)
100% Initial Electrical Test (T0)
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,
+125oC min., Method 1015
100% External Visual, Method 2009
Sample - Group A, Method 5005 (Note 4)
100% Data Package Generation (Note 5)
NOTES:
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the
failures from subgroup 7.
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.
5. Data Package Contents:
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,
Quantity).
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test
equipment, etc. Radiation Read and Record data on file at Intersil.
• X-Ray report and film. Includes penetrometer measurements.
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
• Lot Serial Number Sheet (Good units serial number and lot number).
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed
by an authorized Quality Representative.
Spec Number
226
518835
HCS163MS
Propagation Delay Timing Diagram and
Load Circuit
Pulse Width, Setup, Hold Timing Diagram
Positive Edge Trigger and Load Circuit
INPUT
VIH
INPUT
VS
VIH
TW
VS
VIL
TH
VIL
TPLH
TPHL
TSU
VOH
INPUT CP
VS
TW
VIH
OUTPUT
VOL
VS
VIL
AC VOLTAGE LEVELS
PARAMETER
AC VOLTAGE LEVELS
HCS
UNITS
VCC
4.50
V
VIH
4.50
VS
HCS
UNITS
VCC
4.50
V
V
VIH
4.50
V
2.25
V
VS
2.25
V
VIL
0
V
VIL
0
V
GND
0
V
GND
0
V
DUT
PARAMETER
TEST
POINT
CL
DUT
RL
TEST
POINT
CL
CL = 50pF
CL = 50pF
RL = 500Ω
RL = 500Ω
RL
Spec Number
227
518835
HCS163MS
Die Characteristics
DIE DIMENSIONS:
104 x 86 mils
METALLIZATION:
Type: AlSi
Metal Thickness: 11kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
< 2.0 x 105A/cm2
BOND PAD SIZE:
100µm x 100µm
4 mils x 4 mils
Metallization Mask Layout
HCS163MS
CP
MR
VCC
TC
P0
Q0
P1
Q1
P2
Q2
P3
Q3
PE
GND
SPE
TE
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.
The mask series for the HCS163 is TA14348A.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
228
518835
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