HI-516 Data Sheet October 1999 16-Channel/Differential 8-Channel, CMOS High Speed Analog Multiplexer The Hl-516 is a monolithic, dielectrically isolated, highspeed, high-performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. The dual function of address input A3 enables the Hl-516 to be user programmed either as a single ended 16-Channel multiplexer by connecting ‘out A’ to ‘out B’ and using A3 as a digital address input, or as an 8-Channel differential multiplexer by connecting A3 to the V- supply. The substrate leakages and parasitic capacitances are reduced substantially by using the Intersil Dielectric Isolation process to achieve optimum performance in both high and low level signal applications. The low output leakage current (lD(OFF) < 100pA at 25oC) and fast settling (tSETTLE = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control. • Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 130ns • Settling Time . . . . . . . . . . . . . . . . . . . . . . . . 250ns (0.1%) • Low Leakage (Typical) - IS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10pA - ID(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pA • Low Capacitance (Max) - CS(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10pF - CD(OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25pF • Off Isolation at 500kHz . . . . . . . . . . . . . . . . . . 55dB (Min) • Low Charge Injection Error . . . . . . . . . . . . . . . . . . . 20mV • Single Ended to Differential Selectable (SDS) • Logic Level Selectable (LLS) Applications • Data Acquisition Systems • Precision Instrumentation Ordering Information Pinout HI3-0516-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 28 Ld PDIP • Industrial Control HI-516 (PDIP) TOP VIEW PKG. NO. E28.6 V+ 1 OUT B 2 28 OUT A 27 V- NC 3 26 IN 8/8A IN 16/8B 4 25 IN 7/7A IN 15/7B 5 24 IN 6/6A IN 14/6B 6 23 IN 5/5A IN 13/5B 7 22 IN 4/4A IN 12/4B 8 21 IN 3/3A IN 11/3B 9 20 IN 2/2A IN 10/2B 10 19 IN 1/1A IN 9/1B 11 1 3146.3 Features For MIL-STD-883 compliant parts, request the Hl-516/883 data sheet. PART NUMBER File Number 18 ENABLE GND 12 17 A0 VDD /LLS 13 16 A1 A3 /SDS 14 15 A2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999 HI-516 Truth Tables HI-516 USED AS A 16-CHANNEL MULTIPLEXER OR DUAL 8-CHANNEL MULTIPLEXER (NOTE 1) USE A3 AS DIGITAL ADDRESS INPUT ENABLE A3 A2 A1 A0 HI-516 USED AS A DIFFERENTIAL 8-CHANNEL MULTIPLEXER ON CHANNEL TO OUT A OUT B A3 CONNECTED TO V- SUPPLY ON CHANNEL TO ENABLE A2 A1 A0 OUT A OUT B L X X X X None None L X X X None None H L L L L 1A None H L L L 1A 1B H L L L H 2A None H L L H 2A 2B H L L H L 3A None H L H L 3A 3B H L L H H 4A None H L H H 4A 4B H L H L L 5A None H H L L 5A 5B H L H L H 6A None H H L H 6A 6B H L H H L 7A None H H H L 7A 7B H L H H H 8A None H H H H 8A 8B H H L L L None 1B H H L L H None 2B H H L H L None 3B H H L H H None 4B H H H L L None 5B H H H L H None 6B H H H H L None 7B H H H H H None 8B NOTE: 1. For 16-channel single-ended function, tie ‘out A’ to ‘out B’; for dual 8-channel function use the A3 address pin to select between MUX A and MUX B, where MUX A is selected with A3 low. 2 HI-516 Functional Block Diagram VDD /LLS IN 1A N P EN OUT A A0 DECODER A1 IN 8A A2 N A3 P Q A3 DECODER IN 1B Q N P OUT B DECODER IN 8B N INPUT BUFFER AND DECODERS MULTIPLEXER SWITCHES A3 DECODE 3 P A3 Q Q H H L L L H V- L L HI-516 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V Analog Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VIN , VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Digital Input Voltage: TTL Levels Selected (VDD /LLS Pin = GND or Open) VA0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V VA3/SDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V CMOS Levels Selected (VDD /LLS Pin = VDD) VA0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Temperature Ranges HI-516-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND. (Note 3) Unless Otherwise Specified -5 TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS 25 - 130 175 ns Full - - 225 ns Break-Before-Make Delay, tOPEN 25 10 20 - ns Enable Delay (ON), tON(EN) 25 - 120 175 ns Enable Delay (OFF), tOFF(EN) 25 - 140 175 ns To 0.1% 25 - 250 - ns To 0.01% 25 - 800 - ns Charge Injection Error Note 6 25 - - 20 mV Off Isolation Note 7 25 55 - - dB Channel Input Capacitance, CS(OFF) 25 - - 10 pF Channel Output Capacitance, CD(OFF) 25 - - 25 pF Digital Input Capacitance, CA 25 - - 10 pF Input to Output Capacitance, CDS(OFF) 25 - 0.02 - pF PARAMETER DYNAMIC CHARACTERISTICS Access Time, tA Settling Time DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL (TTL) Note 3 Full - - 0.8 V Input High Threshold, VAH (TTL) Note 3 Full 2.4 - - V Input Low Threshold, VAL (CMOS) Note 3 Full - - 0.3VDD V Input High Threshold, VAH (CMOS) Note 3 Full 0.7VDD - - V Full - - 1 µA Input Leakage Current, IAH (High) 4 HI-516 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V; VDD /LLS = GND. (Note 3) Unless Otherwise Specified (Continued) -5 TEST CONDITIONS PARAMETER Input Leakage Current, IAL (Low) TEMP (oC) MIN TYP MAX UNITS Full - - 25 µA ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN Note 4 Full -15 - +15 V On Resistance, rON Note 5 25 - 620 750 Ω Full - - 1,000 Ω 25 - 0.01 - nA Full - - 50 nA 25 - 0.03 - nA Full - - 100 nA 25 - 0.04 - nA Full - - 900 mW Full - - 30 mA Full - - 30 mA Off Input Leakage Current, lS(OFF) Off Output Leakage Current, ID(OFF) On Channel Leakage Current, ID(ON) POWER SUPPLY CHARACTERISTICS Power Dissipation, PD I+, Current VEN = 2.4V I-, Current NOTES: 3. VDD /LLS pin = open or grounded for TTL compatibility. VDD /LLS pin = VDD for CMOS compatibility. 4. At temperatures above 90oC, care must be taken to assure VIN remains at least 1V below the VSUPPLY for proper operation. 5. VIN = ±10V, IOUT = -100µA. 6. VIN = 0V, CL = 100pF, enable input pulse = 3V, f = 500kHz. 7. VEN = 0.8V, VIN = 3VRMS , f = 500kHz, CL = 40pF, RL = 1K, Pin 3 grounded. 5 HI-516 Test Circuits and Waveforms VDD /LLS = GND, Unless Otherwise Specified. IOUT 100µA 0.8V EN V2 OUT A ID(OFF) IN OUT rON = VIN ±10V V2 ± ±10V 10V 100µA FIGURE 2. ID(OFF) TEST CIRCUIT (NOTE 8) FIGURE 1. ON RESISTANCE TEST CIRCUIT OUT OUT IS(OFF) A A ID(ON) EN EN 0.8V ± ±10V ±10V 10V 10V ± 2.4V FIGURE 3. IS(OFF) TEST CIRCUIT (NOTE 8) FIGURE 4. ID(ON) TEST CIRCUIT (NOTE 8) +15V 3.5V ADDRESS DRIVE (VA) V+ 50% IN 1 A3/SDS ±10V 0V +10V 50Ω OUTPUT 10% 2.4V -10V tA A2 IN 2-15 A1 IN 16 A0 OUT A EN VDD/LLS OUT B ± VA V- GND -15V FIGURE 5A. MEASUREMENT POINTS FIGURE 5B. TEST CIRCUIT NOTE: 8. Two measurements per channel: ±10V and 10V. (Two measurements per device for ID(OFF) ±10V and 10V). FIGURE 6. ACCESS TIME 6 10V 10 kΩ 50 pF HI-516 Test Circuits and Waveforms VDD /LLS = GND, Unless Otherwise Specified. (Continued) +15V V+ 3.5V A3 IN 2-15 ADDRESS DRIVE (VA) 0V VA A1 50Ω 50% 50% IN 16 A0 OUTPUT S1 ON +5V IN 1 A2 EN VDD /LLS 2.4V S16 ON OUTA OUTB VOUT 800 Ω V- 12.5pF GND tOPEN -15V FIGURE 7A. MEASUREMENT POINTS FIGURE 7B. TEST CIRCUIT FIGURE 7. BREAK-BEFORE-MAKE DELAY +15V 3.5V V+ ENABLE DRIVE (VA) A3 50% 50% +10V IN 1 A2 0V IN 2-16 A1 OUTPUT 90% A0 10% 0V tON(EN) EN VDD /LLS 50 Ω VA tOFF(EN) OUTA V- VOUT 800 Ω GND 12.5pF -15V FIGURE 8A. MEASUREMENT POINTS FIGURE 8B. TEST CIRCUIT FIGURE 8. ENABLE DELAYS +15V 2.4V V+ A 0 , A1 , A2 , A3 /SDS 3.0V 0V VA OUT ∆VO VOUT IN VOUT A OR B CL = 100pF EN VA GND VDD/LLS V- -15V FIGURE 9A. MEASUREMENT POINTS FIGURE 9B. TEST CIRCUIT ∆VO is the measured voltage error due to charge injection. The error in coulombs is Q = CL x ∆VO . FIGURE 9. CHARGE INJECTION 7 HI-516 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2250µm x 3720µm x 485µm Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.64 x 105 A/cm2 Metallization Mask Layout HI-516 ENABLE A0 A1 A2 A3 /SDS (18) (17) (16) (15) (14) VDD /LLS GND (13) (12) IN 1/1A (19) (10) IN 9/1B IN 2/2A (20) (9) IN 10/2B IN 3/3A (21) (8) IN 11/3B IN 4/4A (22) (7) IN 12/4B IN 5/5A (23) (6) IN 13/5B IN 6/6A (24) (5) IN 14/6B IN 7/7A (25) (4) IN 15/7B IN 8/8A (26) (3) IN 16/8B (27) (28) -V OUT A (1) +V (2) OUT B All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 8