DATASHEET

ESIGNS
NEW D
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ISL5405
ISL54504, ISL54505
Features
The Intersil ISL54504 and ISL54505 devices are low
ON-resistance, low voltage, bidirectional, single
pole/single throw (SPST) analog switches designed to
operate from a single +1.8V to +5.5V supply. Targeted
applications include battery powered equipment that
benefit from low rON resistance (2.5), excellent rON
flatness (0.6, and fast switching speeds (tON = 25ns,
tOFF = 15ns). The digital logic input is 1.8V CMOS
compatible when using a single +3V supply.
• ON-resistance (rON)
- VCC = +5.0V. . . . . . . . . . . . . . . . . . . . . 2.5
- VCC = +3.0V. . . . . . . . . . . . . . . . . . . . . 4.0
- VCC = +1.8V. . . . . . . . . . . . . . . . . . . . . 7.0
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins
may be limited and digital geometries are not well suited
to analog switch performance. This family of parts may
be used to switch in additional functionality while
reducing ASIC design risk. The ISL54504 and ISL54505
are offered in a 6 Ld 1.2mmx1.0mmx0.4mm pitch
µTDFN package and a 6 Ld SOT-23 package, alleviating
board space limitations.
The ISL54504 has one normally open (NO) switch and
ISL54505 has one normally closed (NC) switch.
TABLE 1. FEATURES AT A GLANCE
ISL54504
ISL54505
Number of Switches
1
1
SW
NO
NC
1.8V rON
6
6
1.8V tON/tOFF
65ns/40ns
65ns/40ns
3V rON
4
4
3V tON/tOFF
30ns/20ns
30ns/20ns
5V rON
2.5
2.5
5V tON/tOFF
25ns/15ns
25ns/15ns
Package
• rON flatness (+4.5V Supply) . . . . . . . . . . . . . 0.6
• Single supply operation . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V Supply)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . 6kV
• 1.8V CMOS logic compatible (+3V supply)
• Available in 6 Ld µTDFN and 6Ld SOT-23 Packages
ISL54504, ISL54505
+1.8V to +5.5V, 2.5, Single SPST Analog Switches
• Pb-free available (RoHS compliant)
Applications
• Battery powered, handheld, and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
6 Ld µTDFN, 6 Ld SOT-23
This is a Pre-Development Preliminary Datasheet. Device functionality and specifications are subject to change
October 23, 2009
FN6552.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54504, ISL54505
Ordering Information
PART NUMBER
(Notes 1, 4)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Tape and Reel) (Pb-Free)
PKG. DWG. #
ISL54504IRUZ-T (Note 2)
4
-40 to +85
6 Ld TDFN
L6.1.2x1.0A
ISL54504IHZ-T (Note 3)
4504
-40 to +85
6 Ld SOT-23
MDP0038
ISL54505IRUZ-T (Note 2)
5
-40 to +85
6 Ld TDFN
L6.1.2x1.0A
ISL54505IHZ-T (Note 3)
4505
-40 to +85
6 Ld SOT-23
MDP0038
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54504, ISL54505. For more information on
MSL please see techbrief TB363.
Pin Configurations
(Note 5)
ISL54504
(6 LD SOT-23)
TOP VIEW
ISL54504
(6 LD TDFN)
TOP VIEW
NO
1
6
IN
GND
2
5
V+
IN
N.C.
3
4
COM
NO 3
N.C.
1
6
IN
GND
2
5
V+
3
4
5 COM
2
4 V+
ISL54505
(6 LD SOT-23)
TOP VIEW
ISL54505
(6 LD TDFN)
TOP VIEW
NC
6 GND
N.C. 1
COM
NC
1
6 GND
IN
2
5 COM
N.C.
3
4 V+
NOTE:
5. Switches Shown for Logic “0” Input.
Truth Table
NOTE:
Pin Descriptions
LOGIC
ISL54504
ISL54505
PIN NAME
FUNCTION
0
Off
On
V+
System Power Supply Input (+1.8V to +5.5V)
1
On
Off
GND
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
IN
COM
Digital Control Input
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
N.C.
2
Ground Connection
No Connect
FN6552.2
October 23, 2009
ISL54504, ISL54505
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V
Input Voltages
NO, NC, IN (Note 4) . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Output Voltages
COM (Note 4) . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Continuous Current NO, NC, or COM. . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) 600mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . >2.2kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
6 Ld µTDFN Package (Notes 7, 9). .
239.2
111.6
6 Ld SOT-23 Package (Note 8, 10) .
260
120
Maximum Junction Temperature (Plastic Package). . +150°C
Maximum Storage Temperature Range. . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V+ (Positive DC Supply Voltage) . . .
Analog Signal Range . . . . . . . . . . .
VIN (Digital Logic Input Voltage (IN)
Temperature Range . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . 1.8V to 5.5V
. . . . . 0V to V+
. . . . . 0V to V+
-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum
current ratings.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
8. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
9. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
10. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V
(Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 12, 13)
TYP
MAX
(Notes 12, 13) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
ON-Resistance, rON
Full
V+ = 4.5V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Note 15, See Figure 4)
0
-
V+
V
25
-
2.2
2.5

Full
-
-
3

25
-
0.6
0.65

rON Flatness, rFLAT(ON)
V+ = 4.5V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Notes 14, 15)
NO or NC OFF Leakage
Current, INO(OFF) or
INC(OFF)
V+ = 5.5V, VCOM = 0.3V, 5V, VNO or
VNC = 5V, 0.3V
COM ON Leakage
Current, ICOM(ON)
V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or
VNC = 0.3V, 5V, or Floating
25
Full
-
-
0.7

25
-25
1.5
25
nA
Full
-150
-
150
nA
25
-30
2.8
30
nA
Full
-300
-
300
nA
-
25
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50,
CL = 35pF (See Figure 1, Note 15)
Turn-OFF Time, tOFF
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50,
CL = 35pF (See Figure 1, Note 15)
Full
-
25
-
ns
25
-
15
-
ns
Full
-
16
-
ns
Break-Before-Make Time
Delay, tD
V+ = 5.5V, VNO or VNC = 3.0V, RL = 50,
CL = 35pF (See Figure 3, Note 15)
Full
-
15
-
ns
Charge Injection, Q
VG = 0V, RG = 0, CL = 1.0nF
(See Figure 2)
25
-
24
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 1MHz,
VCOM = 1VP-P (See Figure 3)
25
-
70
-
dB
3
FN6552.2
October 23, 2009
ISL54504, ISL54505
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.0V, VINL = 0.8V
(Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 12, 13)
TYP
MAX
(Notes 12, 13) UNITS
Total Harmonic
Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P,
RL = 32
25
-
0.15
-
%
Total Harmonic
Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P,
RL = 600
25
-
0.014
-
%
-3dB Bandwidth
Signal = 0dBm, RL = 50
25
-
250
-
MHz
NO or NC OFF
Capacitance, COFF
V+ = 4.5V, f = 1MHz, VNO or
VNC = VCOM = 0V (See Figure 5)
25
-
7
-
pF
COM ON Capacitance,
CCOM(ON)
V+ = 4.5V, f = 1MHz, VNO or
VNC = VCOM = 0V (See Figure 5)
25
-
18
-
pF
Full
1.8
-
5.5
V
25
-
0.028
0.1
A
Full
-
1.1
2.5
A
Full
-
-
0.8
V
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current,
I+
V+ = 5.5V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Full
2.4
-
-
V
Input Current, IINH, IINL V+ = 5.5V, VIN = 0V or V+
Full
-0.1
0.053
0.1
A
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V
(Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 12, 13)
TYP
MAX
(Notes 12, 13) UNITS
Full
0
-
V+
V
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
ON-Resistance, rON
µTDFN
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Note 15, See Figure 4)
25
-
3.3
3.5

Full
-
-
4.5

ON-Resistance, rON
SOT-23
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Note 15, See Figure 4)
25
-
3.3
3.6

Full
-
-
4.5

rON Flatness, rFLAT(ON)
µTDFN
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Notes 7, 15)
25
-
1
1.1

Full
-
-
1.2

rON Flatness, rFLAT(ON)
SOT-23
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Notes 7, 15)
25
-
1
1.2

Full
-
-
1.3

25
-
30
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1, Note 15)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1, Note 15)
Full
-
30
-
ns
25
-
20
-
ns
Full
-
20
-
ns
Charge Injection, Q
VG = 0V, RG = 0,CL = 1.0nF (See Figure 2)
25
-
16
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 1MHz,
VCOM = 1VP-P (See Figure 3)
25
-
-70
-
dB
Total Harmonic
Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32
25
-
0.36
-
%
Total Harmonic
Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P,
RL = 600
25
-
0.03
-
%
4
FN6552.2
October 23, 2009
ISL54504, ISL54505
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V
(Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 12, 13)
TYP
MAX
(Notes 12, 13) UNITS
-3dB Bandwidth
Signal = 0dBm, RL = 50
25
-
250
-
MHz
NO or NC OFF
Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
6
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
15
-
pF
COM ON Capacitance,
CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
18
-
pF
25
-
0.013
-
A
Full
-
0.7
-
A
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+
Full
-0.1
0.058
0.1
A
POWER SUPPLY CHARACTERISTICS
Positive Supply Current,
I+
V+ = 3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 11),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
TEST CONDITIONS
TEMP
(°C)
MIN
MAX
(Notes 12, 13) TYP (Notes 12, 13) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
ON-Resistance, rON
Full
V+ = 1.8V, ICOM = 10mA, VNO or
VNC = 0V to V+ (Note 15, See Figure 4)
0
-
V+
V
25
-
6
6.5

Full
-
-
7

DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1, Note 15)
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1, Note 15)
Charge Injection, Q
VG = V+/2, RG = 0, CL = 1.0nF
(See Figure 2)
25
-
65
-
ns
Full
-
95
-
ns
25
-
40
-
ns
Full
-
65
-
ns
25
-
8.2
-
pC
Full
-
-
0.4
V
Full
1
-
-
V
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
NOTES:
11. VIN = input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
13. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal
range.
15. Limits established by characterization and are not production tested.
5
FN6552.2
October 23, 2009
ISL54504, ISL54505
Test Circuits and Waveforms
V+
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
C
0V
tOFF
SWITCH
INPUT VNO
COM
VOUT
IN
90%
90%
SWITCH
OUTPUT
VOUT
NO OR NC
SWITCH
INPUT
0V
LOGIC
INPUT
RL
50
GND
CL
35pF
tON
Logic input waveform is inverted for switches that have the
opposite logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
--------------------------V OUT = V
(NO or NC) R + r
L
 ON 
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
LOGIC
INPUT
VOUT
ON
RG
C
NO OR NC
VOUT
COM
VINH
ON
VG
OFF
GND
IN
CL
VINL
LOGIC
INPUT
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
V+
rON = V1/I1 *
C
NO OR NC
SIGNAL
GENERATOR
NO OR NC
VNX
IN
0V OR V+
IN
V1
I1
VINL OR VINH
100mA
COM
GND
COM
ANALYZER
GND
RL
* I = 10mA AT V+ = 1.8V
1
FIGURE 3. OFF ISOLATION TEST CIRCUIT
6
FIGURE 4. rON TEST CIRCUIT
FN6552.2
October 23, 2009
ISL54504, ISL54505
Test Circuits and Waveforms (Continued)
V+
C
NO OR NC
IN
VINL OR VINH
IMPEDANCE
ANALYZER
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54504 and ISL54505 are bidirectional, single
pole/single throw (SPST) analog switches. They offer
precise switching capability from a single 1.8V to 5.5V
supply with low ON-resistance (2.5and high speed
operation (tON = 25ns, tOFF = 15ns). The devices are
especially well suited for portable battery powered
equipment due to their low operating supply voltage
(1.8V), low power consumption (0.15µW), low
leakage currents (300nA max) and tiny µTDFN and
SOT-23 packages.
The ISL54504 is a single normally open (NO) SPST
analog switch. The ISL54505 is a single normally
closed (NC) SPST analog switch.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100 resistor in series with the
V+ power supply pin of the ISL54504, ISL54505 IC
(see Figure 6).
During an overvoltage transient event (such as occurs
during system level IEC 61000 ESD testing), substrate
currents can be generated in the IC that can trigger
parasitic SCR structures to turn ON, creating a low
impedance path from the V+ power supply to ground.
This will result in a significant amount of current flow in
the IC, which can potentially create a latch-up state or
permanently damage the IC. The external V+ resistor
limits the current during this over-stress situation and
has been found to prevent latch-up or destructive
damage for many overvoltage transient events.
Under normal operation the sub-microamp IDD current
of the IC produces an insignificant voltage drop across
the 100 series resistor resulting in no impact to
switch operation or performance.
7
V+
OPTIONAL
PROTECTION
RESISTOR
C
100
NO
COM
NC
IN
GND
FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED
ESD AND LATCH-UP IMMUNITY
Supply Sequencing And Overvoltage
Protection
With any CMOS device, proper power supply
sequencing is required to protect the device from
excessive input currents, which might permanently
damage the IC. All I/O pins contain ESD protection
diodes from the pin to V+ and to GND (see Figure 7).
To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed then
precautions must be implemented to prohibit the
current and voltage at the logic pin and signal pins
from exceeding the maximum ratings of the switch.
The following two methods can be used to provide
additional protection to limit the current in the event
that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 7). The
resistor limits the input current below the threshold
that produces permanent damage and the sub-
FN6552.2
October 23, 2009
ISL54504, ISL54505
microamp input current produces an insignificant
voltage drop during normal operation.
This method is not acceptable for the signal path
inputs. Adding a series resistor to the switch input
defeats the purpose of using a low rON switch.
Connecting Schottky diodes to the signal pins (as
shown in Figure 7) will shunt the fault current to the
supply or to ground, thereby protecting the switch.
These Schottky diodes must be sized to handle the
expected fault current.
This switch family is 1.8V CMOS compatible (0.5V and
1.4V) over a supply range of 2V to 3.6V (see
Figure 14). At 3.6V the VIH level is about 0.95V. This is
still below the 1.8V CMOS guaranteed high output
minimum level of 1.4V, but noise margin is reduced.
The digital input stages draw supply current whenever
the digital input voltage is not at one of the supply
rails. Driving the digital input signals from GND to V+
with a fast transition time minimizes power dissipation.
High-Frequency Performance
OPTIONAL
SCHOTTKY
DIODE
In 50 systems, the ISL54504/ISL54505 has a -3dB
bandwidth of 250MHz (see Figure 15). The frequency
response is very consistent over a wide V+ range and
for varying analog signal levels.
V+
OPTIONAL
PROTECTION
RESISTOR
Logic-Level Thresholds
INX
VNX
VCOM
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 7. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54504, ISL54505 construction is typical of
most single supply CMOS analog switches in that they
have two supply pins: V+ and GND. V+ and GND drive
the internal CMOS switches and set their analog
voltage limits. Unlike switches with a 4V maximum
supply voltage, the ISL54504, ISL54505 5.5V
maximum supply voltage provides plenty of room for
the 10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.8V but
the part will operate with a supply below 1.8V. It is
important to note that the input signal range, switching
times, and ON-resistance degrade at lower supply
voltages. Refer to the “Electrical Specifications” tables
starting on page 3 and the “Typical Performance
Curves” starting on page 9 for details.
V+ and GND also power the internal logic and level
shiftier. The level shiftier converts the input logic levels
to switched V+ and GND signals to drive the analog
switch gate terminals.
An OFF switch behaves like a capacitor and passes
higher frequencies with less attenuation, resulting in
signal feedthrough from a switch’s input to output. Off
isolation is the resistance of this signal feedthrough.
Figure 16 details the high off isolation provided by the
ISL54504, ISL54505. At 1MHz, off isolation is about
70dB in 50 systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease off isolation due to the voltage
divider action of the switch OFF impedance and the
load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal
exceeds V+ or GND.
Virtually all the analog leakage current comes from the
ESD diodes to V+ or GND. Although the ESD diodes on
a given signal pin are identical and therefore fairly well
balanced, they are reverse biased differently. Each is
biased by either V+ or GND and the analog signal. This
means their leakages will vary as the signal varies. The
difference in the two diode leakages to the V+ and
GND pins constitutes the analog-signal-path leakage
current. All analog leakage current flows between each
pin and one of the supply terminals, not to the other
switch terminal. This is why both sides of a given
switch can show leakage currents of the same or
opposite polarity. There is no connection between the
analog signal paths and V+ or GND.
This family of switches cannot be operated with bipolar
supplies because the input switching point becomes
negative in this configuration.
8
FN6552.2
October 23, 2009
ISL54504, ISL54505
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified.
3.0
4.0
ICOM = 100mA
3.5
2.5
V+ = 2.7V
3.0
+85°C
2.5
+25°C
2.0
rON ()
rON ()
2.0
V+ = 3V
V+ = 4.5V
1.5
1.5
-40°C
1.0
V+ = 5V
1.0
0.5
0.0
V+ = 4.5V
ICOM = 100mA
0.5
0.0
0
1
2
3
4
5
0
0.5
1.0
1.5
VCOM (V)
3.0
3.5
4.0
4.5
FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE
5.0
8
V+ = 2.7V
ICOM = 100mA
4.5
V+ = 1.8V
ICOM = 10mA
7
4.0
6
+85°C
3.5
+85°C
3.0
rON ()
rON ()
2.5
VCOM (V)
FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
+25°C
2.5
5
+25°C
4
-40°C
-40°C
3
2.0
2
1.5
1.0
2.0
0
0.5
1.0
1.5
2.0
1
2.5
0
0.2
0.4
0.6
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
0.8
1.0 1.2
VCOM (V)
1.4
1.6
1.8
2.0
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
100
70
-40°C
-40°C
90
60
80
70
50
+25°C
tOFF (ns)
tON (ns)
60
50
40 +85°C
40
+25°C
30
+85°C
30
20
20
10
10
0
1.5
2.0
2.5
3.0
3.5
4.0
V+ (V)
4.5
5.0
5.5
6.0
FIGURE 12. TURN-ON TIME vs SUPPLY VOLTAGE
9
0
1.5
2.0
2.5
3.0
3.5
4.0
V+ (V)
4.5
5.0
5.5
6.0
FIGURE 13. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6552.2
October 23, 2009
ISL54504, ISL54505
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified. (Continued)
1.4
0
-1
-2
1.2
V+ = 1.8V TO 5.5V
VCOM = 1VP-P
NORMALIZED GAIN (dB)
VINH AND VINL (V)
-3
1.0
VINH
0.8
VINL
0.6
-4
-5
-6
-7
-8
-9
-10
0.4
-11
-12
0.2
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-13
100k
5.5
1M
10M
V+ (V)
FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY
VOLTAGE
25
V+ = 1.8V TO 5.5V
20
-40
15
-50
10
Q (pC)
-60
(dB)
1G
FIGURE 15. FREQUENCY RESPONSE
-20
-30
100M
FREQUENCY (Hz)
-70
5
0
V+ = 5V
-80
-5
-90
V+ = 1.8V
-100
-15
-110
-120
1k
V+ = 3.3V
-10
-20
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 16. OFF ISOLATION
1G
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VCOM (V)
3.5
4.0
4.5
5.0
FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
PROCESS:
Submicron CMOS
10
FN6552.2
October 23, 2009
ISL54504, ISL54505
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
E
L6.1.2x1.0A
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
PIN 1
REFERENCE
2X
0.10 C
2X
D
0.10 C
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
0.127 REF
A3
TOP VIEW
DETAIL A
0.10 C
7X
SYMBOL
A
0.08 C
b
0.15
0.20
0.25
5
D
0.95
1.00
1.05
-
E
1.15
1.20
1.25
-
e
A1 A3
SIDE VIEW
C
SEATING
PLANE
4X
e
DETAIL B
1
5X
L
3
0.40 BSC
-
L
0.30
0.35
0.40
-
L1
0.40
0.45
0.50
-
N
6
2
Ne
3
3

L1
-
0
-
12
4
Rev. 2 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
6
4
BOTTOM VIEW
b 6X
0.10 C A B
0.05 C NOTE 3
0.1x45°
CHAMFER
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
A3
A1
DETAIL A
DETAIL B PIN 1 LEAD
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
1.00
1.40
0.20
0.30
0.45
0.20
0.35
0.40
LAND PATTERN
11
10
FN6552.2
October 23, 2009
ISL54504, ISL54505
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
TOLERANCE
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
0.25
0° +3°
-0°
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
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12
FN6552.2
October 23, 2009
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