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ISL5405
Data Sheet
May 31, 2007
Ultra Low ON-Resistance, High OffIsolation, Single Supply, Diff SPST Analog
Switch
The Intersil ISL54047 device is a low ON-resistance, low
voltage, high off-isolation, bidirectional, differential singlepole/single-throw (SPST) analog switch. It was designed to
operate from a single +1.65V to +4.5V supply. Targeted
applications include battery powered equipment that benefit
from low RON (0.44 and fast switching speeds (tON = 40ns,
tOFF = 35ns). The digital logic input is 1.8V logic-compatible
when using a single +3V supply.
The ISL54047 has been designed with a T-switch
architecture. This approach results in maximum off-isolation
while retaining a low impedance signal path when switches
are ON.
The device can be used as a low impedance bypass element
for noisy amplifier circuits.
The ISL54047 has two normally open (NO) SPST switches
that are controlled by a single logic control pin.
ISL54047
FN6503.0
Features
• T-Switch Architecture
• OFF-Isolation at 100kHz
- Into 50 Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 102dB
- Into 8 Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118dB
• ON Resistance (RON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.44
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.51
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.98
• RON Matching Between Channels . . . . . . . . . . . . . . . . 0.04
• RON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.07
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD). . . . . . . . . . . . . . . <0.45W
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
• 1.8V Logic Compatible (+3V supply)
TABLE 1. FEATURES AT A GLANCE
• Low ICC Current when VinH is not at the V+ Raill
ISL54047
• Available in 10 lead 1.8 x 1.4 x 0.5mm TQFN
Number of Switches
2
SW
SPST
• Pb-Free Plus Anneal Available (RoHS Compliant)
4.3V RON
0.44
Applications
4.3V tON/tOFF
40ns/35ns
3V RON
0.51
3V tON/tOFF
50ns/40ns
1.8V RON
0.98
1.8V tON/tOFF
70ns/65ns
Package
10 Ld 1.8 x 1.4 x 0.5mm TQFN
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54047
Pinout
Truth Table
(Note 1)
ISL54047 (TQFN)
TOP VIEW
COM2
GND
7
N.C.
8
N.C.
NO2
6
LOGIC
NO1, NO2
0
OFF
1
ON
5
COM1
NOTE:
9
4
IN
Pin Descriptions
10
3
N.C.
1
2
V+
NO1
PIN
FUNCTION
V+
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COMx
Analog Switch Common Pin
NOx
Analog Switch Normally Open Pin
N.C.
No Connect
NOTE:
1. Switches Shown for Logic “0” Input.
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
Ordering Information
PART NUMBER
(Note)
ISL54047IRUZ-T
PART MARKING
D
TEMP. RANGE (°C)
-40 to +85
PACKAGE
(Pb-Free)
10 Ld 1.8 x 1.4 x 0.5mm TQFN
Tape and Reel
PKG.
DWG. #
L10.1.8x1.4A
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
2
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May 31, 2007
ISL54047
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, IN (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, COM . . . . . . . . . . . . . . . . . . . . . . . 300mA
Peak Current NO, COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 500mA
ESD Rating:
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
10 Ld TQFN Package (Note 3) . . . . .
143
61
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Extended operation above the recommended
operating conditions could result in decreased reliability. The Absolute Maximum Ratings are stress only ratings and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NOx, IN, or COMx pins exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.45
-

Full
-
0.55
-

25
-
0.04
-

Full
-
0.04
-

25
-
0.07
-

Full
-
0.08
-

25
-100
-
100
nA
Full
-195
-
195
nA
25
-100
-
100
nA
Full
-195
-
195
nA
25
-
40
-
ns
Full
-
50
-
ns
25
-
35
-
ns
Full
-
45
-
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 3.9V, ICOM = 100mA, VNO = 0V to V+,
(See Figure 4)
RON Matching Between Channels,
RON
V+ = 3.9V, ICOM = 100mA, VNO = Voltage at max RON,
(Note 7)
RON Flatness, RFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO = 0V to V+, (Note 6)
NO OFF Leakage Current,
INO(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 4.5V, VCOM = 0.3V, 3V, or VNO = 0.3V, 3V, or
Floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO = 3.0V, RL =50, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO = 3.0V, RL =50, CL = 35pF,
(See Figure 1)
Charge Injection, Q
CL = 1.0nF, VG = 2V, RG = 0See Figure 2)
25
-
192
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 3)
25
-
102
-
dB
OFF Isolation
RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS,
(See Figure 3)
25
-
81
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS,
(See Figure 5)
25
-
-95
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.01
-
%
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May 31, 2007
ISL54047
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
NO OFF Capacitance, COFF
f = 1MHz, VNO = VCOM = 0V, (See Figure 6)
25
-
46
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO = VCOM = 0V, (See Figure 6)
25
-
233
-
pF
Full
1.65
4.5
V
25
-
-
0.1
A
Full
-
-
1
A
25
-
-
0.5
A
Full
-
-
1
A
25
-
-
12
A
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.6
-
-
V
Full
-0.5
-
0.5
A
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V
Positive Supply Current, I+
V+ = +4.5V, VIN = V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.55
0.6

Full
-
-
0.8

25
-
0.05
0.07

ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 2.7V, ICOM = 100mA, VNO = 0V to V+,
(See Figure 4)
RON Matching Between Channels,
RON
V+ = 2.7V, ICOM = 100mA, VNO = Voltage at max RON,
(Note 7)
RON Flatness, RFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO = 0V to V+, (Note 6)
NO OFF Leakage Current,
INO(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 3.3V, VCOM = 0.3V, 3V, or VNO = 0.3V, 3V, or
Floating
Full
-
-
0.08

25
-
0.1
0.15

Full
-
-
0.15

25
-
0.9
-
nA
Full
-
30
-
nA
25
-
0.8
-
nA
Full
-
30
-
nA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO = 1.5V, RL = 50, CL = 35pF,
(See Figure 1)
25
-
50
-
ns
Full
-
60
-
ns
25
-
40
-
ns
Full
-
50
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 1.5V, RG = 0See Figure 2)
25
-
115
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 3)
25
-
102
-
dB
OFF Isolation
RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS,
(See Figure 3)
25
-
81
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 1MHz, VCOM = 1VRMS,
(See Figure 5)
25
-
-95
-
dB
4
FN6503.0
May 31, 2007
ISL54047
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.016
-
%
NO Capacitance, COFF
f = 1MHz, VNO = VCOM = 0V, (See Figure 6)
25
-
48
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO = VCOM = 0V, (See Figure 6)
25
-
236
-
pF
25
-
0.01
-
A
Full
-
0.52
-
A
Input Voltage Low, VINL
25
-
-
0.5
V
Input Voltage High, VINH
25
1.4
-
-
V
Full
-0.5
-
0.5
A
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
1.24
-

Full
-
1.34
-

25
-
70
-
ns
Full
-
80
-
ns
25
-
65
-
ns
Full
-
75
-
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.65V, ICOM = 100mA, VNO = 0V to V+,
(See Figure 4)
ON Resistance, RON
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO = 1.0V, RL =50, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 1.65V, VNO = 1.0V, RL =50, CL = 35pF,
(See Figure 1)
Charge Injection, Q
CL = 1.0nF, VG = 1V, RG = 0See Figure 2)
25
-
53
-
pC
NO OFF Capacitance, COFF
f = 1MHz, VNO = VCOM = 0V, (See Figure 6)
25
-
52
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO = VCOM = 0V, (See Figure 6)
25
-
237
-
pF
Input Voltage Low, VINL
25
-
-
0.4
V
Input Voltage High, VINH
25
1.0
-
-
V
Full
-0.5
-
0.5
A
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron
value, between NO1 and NO2.
5
FN6503.0
May 31, 2007
ISL54047
Test Circuits and Waveforms
V+
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
0V
tOFF
SWITCH
INPUT VNO
VOUT
NO
SWITCH
INPUT
COM
IN
VOUT
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
CL
35pF
RL
50
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO) -----------------------------R L + R  ON 
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
COM
NO
VOUT
VG
GND
IN
CL
V+
ON
ON
LOGIC
INPUT
OFF
LOGIC
INPUT
0V
Q = VOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
V+
C
SIGNAL
GENERATOR
RON = V1/100mA
NO
NO
IN
0V or V+
VNX
100mA
IN
V1
0V or V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 3. OFF ISOLATION TEST CIRCUIT
6
Repeat test for all switches.
FIGURE 4. RON TEST CIRCUIT
FN6503.0
May 31, 2007
ISL54047
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
NO
COM
50
NO
IN1
IN
0V or V+
NO
COM
ANALYZER
0V or V+
IMPEDANCE
ANALYZER
COM
N.C.
GND
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
Repeat test for all switches.
FIGURE 6. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54047 is a bidirectional, differential single pole/single
throw (SPST) analog switch that offer precise switching
capability from a single 1.65V to 4.5V supply with low
on-resistance (0.44) and high speed operation (tON =
40ns, tOFF = 35ns). The devices are especially well suited
for portable battery powered equipment due to their low
operating supply voltage (1.65V), low power consumption
(4.5W max) and the tiny TQFN package. The ultra low onresistance and Ron flatness provide very low insertion loss
and distortion to applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil
recommends adding a 100 resistor in series with the V+
power supply pin of the ISL54047 IC (see Figure 7).
During an over-voltage transient event, such as occurs
during system level IEC 61000 ESD testing, substrate
currents can be generated in the IC that can trigger parasitic
SCR structures to turn ON, creating a low impedance path
from the V+ power supply to ground. This will result in a
significant amount of current flow in the IC which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many over voltage transient
events.
Under normal operation the sub-microamp IDD current of the
IC produces an insignificant voltage drop across the 100
series resistor resulting in no impact to switch operation or
performance.
V+
OPTIONAL
PROTECTION
RESISTOR
C
100
NO1
COM1
N02
COM2
IN
GND
FIGURE 7. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 8). The resistor limits
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FN6503.0
May 31, 2007
ISL54047
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch. Connecting schottky
diodes to the signal pins as shown in Figure 8 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
OPTIONAL
SCHOTTKY
DIODE
INX
VNX
OPTIONAL
SCHOTTKY
DIODE
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
The ISL54047 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply
the device draws only 12A of current (see Figure 16 for
VIN = 2.85V).
Frequency Performance
V+
OPTIONAL
PROTECTION
RESISTOR
2.7V the VIL level is about 0.53V. This is still above the 1.8V
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
VCOM
GND
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54047 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL54047 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the Electrical Specification Tables on page 5 and Typical
Performance Curves on page 9 for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
In 50 systems, the ISL54047 has a -3dB bandwidth of
27MHz (see Figure 21). The frequency response is very
consistent over a wide V+ range, and for varying analog
signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another. Figure
22 details the high Off Isolation and Crosstalk rejection
provided by this part. At 100kHz, Off Isolation is about 102dB
in 50 systems, 118dB into 8, and 124dB into 4,
decreasing approximately 20dB per decade as frequency
increases. Higher load impedances decrease Off Isolation
and Crosstalk rejection due to the voltage divider action of
the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Logic-Level Thresholds
This switch family are 1.8V CMOS compatible (0.5V and
1.4V) over a supply range of 2.7V to 4.5V (see Figure 18). At
8
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ISL54047
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
0.46
0.56
ICOM = 100mA
ICOM = 100mA
0.54
0.44
0.52
V+ = 2.7V
0.50
RON ()
RON (W)
0.42
0.40
V+ = 3.9V
0.48
V+ = 3V
0.46
0.38
0.44
V+ = 4.3V
V+ = 3.3V
0.36
0.42
V+ = 4.5V
0.34
0
1
2
3
4
0.40
5
0
0.5
1
1.5
2
VCOM (V)
VCOM (V)
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
3
3.5
FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.55
1.3
V+ = 4.3V
ICOM = 100mA
ICOM = 100mA
1.2
0.50
1.1
V+ = 1.65V
85°C
0.45
RON ()
1.0
RON ()
2.5
V+ = 1.8V
0.9
0.8
V+ = 2V
0.40
25°C
0.35
0.7
0.30
0.6
-40°C
0.5
0
0.5
1
1.5
0.25
2
0
1
2
VCOM (V)
3
4
5
VCOM (V)
FIGURE 11. ON RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.60
FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE
0.70
V+ = 3.3V
ICOM = 100mA
V+ = 2.7V
ICOM = 100mA
0.65
0.55
85°C
85°C
0.60
RON ()
RON ()
0.50
0.45
25°C
0.40
0.55
25°C
0.50
0.45
0.35
-40°C
0.40
-40°C
0.30
0
0.5
1
1.5
2
2.5
3
VCOM (V)
FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE
9
3.5
0.35
0
0.5
1
1.5
2
2.5
3
VCOM (V)
FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE
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ISL54047
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
1.1
V+ = 1.8V
ICOM = 100mA
85°C
1.0
200
V+ = 4.2V
25°C
0.9
150
-40°C
iON (A)
RON ()
0.8
0.7
100
0.6
50
0.5
0.4
0
0
0.5
1
1.5
1
2
2
VCOM (V)
FIGURE 15. ON RESISTANCE vs SWITCH VOLTAGE
1.1
600
1.0
400
VINH AND VINL (V)
Q (pC)
V+ = 1.8V
V+ = 3V
-400
-600
VINH
0.8
0.7
0.6
0.5
VINL
0.4
-800
-1000
0
1
2
3
4
0.3
1.5
2.0
2.5
VCOM (V)
200
200
150
150
+85°C
100
+25°C
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
tOFF (ns)
tON (ns)
FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE
50
5
0.9
V+ = 4.3V
200
-200
4
FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE
800
0
3
VIN(V)
100
+85°C
+25°C
-40°C
0
1.0
50
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE
10
0
1.0
-40°C
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6503.0
May 31, 2007
ISL54047
0
0
-1
-2
-20
GAIN
-3
-4
-5
-6
-7
-8
0
V+ = 4.3V
RL = 50
20
-40
40
-60
60
-80
80
ISOLATION
-100
-9
OFF ISOLATION (dB)
1
CROSSTALK (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
100
CROSSTALK
V+ = 4.3V
RL = 50
VIN = 0.2VP-P to 2VP-P
0.01
-120
1
0.1
10
FREQUENCY (MHz)
FIGURE 21. FREQUENCY RESPONSE
100
-140
1k
120
10k
100k
1M
10M
140
100M 500M
FREQUENCY (Hz)
FIGURE 22. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
11
FN6503.0
May 31, 2007
ISL54047
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
2X
A
B
1
2
TOP VIEW
C
A
SIDE VIEW
(DATUM A)
1
2
NX L
NX b 5
10X
0.10 M C A B
0.05 M C
L1
5
(DATUM B)
NOMINAL
MAX
NOTES
0.45
0.50
0.55
-
A1
-
-
0.05
-
0.127 or 0.15 REF
-
b
0.15
0.20
0.25
5, 9
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
A1
PIN #1 ID
MIN
A
A3
0.10 C
SEATING PLANE
MILLIMETERS
SYMBOL
0.10 C
0.05 C
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
E
N
0.10 C
2X
L10.1.8x1.4A
0.40 BSC
-
L
0.35
0.40
0.45
L1
0.45
0.50
0.55
9
-
N
10
2
Nd
2
3
Ne
3
3

0
-
12
4
Rev. 1 1/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
7
e
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
NX (b)
(A1)
9 L
5
e
SECTION "C-C"
C C
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
TERMINAL TIP
8. Maximum allowable burrs is 0.076mm in all directions.
9. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
10. JEDEC Reference MO-255.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6503.0
May 31, 2007
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