DATASHEET

S
DESIGN
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OMMEN REPLACEMEN
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ISL5405
ISL54054, ISL54055
Features
The Intersil ISL54054 and ISL54055 devices consist of
low ON-resistance, low voltage, bi-directional SPST
analog switches designed to operate from a single +1.8V
to +5.5V supply. These devices have an unique
architecture. They have two signal pins (pin 1 and pin 3)
that are simultaneously connected or disconnected to a
common pin (pin 4) under the control of a single logic
control pin (pin 6). The ISL54054 switches are OFF when
the logic is low and ON when the logic is high. The
ISL54055 switches are ON when the logic is low and OFF
when the logic is high. This architecture allows these
devices to be used as a single SPST switch or as a
distribution switch to distribute a single source to two
different loads.
• ON-resistance (rON) (Signal Pins Connected)
- VCC = +5.0V. . . . . . . . . . . . . . . . . . . . . 0.34
- VCC = +3.0V. . . . . . . . . . . . . . . . . . . . . 0.51
- VCC = +1.8V. . . . . . . . . . . . . . . . . . . . . 1.1
SPST operation is achieved by using one of the signal
pins while floating the other signal pin or by externally
connecting the two signal pins together. When both
signal pins are tied together, the rON of the SPST is
reduced by half, from 1 to 0.5 (when operated with a
5V supply).
Targeted applications include battery powered equipment
that benefit from low rON resistance, excellent rON
flatness, and fast switching speeds (tON = 12ns,
tOFF = 12ns). The digital logic input is 1.8V logic
compatible when using a single 2.7V to +3.6V supply
and TTL compatible when the supply is > +3.6V.
The ISL54054 is offered in a 6 Ld
1.2mmx1.0mmx0.5mm TDFN and 6 Ld SOT-23
packages. The ISL54055 is offered in a 6 Ld
1.2mmx1.0mmx0.5mm TDFN, alleviating board space
limitations.
• rON flatness (+4.5V supply) . . . . . . . . . . . . 0.13
• Single supply operation . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V supply)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . >6kV
• 1.8V logic compatible (+3V supply)
ISL54054, ISL54055
Ultra Low ON-Resistance, Low Voltage, Single
Supply, Single SPST/1:2 Distribution Analog Switch
• Available in 6 Ld TDFN and 6Ld SOT-23 Packages
• Pb-free (RoHS compliant)
Applications
• Battery powered, handheld and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Portable test and measurement
• Medical equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
The ISL54054 has two normally open (NO) switches and
the ISL54055 has two normally closed (NC) switches.
TABLE 1. FEATURES AT A GLANCE
ISL54054
ISL54055
1
1
Number of Switches
SW
NO
NC
1.8V rON
1.1
1.1
1.8V tON/tOFF
115ns/90ns
115ns/90ns
3V rON
0.51
0.51
3V tON/tOFF
22ns/17ns
22ns/17ns
5V rON
0.34
0.34
5V tON/tOFF
12ns/12ns
12ns/12ns
6 Ld TDFN
Packages
6 Ld TDFN,
6 Ld SOT-23
This is a Pre-Development Preliminary Datasheet. Device functionality and specifications are subject to change
October 19, 2009
FN6461.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54054, ISL54055
Ordering Information
PART NUMBER
(Notes 1, 4)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54054IRUZ-T (Note 3)
D
-40 to +85
6 Ld TDFN
Tape and Reel
L6.1.2x1.0A
ISL54054IHZ-T (Note 2)
4054
-40 to +85
6 Ld SOT-23
Tape and Reel
MDP0038
ISL54055IRUZ-T (Note 3)
E
-40 to +85
6 Ld TDFN
Tape and Reel
L6.1.2x1.0A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54054, ISL54055. For more information on
MSL please see techbrief TB363.
Pin Configurations
(Note 5)
ISL54054
(6 LD SOT-23)
TOP VIEW
ISL54054
(6 LD TDFN)
TOP VIEW
NO
1
6
IN
GND
2
5
V+
NO
3
4
COM
NO 1
6 GND
IN
5 COM
2
4 V+
NO 3
ISL54055
(6 LD TDFN)
TOP VIEW
NC
1
6
IN
GND
2
5
V+
NC
3
4
COM
NOTE:
5. Switches Shown for Logic “0” Input.
Pin Descriptions
Truth Table
LOGIC
ISL54055
Both NC
Switches
0
Off
On
1
NOTE:
PIN
ISL54054
Both NO
Switches
On
Off
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
2
V+
GND
IN
COM
FUNCTION
System Power Supply Input (+1.8V to +5.5V)
Ground Connection
Digital Control Input
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
FN6461.2
October 19, 2009
ISL54054, ISL54055
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V
Input Voltages
NO, NC, IN (Note 6) . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 6) . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM. . . . . . . . . . . . 300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max)600mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >200V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . >2.2kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
6 Ld TDFN Package (Note 7) . . . .
175
N/A
6 Ld SOT-23 Package (Note 8) . . . .
260
120
Maximum Junction Temperature (Plastic Package). . +150°C
Maximum Storage Temperature Range. . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V+ (Positive DC Supply Voltage) . . .
Analog Signal Range . . . . . . . . . . .
VIN (Digital Logic Input Voltage (IN)
Temperature Range . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . 1.8V to 5.5V
. . . . . 0V to V+
. . . . . 0V to V+
-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum
current ratings.
7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
8. For JC, the “case temp” location is taken at the package top center.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
Full
ON-Resistance, rON
(Nx Inputs Connected)
V+ = 4.5V, ICOM = 100mA, VNO or
VNC = 0V to V+, (See Figure 4, Note 13)
rON Flatness, rFLAT(ON)
(Nx Inputs Connected)
V+ = 4.5V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Notes 12, 13)
ON-Resistance, rON
(Single Nx Input)
V+ = 4.5V, ICOM = 100mA, VNO or
VNC = 0V to V+, (See Figure 4, Note 13)
rON Flatness, rFLAT(ON)
(Single Nx Input)
V+ = 4.5V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Notes 12, 13)
NO or NC OFF Leakage
Current, INO(OFF) or
INC(OFF)
V+ = 5.5V, VCOM = 0.3V, 5V, VNO or
VNC = 5V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 5.5V, VCOM = 0.3V, 5V, or VNO or
VNC = 0.3V, 5V, or floating
0
-
V+
V
25
-
0.36
-

Full
-
0.49
-

25
-
0.12
-

Full
-
0.13
-

25
-
0.85
-

Full
-
1.1
-

25
-
0.25
-

Full
-
0.25
-

25
-10
5
10
nA
Full
-150
-
150
nA
25
-20
9
20
nA
Full
-300
-
300
nA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50,
CL = 35pF (See Figure 1)
25
-
12
-
ns
Full
-
15
-
ns
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50,
CL = 35pF (See Figure 1)
25
-
12
-
ns
Full
-
15
-
ns
Charge Injection, Q
VG = 0V, RG = 0, CL = 1.0nF
(See Figure 2)
25
-
71
-
pC
OFF Isolation
(Nx Inputs Connected)
RL = 50, CL = 5pF, f = 100kHz,
VCOM = 1VRMS (See Figure 3)
25
-
74
-
dB
3
FN6461.2
October 19, 2009
ISL54054, ISL54055
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V
(Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
OFF Isolation
(Single Nx Input)
RL = 50, CL = 5pF, f = 100kHz,
VCOM = 1VRMS (See Figure 3)
25
-
83
-
dB
-3dB Bandwidth
(Nx Inputs Connected)
RL = 50
25
-
72
-
MHz
-3dB Bandwidth
(Single Nx Input)
RL = 50
25
-
138
-
MHz
NO or NC OFF Capacitance, f = 1MHz, VNO or VNC = VCOM = 0V
COFF (Nx Inputs Connected) (See Figure 5)
25
-
30
-
pF
COM ON Capacitance,
CCOM(ON) (Nx Inputs
Connected)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
62
-
pF
NO or NC OFF Capacitance,
COFF (Single Nx Input)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
16
-
pF
COM ON Capacitance,
CCOM(ON) (Single Nx Input)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
89
-
pF
Full
1.8
-
5.5
V
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
(TDFN)
V+ = 5.5V, VIN = 0V or V+
Positive Supply Current, I+
(SOT-23)
V+ = 5.5V, VIN = 0V or V+
25
-
-
0.5
A
Full
-
-
1.0
A
25
-
-
0.5
A
Full
-
-
1.4
A
Full
-
-
0.8
V
Full
2.4
-
-
V
Full
-1
-
1
A
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 5.5V, VIN = 0V or V+
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V
(Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
ON-Resistance, rON
(Nx Inputs Connected)
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (See Figure 4, Note 13)
rON Flatness, rFLAT(ON)
(Nx Inputs Connected)
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Notes 12, 13)
ON-Resistance, rON
(Single Nx Input)
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (See Figure 4, Note 13)
rON Flatness, rFLAT(ON)
(Single Nx Input)
V+ = 2.7V, ICOM = 100mA, VNO or
VNC = 0V to V+, (Notes 12, 13)
Full
0
-
V+
V
25
-
0.57
0.65

Full
-
0.73
1.0

25
-
0.2
0.4

Full
-
0.2
0.5

25
-
1.3
1.7

Full
-
1.6
2.0

25
-
0.4
0.6

Full
-
0.4
0.7

DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1)
25
-
22
-
ns
Full
-
25
-
ns
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1)
25
-
17
-
ns
Full
-
20
-
ns
4
FN6461.2
October 19, 2009
ISL54054, ISL54055
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V
(Note 9), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
Charge Injection, Q
VG = 0V, RG = 0, CL = 1.0nF
(See Figure 2)
25
-
42
-
pC
OFF Isolation
(Nx Inputs Connected)
RL = 50, CL = 5pF, f = 100kHz,
VCOM = 1VRMS (See Figure 3)
25
-
74
-
dB
OFF Isolation
(Single Nx Input)
RL = 50, CL = 5pF, f = 100kHz,
VCOM = 1VRMS (See Figure 3)
25
-
83
-
dB
NO or NC OFF Capacitance, f = 1MHz, VNO or VNC = VCOM = 0V
COFF (Nx Inputs Connected) (See Figure 5)
25
-
30
-
pF
COM ON Capacitance,
CCOM(ON) (Nx Inputs
Connected)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
62
-
pF
NO or NC OFF Capacitance,
COFF (Single Nx Input)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
16
-
pF
COM ON Capacitance,
CCOM(ON) (Single Nx Input)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
89
-
pF
Full
-
-
0.5
V
Full
1.4
-
-
V
Full
-1
-
1
A
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.8V, VINL = 0V (Note 9),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
ON-Resistance, rON
(Nx Inputs Connected)
V+ = 1.8V, ICOM = 100mA, VNO or
VNC = 0V to V+, Pins 1 and 3 connected,
(See Figure 4, Note 13)
ON-Resistance, rON
(Single Nx Input)
V+ = 1.8V, ICOM = 100mA, VNO or
VNC = 0V to V+ (See Figure 4, Note 13)
Full
0
-
V+
V
25
-
1.1
-

Full
-
1.3
-

25
-
2.3
-

Full
-
2.53
-

DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1)
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50,
CL = 35pF (See Figure 1)
Charge Injection, Q
VG = 0V, RG = 0,CL = 1.0nF
(See Figure 2)
25
-
115
-
ns
Full
-
246
-
ns
25
-
90
-
ns
Full
-
192
-
ns
25
-
22
-
pC
NOTES:
9. VIN = input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal
range.
13. Limits established by characterization and are not production tested.
5
FN6461.2
October 19, 2009
ISL54054, ISL54055
Test Circuits and Waveforms
VINH
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
C
VINL
tOFF
SWITCH
INPUT VNO
COM
VOUT
IN
90%
90%
SWITCH
OUTPUT
VOUT
NO OR NC
SWITCH
INPUT
0V
LOGIC
INPUT
CL
35pF
RL
50
GND
tON
Logic input waveform is inverted for switches that have the
opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance.
V OUT = V
FIGURE 1A. MEASUREMENT POINTS
RL
--------------------------(NO or NC) R + r
L
 ON 
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
LOGIC
INPUT
VOUT
RG
VOUT
COM
NO OR NC
VINH
ON
ON
C
VG
OFF
GND
IN
CL
VINL
LOGIC
INPUT
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
V+
C
C
rON = V1/100mA
SIGNAL
GENERATOR
NO OR NC
NO OR NC
VNX
IN
0V OR V+
COM
ANALYZER
100mA
IN
V1
VINL OR VINH
COM
GND
GND
RL
FIGURE 3. OFF ISOLATION TEST CIRCUIT
6
FIGURE 4. rON TEST CIRCUIT
FN6461.2
October 19, 2009
ISL54054, ISL54055
Test Circuits and Waveforms (Continued)
V+
C
NO OR NC
IN
VINL OR VINH
IMPEDANCE
ANALYZER
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The Intersil ISL54054 and ISL54055 devices consist of
low ON-resistance, low voltage, bi-directional analog
switches designed to operate from a single +1.8V to
+5.5V supply. With a single supply of 5V the typical
ON-resistance is only 0.34, with a typical turn-on and
turn-off time of: tON = 12ns, tOFF = 12ns. The
devices are especially well suited for portable battery
powered equipment due to its low operating supply
voltage (1.8V), low power consumption (5.5W), low
leakage currents (300nA max) and the tiny TDFN
and SOT-23 packages.
These devices have an unique architecture. They have
two signal pins (pin 1 and pin 3) that are
simultaneously connected or disconnected to a single
common pin (pin 4) under the control of a single logic
control pin (pin 6). The ISL54054 switches are OFF
when the logic is low and ON when the logic is high.
The ISL54055 are ON when the logic is low and OFF
when the logic is high. This architecture allows these
devices to be used as a single SPST switch or as a
distribution switch to distribute a single source to two
different loads.
SPST operation is achieved by using one of the Nx
signal pins while floating the other Nx signal pin or by
externally connecting the two Nx signal pins together.
When both signal pins are tied together, the rON of the
SPST is reduced by half, from 1 to 0.5 (when
operated with a 5V supply).
The ISL54054 is a normally open (NO) SPST analog
switch. The ISL54055 is a normally closed (NC) SPST
analog switch.
Supply Sequencing and Overvoltage
Protection
To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 6). The
resistor limits the input current below the threshold
that produces permanent damage, and the submicroamp input current produces an insignificant
voltage drop during normal operation.
This method is not acceptable for the signal path
inputs. Adding a series resistor to the switch input
defeats the purpose of using a low rON switch.
Connecting schottky diodes to the signal pins (as
shown in Figure 6) will shunt the fault current to the
supply or to ground, thereby protecting the switch.
These schottky diodes must be sized to handle the
expected fault current.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNX
OPTIONAL
SCHOTTKY
DIODE
VCOM
GND
FIGURE 6. OVERVOLTAGE PROTECTION
With any CMOS device, proper power supply
sequencing is required to protect the device from
excessive input currents, which might permanently
damage the IC. All I/O pins contain ESD protection
diodes from the pin to V+ and to GND (see Figure 6).
7
FN6461.2
October 19, 2009
ISL54054, ISL54055
Power-Supply Considerations
High-Frequency Performance
The construction of the ISL54054 and the ISL54055 is
typical of most single supply CMOS analog switches in
that they have two supply pins: V+ and GND. V+ and
GND drive the internal CMOS switches and set their
analog voltage limits. Unlike switches with a 4.5V
maximum supply voltage, the ISL54054 and the
ISL54055’s 5.5V maximum supply voltage provides
plenty of room for the 10% tolerance of 4.5V supplies,
as well as room for overshoot and noise spikes.
In 50 systems, the ISL54054 and the ISL54055 have a
-3dB bandwidth of 72MHz with Nx pins connected and
138MHz for a single Nx input (see Figure 20). The
frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
The minimum recommended supply voltage is 1.8V. It
is important to note that the input signal range,
switching times, and on-resistance degrade at lower
supply voltages. Refer to the “Electrical Specifications”
tables starting on page 3 and “Typical Performance
Curves” on page 8 for details.
V+ and GND also power the internal logic and level
shiftier. The level shiftier converts the input logic levels
to switched V+ and GND signals to drive the analog
switch gate terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V logic compatible (0.5V and
1.4V) over a supply range of 2.5V to 5V (see
Figure 19). At 5V the VIH level is about 1.38V. This is
still below the 1.8V CMOS guaranteed high output
minimum level of 1.4V, but noise margin is reduced. At
1.8V operation the VIL level is around 0.1V and can
only be used in 1.8V applications with minimal ground
bounce.
The digital input stages draw supply current whenever
the digital input voltage is not at one of the supply
rails. Driving the digital input signals from GND to V+
with a fast transition time minimizes power dissipation.
Typical Performance Curves
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off
isolation is the resistance to this feedthrough.
Figure 21 details the high off isolation rejection
provided by this family. At 100kHz, off isolation in 50
systems is about 74dB with Nx pins connected and
83dB with a single Nx input, decreasing approximately
20dB per decade as frequency increases. Higher load
impedances decrease off isolation rejection due to the
voltage divider action of the switch OFF impedance and
the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND.
One of these diodes conducts if any analog signal
exceeds V+ or GND.
Virtually all the analog leakage current comes from the
ESD diodes to V+ or GND. Although the ESD diodes on
a given signal pin are identical and therefore fairly well
balanced, they are reverse biased differently. Each is
biased by either V+ or GND and the analog signal. This
means their leakages will vary as the signal varies. The
difference in the two diode leakages to the V+ and
GND pins constitutes the analog-signal-path leakage
current. All analog leakage current flows between each
pin and one of the supply terminals, not to the other
switch terminal. This is why both sides of a given
switch can show leakage currents of the same or
opposite polarity. There is no connection between the
analog signal paths and V+ or GND.
TA = +25°C, Unless Otherwise Specified
1.4
1.2
ICOM = 100mA
1.1
1.2
1.0
V+ = 1.8V
1.0
+85°C
0.8
rON ()
rON ()
0.9
0.7
0.6
0.8
+25°C
0.6
0.5
V+ = 2.7V
-40°C
0.4
V+ = 4.5V
V+ = 3V
0.3
0.2
V+ = 1.8V
ICOM = 100mA
0.4
V+ = 5V
0
1
2
VCOM (V)
3
4
5
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE (NX PINS CONNECTED)
8
0.2
0
0.5
1.0
VCOM (V)
1.5
1.8
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE
(NX PINS CONNECTED)
FN6461.2
October 19, 2009
ISL54054, ISL54055
Typical Performance Curves
0.7
TA = +25°C, Unless Otherwise Specified (Continued)
0.45
V+ = 3V
ICOM = 100mA
0.6
+85°C
0.4
+25°C
0.35
+85°C
0.25
+25°C
0.20
0.3
0.15
-40°C
0.2
0.1
V+ = 5V
ICOM = 100mA
0.30
rON ()
rON ()
0.5
0.40
0.10
0
0.5
1.0
1.5
VCOM (V)
2.0
2.5
0.05
3.0
FIGURE 9. ON-RESISTANCE VS SWITCH VOLTAGE
(NX PINS CONNECTED)
-40°C
0
1
2
VCOM (V)
3
4
5
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
(NX PINS CONNECTED)
3.0
2.3
V+ = 1.8V
ICOM = 100mA
ICOM = 100mA
2.1
2.5
1.9
V+ = 1.8V
rON ()
rON ()
1.7
1.5
1.3
1.1
2.0
+85°C
1.5
+25°C
V+ = 2.7V
-40°C
V+ = 3V
V+ = 4.5V
0.9
1.0
0.7
0.5
V+ = 5V
0
1
2
VCOM (V)
3
4
0.5 0
5
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE (SINGLE NX INPUT)
0.5
1.0
VCOM (V)
1.5
1.8
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
1.1
1.6
V+ = 5V
1.0 ICOM = 100mA
V+ = 3V
ICOM = 100mA
1.4
0.9
+85°C
0.8
rON ()
rON ()
1.2
1.0
+25°C
0.7
+25°C
0.6
0.8
0.5
-40°C
0.6
0.4
+85°C
0.4
0
0.5
1.0
1.5
VCOM (V)
2.0
2.5
3.0
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
9
0.3
-40°C
0
1
2
VCOM (V)
3
4
5
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
FN6461.2
October 19, 2009
ISL54054, ISL54055
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
200
30
180
-40°C
160
25
tOFF (ns)
tON (ns)
140
20
+85°C
15
120
100 +25°C
+25°C
80
60
40 +85°C
10
-40°C
5
1.5
2.0
2.5
20
3.0
3.5
V+ (V)
4.0
4.5
5.0
0
1.5
5.5
FIGURE 15. TURN ON TIME vs SUPPLY VOLTAGE
(ISL54054)
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
FIGURE 16. TURN OFF TIME vs SUPPLY VOLTAGE
(ISL54054)
250
30
-40°C
200
25
tON (ns)
tOFF (ns)
+85°C
150
25°C
100
50
2.0
+25°C
15
-40°C
85°C
0
1.5
20
10
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5
1.5
5.5
FIGURE 17. TURN ON TIME vs SUPPLY VOLTAGE
(ISL54055)
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
FIGURE 18. TURN OFF TIME vs SUPPLY VOLTAGE
(ISL54055)
V+ = 5V
1.6
VINH AND VINL (V)
1.2
NORMALIZED GAIN (dB)
1.4
VINH
1.0
VINL
0.8
0.6
0.4
-3
NX PINS CONNECTED
-6
-9
0.2
0
1.5
SINGLE NX INPUT
0
RL = 50
VIN = 0.2VP-P TO 2.8VP-P
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY
VOLTAGE
10
0.1k
1M
10M
FREQUENCY (Hz)
100M
500M
FIGURE 20. FREQUENCY RESPONSE
FN6461.2
October 19, 2009
ISL54054, ISL54055
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
10
V+ = 1.8V TO 5.5V
20 RL = 50
VIN = 1VP-P
30
140
120
V+ = 5V
OFF ISOLATION (dB)
40
100
50
Nx PINS CONNECTED
Q (pC)
60
70
80
60
V+ = 3V
80
40
SINGLE Nx INPUT
90
20
100
110
1k
V+ = 1.8V
0
10k
100k
1M
10M
FREQUENCY (Hz)
100M 500M
FIGURE 21. OFF ISOLATION
0
0.5
1.0
1.5
2.0 2.5 3.0
VCOM (V)
3.5
4.0
4.5
5.0
FIGURE 22. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
57
PROCESS:
Submicron CMOS
11
FN6461.2
October 19, 2009
ISL54054, ISL54055
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
E
L6.1.2x1.0A
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
PIN 1
REFERENCE
2X
0.10C
2X
0.10C
TOP VIEW
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
DETAIL A
0.10C
7X
SYMBOL
D
A
0.08C
A1 A3
SIDE VIEW
C
SEATING
PLANE
4X
e
DETAIL B
1
5X
L
3
L1
-
0.127 REF
b
0.15
0.20
0.25
5
D
0.95
1.00
1.05
-
E
1.15
1.20
1.25
-
e
-
0.40 BSC
L
0.30
0.35
0.40
-
L1
0.40
0.45
0.50
-
N
6
2
Ne
3
3

0
-
4
12
Rev. 2 8/06
NOTES:
6
4
BOTTOM VIEW
b 6X
0.10 C A B
0.05C NOTE 3
1. Dimensioning and tolerancing conform to ASME Y14.51994.
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
0.1x45°
CHAMFER
5. Dimension b applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the
terminal tip.
6. The configuration of the pin #1 identifier is optional, but
must be located within the zone indicated. The pin #1
identifier may be either a mold or mark feature.
A3
A1
7. Maximum package warpage is 0.05mm.
DETAIL A
DETAIL B PIN 1 LEAD
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land
Pattern Design effort, see Intersil Technical Brief TB389.
1.00
1.40
0.20
0.30
0.45
0.20
0.35
0.40
LAND PATTERN 10
12
FN6461.2
October 19, 2009
ISL54054, ISL54055
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
TOLERANCE
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
0.25
0° +3°
-0°
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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13
FN6461.2
October 19, 2009
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