DC1371B - Schematic

5
4
3
2
1
DVCC50
USB
R2
287
PC7(A15/IC.3/CLK0)
PC6(A14/OC.3A)
PC5(A13/OC.3B)
PC4(A12/OC.3C)
PC3(A11/T.3)
PC2(A10)
PC1(A9)
PC0(A8)
R8
10K
DVCC50
U8
8
1
3
RESET_SELF_OUT
SW1
4
SEL1
SEL2
MR
GND
RT
5
2 R151
7 R152
DVCC50
PD7(T0)
PD6(T1)
PD5(XCK1)
PD4(ICP1)
PD3(TXD1/INT3)
PD2(RXD1/INT2)
PD1(OC2B/SDA/INT1)
PD0(OC0B/SCL/INT0)
TP5
6 C270
0.01uF
0603XS
DGND
DGND
Y1
3
C8
DGND
DGND
15pF
0603XS
DGND
63
RS232
PF7(ADC7/TDI)
PF6(ADC6/TDO)
PF5(ADC5/TMS)
PF4(ADC4/TCK)
PF3(ADC3)
PF2(ADC2)
PF1(ADC1)
PF0(ADC0)
ATTACH_PAD
15pF
0603XS
2
C7
TXD
RXD
XTAL1
XTAL2
1
RESET_SELF_IN
MPI1_SPI_CS3
MPI1_SPI_CS2
MPI1_SPI_CS1
MPI1_MISO
MPI1_MOSI
R7
MPI1_SPI_CS0
MPI1_INT6
MPI1_INT5
10K
RESET_SELF_OUT
42
41
40
39
38
37
36
35
MPI1_SPI_CS4
MPI1_SPI4_WP
MPI1_SPI4_CD
USERIO20
USERIO21
USERIO22
USERIO23
32
31
30
29
28
27
26
25
PG_C2M_FMC
PG_M2C_FMC_B
POWER_DONE
USERIO24
TXD
RXD
SDA
SCL
2
1
19
18
9
43
34
33
POWER_RESET
MPI1_INT6
MPI1_INT5
MPI1_CS
USB_ID
MPI1_ALE
MPI1_RD
MPI1_WR
Q1
PDTC144EU
MPI1_MISO
MPI1_MOSI
MPI1_SPI_CLK
DGND
39
MPI1_SPI4_WP
MPI1_SPI4_CD
R9
39
SDA
SCL
RESET
MPI1_RESET
MPI1_RSV0
MPI1_RSV1
PRSNT_FMC
PG_C2M_FMC
PG_M2C_FMC_B
POWER_RESET
POWER_DONE
R11
1K
10K
10K
Q22
PDTC144EU
MPI1_TDI
MPI1_TDO
MPI1_TMS
MPI1_TCK
MPI1_RESET
PRSNT_FMC
MPI1_RSV0
MPI1_RSV1
MPI1_TCK
MPI1_TDO
MPI1_TMS
1
DVCC50
C9
1uF
0603XS
MPI1_TDI
MPI1_ALE
MPI1_WR
MPI1_RD
MPI1_CS
MPI1_CLK
3
3
3
3
3
MPI1_INT6
MPI1_INT5
3
3
MPI1_SPI_CS0
MPI1_SPI_CS1
MPI1_SPI_CS2
MPI1_SPI_CS3
MPI1_SPI_CS4
2
2
3
3
2
D
SDA
SCL
12
12
RESET
MPI1_RESET
2,3
3
MPI1_RSV0
MPI1_RSV1
3
3
C
POWER_RESET 13
POWER_DONE 13
J11
Q2
PDTC144EU
3,8,10
PRSNT_FMC 12
PG_C2M_FMC 12
PG_M2C_FMC_B 12
DVCC50
R165
USERIO[24:0]
MPI1_SPI4_WP 2
MPI1_SPI4_CD 2
MPI1_CLK
R10
3
MPI1_MISO
2,3
MPI1_MOSI
2,3
MPI1_SPI_CLK 2,3
MPI1_SPI_CLK
1
54
55
56
57
58
59
60
61
MPI1_SPI_CS0
MPI1_SPI_CS1
MPI1_SPI_CS2
MPI1_SPI_CS3
MPI1_SPI_CS4
MPI1_AD[7:0]
HEADER 5X2
1
3
5
7
9
2
4
6
8
10
SW2
DVCC50
RESET
B
DGND DVCC50
TRIGGER
C283
65
1
2
3
4
8 MHz
1
DVCC50
24
23
MPI1_XTAL1
MPI1_XTAL2
PE7(INT7/AIN.1/UVCON)
PE6(INT6/AIN0)
PE5(INT5/TOSC2)
PE4(INT4/TOSC1)
PE3(IUID)
PE2(ALE/HWBL)
PE1(RDL)
PE0(WRL)
GND1
GND2
J1
HEADER 4x1
0
0
RESET
1uF
0603XS
RESET
B
20
RESET
22
53
DGND
RST
AGND
C6
VCC
VM
4
C5
0.1uF
LTC2916
17
16
15
14
13
12
11
10
R4
3
DVCC50
MPI1_AD7
MPI1_AD6
MPI1_AD5
MPI1_AD4
MPI1_AD3
MPI1_AD2
MPI1_AD1
MPI1_AD0
2
UGND
C
62
PB7(PCINT7/OC.0A/OC.1C)
PB6(PCINT6/OC.1B)
PB5(PCINT5/OC.1A)
PB4(PCINT4/OC.2A)
PB3(PDO/PCINT3/MISO)
PB2(PDI/PCINT2/MOSI)
PB1(PCINT1/SCLK)
PB0(SS/PCINT0)
U6
SN75240
1
3
5
7
GND1
GND2
GND3
GND4
UGND
UGND
44
45
46
47
48
49
50
51
3
A
B
C
D
P1
USB mini AB REC
PA7(AD7)
PA6(AD6)
PA5(AD5)
PA4(AD4)
PA3(AD3)
PA2(AD2)
PA1(AD1)
PA0(AD0)
2
C3
DVCC50
3
USB_DUSB_D+
USB_ID
VBUS
DD+
UCAP
UGND
MPI1_ALE
MPI1_WR
MPI1_RD
MPI1_CS
MPI1_CLK
2
22
22
8
6
2
4
R174
R175
8
4
5
7
1uF
0603XS 6
0.1uF
0603XS
AVREF
1
2
3
4
5
64
0805XS
VBUS
AVCC
C286
10uF/10V
0805XS
UGND
VBUS
DD+
ID
GND
USERIO[24:0]
AGND
3
21
52
8
9
GND2
GND1
7
6
C1
1
GREEN
GND3
GND4
D
VBUS
UVCC
VCC1
VCC2
2
UGND
MPI1_AD[7:0]
AVCC
LED1
U5 AT90USB1287-16MU
0.1uF
DGND
DGND
AGND
R167 0 1206
VBUS
OPT
DVCC50
DVCC50
DVCC50
CUSTOMER NOTICE
AVCC
AVCC
AGND
A
DGND
DGND
UGND
C10
C12
C13
C14
C11
C15
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
10uF/10V
0805XS
0.1uF
DGND
AGND
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
5
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
1
OF 16
A
5
4
3
2
1
D
D
RESET
3
SI
SO
SCK
RESET
CS
WP
VCC
GND
4
5
MPI1_SPI_CS0 R1
SPI0_WP
R3
10K
10K
MPI1_SPI_CS4
MPI1_MOSI
10K
10K
MPI1_SPI_CLK
6
7
MPI1_MISO
C2
0.1uF
R170
10K
9
1
2
3
4
5
6
7
8
11
DGND
AT45DB642D
C
DGND
U7
1
MPI1_MOSI
8
MPI1_MISO
MPI1_SPI_CLK 2
RESET
3
CS
WP
VCC
GND
AT45DB642D
B
MPI1_SPI4_WP
MPI1_SPI4_CD
C284
0.1uF
13
14
C285
0.1uF
DGND
C
DGND
DVCC33
SI
SO
SCK
RESET
10K
10K
12
DGND
R171
R172
SDC2
SDC3/CD
CMD
VSS1
VDD
CLK
VSS2
SDC0
SDC1 NC0
COM NC1
WP
1
MPI1_MOSI
8
MPI1_MISO
MPI1_SPI_CLK 2
R168
R169
DVCC33
DVCC33
SDCARD
10
U4
P2
CD
DVCC33
4
5
MPI1_SPI_CS1 R5
SPI1_WP
R6
10K
10K
MPI1_SPI_CS0
MPI1_SPI_CS1
MPI1_SPI_CS4
6
7
C4
0.1uF
MPI1_MISO
MPI1_MOSI
MPI1_SPI_CLK
DGND
MPI1_SPI4_WP
MPI1_SPI4_CD
DGND
RESET
CUSTOMER NOTICE
MPI1_SPI_CS0 1
MPI1_SPI_CS1 1
MPI1_SPI_CS4 1
MPI1_MISO
1,3
MPI1_MOSI
1,3
MPI1_SPI_CLK 1,3
B
MPI1_SPI4_WP 1
MPI1_SPI4_CD 1
RESET
1,3
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
5
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
2
OF 16
A
5
4
3
2
U1-19
DVCC33
C19
C20
C21
C22
C23
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DVCC33
DGND
DVCC33
DGND
DVCC33
DVCC33
C
R153
R154
R29
R30
10K
10K
10K
10K
11
12
13
14
15
16
17
18
25
28
MPI1_AD7
MPI1_AD6
MPI1_AD5
MPI1_AD4
MPI1_AD3
MPI1_AD2
MPI1_AD1
MPI1_AD0
MPI1_RESET
MPI1_CS
MPI1_SPI_CS3
MPI1_SPI_CS2
MPI1_MISO
MPI1_MOSI
MPI1_SPI_CLK
MPI1_RSV0
MPI1_RSV1
USERIO18
29
30
32
33
35
36
37
39
RESET
99
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
FB1-1
FB1-2
FB1-3
FB1-4
FB1-5
FB1-6
FB1-7
FB1-8
FB1-9
FB1-10
FB3-1
FB3-2
FB3-3
FB3-4
FB3-5
FB3-6
FB3-7
FB3-8
R31
R32
10K
10K
B
22
23
27
TRST_B
USERIO19
3
4
48
45
83
47
TCK
TDO_SRAMB
TDO_CPLD
TMS
90
FB4-3
GSR
DVCC33
MPI1_CLK
MPI2_INT6
MPI2_INT5
97
96
95
94
93
92
91
FB4-10
FB4-9
FB4-8
FB4-7
FB4-6
FB4-5
FB4-4
FB4-2
FB4-1
FB6-10
FB6-9
FB6-8
FB6-7
FB6-6
FB6-5
FB6-4
FB6-3
FB8-2
FB8-1
FB7-10
FB7-1
FB5-10
FB5-9
FB5-8
FB5-7
GTS1
GTS2
TCK
TDI
TDO
TMS
FB5-6
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
FB7-9
R159 0 1206
DVCC33
DVCC25
R36
A
4.7K
39
10K
330
4.7K
DVCC33
R28
120
0805XS
MPI2_CLK
89
87
86
85
82
81
79
78
MPI2_A7
MPI2_A6
MPI2_A5
MPI2_A4
MPI2_A3
MPI2_A2
MPI2_A1
MPI2_A0
77
76
MPI2_WR
MPI2_RD
74
72
71
70
68
67
66
65
MPI2_DIN7
MPI2_DIN6
MPI2_DIN5
MPI2_DIN4
MPI2_DIN3
MPI2_DIN2
MPI2_DIN1
MPI2_DIN0
64
63
MPI2_CS
MPI2_RSV0
61
60
59
58
56
55
54
53
MPI2_DOUT7
MPI2_DOUT6
MPI2_DOUT5
MPI2_DOUT4
MPI2_DOUT3
MPI2_DOUT2
MPI2_DOUT1
MPI2_DOUT0
52
MPI2_RESET
20
MPI2_RSV1
50
49
42
41
40
MPI2_SPI_CS3 R34
MPI2_SPI_CS2 R35
MPI2_MISO
MPI2_MOSI
39 MPI2_SPI_CLK
0
0
0
U20
W20
T20
R26
0
K20
R27
0
J10
R15
R14
DGND
LED2
FB5-5
FB5-4
FB5-3
FB5-2
FB5-1
R156
2
4
TMS
6
TCK
TDO_CPLD 8
10
TDI
12
TRST_B
14
1
3
5
7
9
11
13
DONE
HEADER 7X2
CCLK_0
CS_B_0
RDWR_B_0
PROGRAM_B_0
D_OUT_BUSY_0
DONE_0
INIT_B_0
RSVD0
RSVD1
VP_0
VN_0
VREFP_0
VREFN_0
M2_0
M1_0
M0_0
AVSS_0
AVDD_0
HSWAPEN_0
FLOAT
J19
P20
R20
N15
P14
P15
N14
M14
M15
N4 DGND
B13
E14
D
D_IN_0
DXP_0
DXN_0
XC5VLX30T
BANK 0
XC5VLX30T
DVCC33
DVCC33
GREEN
C
Q3
PDTC144EU
1
CFG_DONE
TDO_SRAMB
TRST_B
TMS
TCK
TDO_FMC
TDI
TDO_FPGA
MPI1_AD[7:0]
USERIO[24:0]
MPI1_ALE
MPI1_WR
MPI1_RD
MPI1_CS
MPI1_CLK
MPI1_INT6
MPI1_INT5
MPI1_SPI_CS3
MPI1_SPI_CS2
MPI1_MISO
MPI1_MOSI
MPI1_SPI_CLK
DVCC33
R33
10K
RESET
MPI1_RESET
10K
10K
MPI1_RSV0
MPI1_RSV1
TDO_SRAMB
TRST_B
TMS
TCK
TDO_FMC
TDI
TDO_FPGA
4
4,12
4,12
4,12
12
12
4
MPI1_AD[7:0]
1
USERIO[24:0]
MPI1_ALE
MPI1_WR
MPI1_RD
MPI1_CS
MPI1_CLK
1,8,10
1
1
1
1
1
MPI1_INT6
MPI1_INT5
1
1
MPI1_SPI_CS3
MPI1_SPI_CS2
MPI1_MISO
MPI1_MOSI
MPI1_SPI_CLK
1
1
1,2
1,2
1,2
RESET
MPI1_RESET
1,2
1
MPI1_RSV0
MPI1_RSV1
1
1
C31
C32
C24
C27
C28
C29
C30
0.1uF
0.1uF
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
DGND
DGND
U1-2
CUSTOMER NOTICE
MPI2_SPI_CS3
MPI2_SPI_CS2
MPI2_MISO
MPI2_MOSI
MPI2_SPI_CLK
MPI2_RESET
MPI2_INT5
MPI2_INT6
MPI2_RSV0
MPI2_RSV1
USERIO16
USERIO17
Y10
W11
Y12
AA12
AA17
Y17
AA19
Y20
Y11
AA10
Y18
AA18
MPI2_DOUT7
MPI2_DOUT6
MPI2_DOUT5
MPI2_DOUT4
MPI2_DOUT3
MPI2_DOUT2
MPI2_DOUT1
MPI2_DOUT0
AA13
AA14
Y16
W16
Y13
W14
Y15
AA15
DVCC33
IO_L0N_CC_RS0_2
VCCO_20
IO_L0P_CC_RS1_2
VCCO_21
IO_L4P_FCS_B_2
IO_L4N_VREF_FOE_B_MOSI_2
IO_L5P_FWE_B_2
IO_L5N_CSO_B_2
IO_L1N_CC_A24_2
IO_L1P_CC_A25_2
IO_L2N_A22_2
IO_L2P_A23_2
IO_L3N_A20_2
IO_L3P_A21_2
IO_L6P_D7_2
IO_L6N_D6_2
IO_L7P_D5_2
IO_L7N_D4_2
IO_L8P_D3_2
IO_L8N_D2_FS2_2
IO_L9P_D1_FS1_2
IO_L9N_D0_FS0_2
DGND
No Bypass
3
2
JP1
1
DGND
TDO_FMC
TDO_FMC_JP
TDI
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
AA16
AD17
B
SIZE
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
NOTES: UNLESS OTHERWISE SPECIFIED
5
IO_L0N_A18_1
VCCO_10
IO_L0P_A19_1
VCCO_11
IO_L1N_A16_1
IO_L1P_A17_1
IO_L5N_A8_D24_1
IO_L5P_A9_D25_1
IO_L6N_A6_D22_1
IO_L6P_A7_D23_1
IO_L7N_A4_D20_1
IO_L7P_A5_D21_1
IO_L8N_CC_A2_D18_1
IO_L8P_CC_A3_D19_1
IO_L9N_CC_A0_D16_1
IO_L9P_CC_A1_D17_1
IO_L2N_A14_D30_1
IO_L2P_A15_D31_1
IO_L3N_A12_D28_1
IO_L3P_A13_D29_1
IO_L4N_VREF_A10_D26_1
IO_L4P_A11_D27_1
XC5VLX30T
Bypass FMC
J2
J11
L20
M20
J20
U12
K11
H12
R21
R22
R23
21
31
44
62
69
75
84
100
R160 0 1206
R155
R18
R19
R20
CFG_CCLK
CFG_CS
CFG_WR
CFG_PROGRAM
CFG_BUSY
OPT
CFG_DONE
CFG_INT
DVCC33
DGND
FB6-2
FB6-1
FB8-10
FB8-9
FB8-8
FB8-7
FB8-6
FB8-5
FB8-4
FB8-3
GCK1
GCK2
GCK3
CFG_CCLK
CFG_CS
CFG_WR
CFG_PROGRAM
CFG_BUSY
CFG_DONE
CFG_INT
100 1%
100 1%
10K
10K
VBATT_0
G16
G15
G14
H13
G12
F13
H19
H18
H11
G11
H21
G20
H9
G10
F17
G17
F14
F15
G19
F18
MPI2_CLK
MPI2_A7
MPI2_A6
MPI2_A5
MPI2_A4
MPI2_A3
MPI2_A2
MPI2_A1
MPI2_A0
MPI2_CS
MPI2_WR
MPI2_RD
MPI2_DIN7
MPI2_DIN6
MPI2_DIN5
MPI2_DIN4
MPI2_DIN3
MPI2_DIN2
MPI2_DIN1
MPI2_DIN0
DVCC33
32
10K
10K
FB2-1
FB2-2
FB2-3
FB2-4
FB2-5
XC9572XL-5
R24
R25
1
6
8
9
10
MPI1_ALE
MPI1_WR
MPI1_RD
MPI1_INT6
MPI1_INT5
DVCC33
5
57
98
26
38
51
88
U9
R14
R15
R16
R17
VCCO_01
VCCO_00
BANK 2
C18
TCK_0
TDI_0
TDO_0
TMS_0
J12
F11
BANK 1
C17
1
C16
DGND
DVCC33
DVCC33
U1-1
V11
V13
V12
W13
TCK
TDO_FMC_JP
TDO_FPGA
TMS
2
D
1
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
3
OF 16
A
5
4
3
2
1
U2A
DVCC25
W22
R24
V25
VCCO_130
VCCO_131
VCCO_132
IO_L10P_CC_13
IO_L10N_CC_13
IO_L11P_CC_13
IO_L11N_CC_13
DVCC25
IO_L4P_13
R40
49.9 1%
Y26
Y25
R44
49.9 1%
DGND
BANK 13
C
IO_L2P_SM6P_13
IO_L3P_SM5P_13
IO_L7P_SM2P_13
IO_L16P_13
IO_L12P_VRN_13
IO_L16N_13
IO_L12N_VRP_13IO_L3N_SM5N_13
IO_L2N_SM6N_13
IO_L6P_SM3P_13
IO_L17N_13
IO_L18N_13
IO_L9P_CC_SM0P_13
IO_L13P_13
IO_L13N_13
IO_L14P_13
IO_L15P_13
IO_L15N_13
IO_L19N_13
IO_L19P_13
IO_L14N_VREF_13
IO_L18P_13
IO_L6N_SM3N_13
IO_L17P_13
IO_L0P_SM8P_13
IO_L1P_SM7P_13
IO_L1N_SM7N_13
IO_L0N_SM8N_13
IO_L5N_SM4N_13
IO_L5P_SM4P_13
IO_L8N_CC_SM1N_13
IO_L8P_CC_SM1P_13
IO_L7N_SM2N_13
IO_L4N_VREF_13
IO_L9N_CC_SM0N_13
AA22
Y22
Y23
W23
CLKA
CE1_B_A
ADV_LDA_B_A
RD_WR_B_A
U26
CEN_B_A
P24
R23
U24
P21
R21
R22
P23
T24
U22
V22
W24
AA25
AB26
AB25
AB24
AA23
W21
V21
AA24
U21
T23
T22
P26
P25
R25
R26
T25
U25
W25
W26
V24
V26
V23
DA31
DA30
DA29
DA28
DA27
DA26
DA25
DA24
DA23
DA22
DA21
DA20
DA19
DA18
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DPA1
A9
R8
A10
R3
R11
P9
P4
P10
R10
B2
B10
R4
A2
R9
B9
P3
P8
P6
R6
AA18
AA17
AA16
AA15
AA14
AA13
AA12
AA11
AA10
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
D
B4
A4
A5
B5
TP6
DVCC25
TP8
DVCC25
A3
A6
B3
H11
CE1_B_A
R47
10K
R49
10K
B6
A8
B7
B8
A7
R1
CLKA
ADV_LDA_B_A
RD_WR_B_A
CEN_B_A
R7
R5
P5
P7
TCK
TMS
TDO_FPGA
TDO_SRAMA_R
R53
0
OPT
XC5VLX30T
U3A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A1
A0
DQPd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
BWd#
BWc#
BWb#
BWa#
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
CE#
CE2#
CE2
ZZ
CLK
ADV
WE#
OE#
CKE#
MODE
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
TCK
TMS
TDI
TDO
N1
K1
K2
J2
J1
L1
L2
M2
M1
DPA4
DA26
DA25
DA27
DA28
DA29
DA31
DA30
DA24
C1
E2
D2
D1
G2
E1
F1
G1
F2
DPA3
DA16
DA23
DA22
DA20
DA17
DA18
DA19
DA21
C11
E11
F10
D11
E10
D10
F11
G11
G10
DPA2
DA12
DA11
DA13
DA14
DA15
DA10
DA9
DA8
N11
J11
L11
J10
K10
K11
M11
M10
L10
DPA1
DA6
DA1
DA7
DA4
DA5
DA3
DA2
DA0
U1-11
DVCC25
J22
M23
H25
VCCO_110
VCCO_111
VCCO_112
DVCC25
IO_L8P_CC_11
IO_L8N_CC_11
IO_L9P_CC_11
IO_L9N_CC_11
IO_L0P_11
R39
49.9 1%
H24
J24
R43
49.9 1%
DGND
IO_L4N_VREF_11
IO_L5N_11
IO_L6P_11
IO_L4P_11
IO_L12P_VRN_11
IO_L3N_11
IO_L12N_VRP_11
IO_L7N_11
IO_L5P_11
IO_L6N_11
IO_L17N_SM11N_11
IO_L15P_SM13P_11
IO_L3P_11
IO_L19P_SM9P_11
IO_L1P_11
IO_L7P_11
IO_L1N_11
IO_L13P_11
IO_L13N_11
IO_L15N_SM13N_11
IO_L2P_11
IO_L2N_11
IO_L0N_11
IO_L14P_11
IO_L11N_CC_SM14N_11
IO_L14N_VREF_11
IO_L17P_SM11P_11
IO_L10P_CC_SM15P_11
IO_L16N_SM12N_11
IO_L10N_CC_SM15N_11
IO_L19N_SM9N_11
IO_L11P_CC_SM14P_11
IO_L18P_SM10P_11
IO_L16P_SM12P_11
IO_L18N_SM10N_11
BANK 11
U1-13
J21
K21
K22
K23
CLKB
CE1_B_B
ADV_LDA_B_B
RD_WR_B_B
E26
CEN_B_B
E22
F22
G22
E23
G24
J23
F23
H22
M24
L24
F24
N22
F25
H23
G26
J25
J26
K25
H26
G25
E25
K26
N21
L25
M25
L23
M26
L22
M22
M21
N24
N26
N23
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DPB1
TDO_SRAMA
B4
A4
A5
B5
TP7
DVCC25
DVCC25
A3
A6
B3
H11
CE1_B_B
TP9
R50
10K
R48
10K
R54
0
OPT
XC5VLX30T
C35
C36
C37
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
DGND
DVCC25
DVCC25
R84
49.9 1%
C148
C152
C153
C154
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
AF19
AF18
A
R85
49.9 1%
VCCO_170
VCCO_171
VCCO_172
IO_L12P_VRN_17
IO_L12N_VRP_17
IO_L8P_CC_17
IO_L1P_17
IO_L9P_CC_17
IO_L1N_17
IO_L7N_17
IO_L0P_17
IO_L3P_17
IO_L6N_17
IO_L7P_17
IO_L4N_VREF_17
IO_L8N_CC_17
IO_L2P_17
IO_L4P_17
IO_L6P_17
IO_L5P_17
IO_L3N_17
IO_L2N_17
IO_L0N_17
IO_L5N_17
TDO_SRAMB
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
5
AF22
AD25
AF20
AD24
AB22
AC26
AF25
AC23
AC22
AE23
AE21
AE25
AF23
AC24
AE22
AF24
AE26
AD26
AD23
AA18
AA17
AA16
AA15
AA14
AA13
AA12
AA11
AA10
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
XC5VLX30T
Open solder mask on pin A3, B6 of U2
and A3, B6 of U3 on bottom side to
make test points
4
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
CE#
CE2#
CE2
ZZ
CLK
ADV
WE#
OE#
CKE#
MODE
TCK
TMS
TDI
TDO
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DPB4
DB27
DB25
DB26
DB24
DB28
DB29
DB30
DB31
C1
E2
D2
D1
G2
E1
F1
G1
F2
DPB3
DB23
DB20
DB22
DB21
DB16
DB18
DB19
DB17
C11
E11
F10
D11
E10
D10
F11
G11
G10
DPB2
DB9
DB12
DB8
DB14
DB10
DB15
DB13
DB11
N11
J11
L11
J10
K10
K11
M11
M10
L10
DPB1
DB5
DB0
DB6
DB4
DB1
DB7
DB3
DB2
D
C
TDO_SRAMB_R
TMS
TCK
TDO_FPGA
TDO_SRAMB
C38
C39
C40
0.1uF
0.1uF
0.1uF
DPA[4:1]
DPB[4:1]
B
TMS
TCK
TDO_FPGA
TDO_SRAMB
3,12
3,12
3
3
DPA[4:1]
10
DPB[4:1]
10
DGND
CUSTOMER NOTICE
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
DGND
BWd#
BWc#
BWb#
BWa#
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
N1
K1
K2
J2
J1
L1
L2
M2
M1
R158 0
DGND
NOTES: UNLESS OTHERWISE SPECIFIED
DQPd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
IS61NVP51236
DVCC25
BANK 17A
C33
AC20
AB23
AE24
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A1
A0
DGND
TDO_SRAMA_R
U1-17
DVCC25
DVCC25
R7
R5
P5
P7
TCK
TMS
TDO_SRAMA
TDO_SRAMB_R
R157 0
B
B6
A8
B7
B8
A7
R1
CLKB
ADV_LDA_B_B
RD_WR_B_B
CEN_B_B
IS61NVP51236
DGND
A9
R8
A10
R3
R11
P9
P4
P10
R10
B2
B10
R4
A2
R9
B9
P3
P8
P6
R6
AA18
AA17
AA16
AA15
AA14
AA13
AA12
AA11
AA10
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
4
OF 16
A
5
4
3
2
1
DVCC25
D
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C51
C52
C53
C54
C55
C56
C57
C58
C59
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C292
C288
C289
C291
C294
C295
C297
C299
C301
C303
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
D
DGND
DVCC25
DVCC25
DVCC25
U2B
N3
L3
F3
G3
N9
M3
K9
E3
G9
J9
C9
J3
K3
F9
E9
D3
C3
D9
M9
L9
C
C5
D5
E5
F5
G5
H5
J5
K5
F6
M5
D7
E7
F7
C6
N8
E6
D6
G6
H6
M6
C8
C4
L5
J7
J6
K6
L6
G7
H7
N4
K7
L7
M7
C7
B
DGND
A
U3B
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
F4
M8
H8
G4
H2
K4
G8
M4
D8
J4
E4
L4
K8
H4
F8
L8
J8
D4
E8
N3
L3
F3
G3
N9
M3
K9
E3
G9
J9
C9
J3
K3
F9
E9
D3
C3
D9
M9
L9
N7
C10
P2
P1
H1
B1
R2
N5
B11
N10
A1
N2
A11
C2
P11
H10
N6
H3
H9
C5
D5
E5
F5
G5
H5
J5
K5
F6
M5
D7
E7
F7
C6
N8
E6
D6
G6
H6
M6
C8
C4
L5
J7
J6
K6
L6
G7
H7
N4
K7
L7
M7
C7
IS61NVP51236
DGND
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vddq
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
Vdd
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IS61NVP51236
F4
M8
H8
G4
H2
K4
G8
M4
D8
J4
E4
L4
K8
H4
F8
L8
J8
D4
E8
DGND
DVCC25
C
DGND
DVCC25
N7
C10
P2
P1
H1
B1
R2
N5
B11
N10
A1
N2
A11
C2
P11
H10
N6
H3
H9
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C71
C72
C73
C74
C75
C76
C77
C78
C79
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DGND
DVCC25
B
DGND
DVCC25
C308
C304
C306
C309
C311
C312
C314
C316
C318
C319
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DGND
CUSTOMER NOTICE
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
ALL CAPACITORS ARE 0402
5
4
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
5
OF 16
A
5
R55
4
10K
3
DVCC25
R56
DGND
DGND
1
2
3
REFCLK_116_P 7
REFCLK_116_N 7
CLK_116_P
8
CLK_116_N
8
CLK_116_SEL 10
CLK_116_ON 10
CLK_IODLY_P
CLK_IODLY_N
CLK_IODLY_ON
R65
DVCC25
OE
NC
GND
VCC
OUT
OUT
6
4
5
CLK_IODLY_P
CLK_IODLY_N
C91
C92
C93
10uF/10V
0805XS
0.1uF
0.01uF
1
2
3
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
0.1uF
IN1
IN1
VT1
Q1
Q1
VREF_AC1
SEL
NC
C97
0.01uF
DGND
R71
10K
DGND
SY89474U
PAD
15
Q0
Q0
VREF_AC0
25
10uF/10V
0805XS
23
20
22
CLK_116_SEL
C96
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
10K
U16
OE
NC
GND
VCC
OUT
OUT
6
4
5
5
2
4
CLK_118_OSCIN_P
CLK_118_OSCIN_N
EG2121CA 105.0000MHz
OPT
CLK_118_EXTIN_P
CLK_118_EXTIN_N
23
20
22
DGND
7
8
3
11
12
21
REFCLK_116_C_P
REFCLK_116_C_N
C277
C278
0.1uF
0.1uF
REFCLK_114_P
REFCLK_114_N
D
16
PAD
DVCC25
C89
C90
0.1uF
0.01uF
DGND
CLK_112_EXTIN_P
CLK_112_EXTIN_N
CLK_114_EXTIN_P
CLK_114_EXTIN_N
CLK_116_EXTIN_P
CLK_116_EXTIN_N
CLK_118_EXTIN_P
CLK_118_EXTIN_N
REFCLK_114_P 7
REFCLK_114_N 7
CLK_114_P
8
CLK_114_N
8
CLK_114_SEL 10
CLK_114_ON 10
IN0
IN0
VT0
Q0
Q0
VREF_AC0
IN1
IN1
VT1
Q1
Q1
VREF_AC1
SEL
NC
REFCLK_116_P
REFCLK_116_N
C95
10uF/10V
0805XS
CLK_116_P
CLK_116_N
C100
0.1uF
C101
0.01uF
DGND
16
15
CLK_118_SEL
SY89474U
R72
10K
DGND
CLK_112_EXTIN_P
CLK_112_EXTIN_N
CLK_114_EXTIN_P
CLK_114_EXTIN_N
CLK_116_EXTIN_P
CLK_116_EXTIN_N
CLK_118_EXTIN_P
CLK_118_EXTIN_N
12
12
12
12
12
12
12
12
C
CUSTOMER NOTICE
11
12
21
CLK_118_P
CLK_118_N
16
C275
C276
0.1uF
0.1uF
REFCLK_118_P
REFCLK_118_N
B
DVCC25
C102
C103
0.1uF
0.01uF
DGND
C98
C99
0.1uF
0.01uF
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
REFCLK_118_C_P
REFCLK_118_C_N
DVCC25
DGND
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
7
8
3
DGND
NOTES: UNLESS OTHERWISE SPECIFIED
5
CLK_114_P
CLK_114_N
0.1uF
0.1uF
DVCC25
DVCC25
DVCC25
IN0
IN0
VT0
GND1
GND2
GND3
C94
A
5
2
4
CLK_116_OSCIN_P
CLK_116_OSCIN_N
EG2121CA 105.0000MHz
OPT
CLK_116_EXTIN_P
CLK_116_EXTIN_N
DVCC25
REFCLK_114_P
REFCLK_114_N
CLK_114_P
CLK_114_N
CLK_114_SEL
CLK_114_ON
1
6
9
10
13
19
24
U15
DVCC25
11
12
21
C272
C274
DGND
DVCC25
14
17
18
DGND
0.01uF
DGND
Y5
10K
6
4
5
NC
REFCLK_114_C_P
REFCLK_114_C_N
DGND
DGND
VCC
OUT
OUT
SEL
SY89474U
R62
10K
REFCLK_118_P 7
REFCLK_118_N 7
CLK_118_P
8
CLK_118_N
8
CLK_118_SEL 10
CLK_118_ON 10
R66
CLK_IODLY_P 8
CLK_IODLY_N 8
CLK_IODLY_ON 10
DGND
OE
NC
GND
Q1
Q1
VREF_AC1
DGND
B
1
2
3
IN1
IN1
VT1
7
8
3
CLK_118_ON
CLK_116_ON
Y6
Q0
Q0
VREF_AC0
DVCC25
EG2121CA 200.0000MHz
DGND
15
IN0
IN0
VT0
C88
0.1uF
REFCLK_118_P
REFCLK_118_N
CLK_118_P
CLK_118_N
CLK_118_SEL
CLK_118_ON
DGND
Y4
C87
DGND
10K
23
20
22
CLK_114_SEL
10uF/10V
0805XS
CLK_IODLY_ON
REFCLK_112_P 7
REFCLK_112_N 7
CLK_112_P
8
CLK_112_N
8
CLK_112_SEL 10
CLK_112_ON 10
REFCLK_116_P
REFCLK_116_N
CLK_116_P
CLK_116_N
CLK_116_SEL
CLK_116_ON
EG2121CA 105.0000MHz
OPT
CLK_114_EXTIN_P
CLK_114_EXTIN_N
C82
0.01uF
5
2
4
CLK_114_OSCIN_P
CLK_114_OSCIN_N
GND1
GND2
GND3
REFCLK_112_P
REFCLK_112_N
CLK_112_P
CLK_112_N
CLK_112_SEL
CLK_112_ON
C86
0.1uF
DGND
6
4
5
DVCC25
C85
R63
C
DVCC25
VCC
OUT
OUT
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
DGND
16
OE
NC
GND
PAD
SY89474U
R61
10K
0.01uF
1
2
3
REFCLK_112_P
REFCLK_112_N
25
C84
0.1uF
CLK_112_P
CLK_112_N
0.1uF
0.1uF
25
NC
11
12
21
C271
C273
GND1
GND2
GND3
SEL
REFCLK_112_C_P
REFCLK_112_C_N
14
17
18
10uF/10V
0805XS
Q1
Q1
VREF_AC1
14
17
18
C83
IN1
IN1
VT1
7
8
3
PAD
15
CLK_112_SEL
C81
Q0
Q0
VREF_AC0
GND1
GND2
GND3
DVCC25
IN0
IN0
VT0
DGND
23
20
22
U11
DVCC25
14
17
18
5
2
4
CLK_112_OSCIN_P
CLK_112_OSCIN_N
25
6
4
5
VCC
OUT
OUT
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
DVCC25
Y3
1
6
9
10
13
19
24
U10
EG2121CA 105.0000MHz
OPT
CLK_112_EXTIN_P
CLK_112_EXTIN_N
DGND
DVCC25
DGND
1
6
9
10
13
19
24
DGND
D
10K
CLK_114_ON
Y2
OE
NC
GND
1
1
6
9
10
13
19
24
CLK_112_ON
1
2
3
2
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
6
OF 16
A
5
4
3
FB2
FB3
AVCC10_1120 C104
AVCC10_1121 C105
0.22uF
0.22uF
AVTT12
FB4
FB5
FB6
FB7
AVTT12_1120
AVTT12_1121
AVTT12_1122
AVTT12_1123
C106
C107
C108
C109
0.22uF
0.22uF
0.22uF
0.22uF
R73
49.9 1%
AVPLL12
AVCC10_1120
AVCC10_1121
L3
L4
AVTT12_1120
AVTT12_1121
H3
N3
AVTT12_1122
J3
AVPLL12_1120
M3
AVTT12_1123
AVTT12_R_1121
FB8
AVPLL12_1120 C110
FB9
FB10
AVCC10_1140 C111
AVCC10_1141 C112
0.22uF
0.22uF
C113
C114
C115
0.22uF
0.22uF
0.22uF
AVTT12_1140
AVTT12_1141
AVTT12_1142
MGTAVCC_1120
MGTAVCC_1121
MGTREFCLKP_112
MGTREFCLKN_112
MGTAVTTTX_1120
MGTAVTTTX_1121
MGTTXP0_112
MGTTXN0_112
MGTAVTTRX_112
MGTTXP1_112
MGTTXN1_112
MGTAVCCPLL_112
MGTRXP0_112
MGTRXN0_112
MGTAVTTRXC
MGTRREF_112
MGTRXP1_112
MGTRXN1_112
AVTT12
FB11
FB12
FB13
P5
P4
0.22uF
AVCC10
C
AVCC10_1140
AVCC10_1141
U3
U4
AVTT12_1140
AVTT12_1141
P3
W3
AVTT12_1142
R3
AVPLL12_1140
V3
MGTAVCC_1140
MGTAVCC_1141
MGTREFCLKP_114
MGTREFCLKN_114
MGTAVTTTX_1140
MGTAVTTTX_1141
MGTTXP0_114
MGTTXN0_114
MGTAVTTRX_114
MGTTXP1_114
MGTTXN1_114
MGTAVCCPLL_114
MGTRXP0_114
MGTRXN0_114
AVPLL12
FB14
AVPLL12_1140 C116
MGTRXP1_114
MGTRXN1_114
0.22uF
AVCC10
FB15
FB16
AVCC10_1160 C117
AVCC10_1161 C118
0.22uF
0.22uF
AVTT12
FB17
FB18
FB19
AVTT12_1160
AVTT12_1161
AVTT12_1162
C119
C120
C121
0.22uF
0.22uF
0.22uF
AVCC10_1160
AVCC10_1161
E3
E4
AVTT12_1160
AVTT12_1161
B3
G3
AVTT12_1162
C3
AVPLL12_1160
F3
MGTAVCC_1160
MGTAVCC_1161
MGTREFCLKP_116
MGTREFCLKN_116
MGTAVTTTX_1160
MGTAVTTTX_1161
MGTTXP0_116
MGTTXN0_116
MGTAVTTRX_116
MGTTXP1_116
MGTTXN1_116
MGTAVCCPLL_116
MGTRXP0_116
MGTRXN0_116
AVPLL12
FB20
B
1
U1-5
AVCC10
D
2
AVPLL12_1160 C122
MGTRXP1_116
MGTRXN1_116
0.22uF
AVCC10
FB21
FB22
AVCC10_1180 C123
AVCC10_1181 C124
0.22uF
0.22uF
AVTT12
FB23
FB24
FB25
AVTT12_1180
AVTT12_1181
AVTT12_1182
C125
C126
C127
0.22uF
0.22uF
0.22uF
AVCC10_1180
AVCC10_1181
AC3
AC4
AVTT12_1180
AVTT12_1181
Y3
AE3
AVTT12_1182
AA3
AVPLL12_1180
AD3
MGTAVCC_1180
MGTAVCC_1181
MGTREFCLKP_118
MGTREFCLKN_118
MGTAVTTTX_1180
MGTAVTTTX_1181
MGTTXP0_118
MGTTXN0_118
MGTAVTTRX_118
MGTTXP1_118
MGTTXN1_118
MGTAVCCPLL_118
MGTRXP0_118
MGTRXN0_118
AVPLL12
BANK NAA
FB26
AVPLL12_1180 C128
MGTRXP1_118
MGTRXN1_118
K4
K3
REFCLK_112_N
REFCLK_112_P
H2
J2
MGTTXN0_112
MGTTXP0_112
N2
M2
MGTTXP1_112
MGTTXN1_112
J1
K1
MGTRXN0_112
MGTRXP0_112
M1
L1
MGTRXP1_112
MGTRXN1_112
T4
T3
REFCLK_114_N
REFCLK_114_P
MGTTXP1_116
MGTTXN1_116
P2
R2
MGTTXN0_114
MGTTXP0_114
MGTTXP0_118
MGTTXN0_118
W2
V2
MGTTXP1_114
MGTTXN1_114
MGTTXP1_118
MGTTXN1_118
R1
T1
MGTRXN0_114
MGTRXP0_114
V1
U1
MGTRXP1_114
MGTRXN1_114
MGTTXP0_112
MGTTXN0_112
MGTTXP1_112
MGTTXN1_112
MGTTXP0_114
MGTTXN0_114
MGTTXP1_114
MGTTXN1_114
MGTTXP0_116
MGTTXN0_116
MGTRXP0_112
MGTRXN0_112
MGTRXP1_112
MGTRXN1_112
D4
D3
REFCLK_116_N
REFCLK_116_P
B2
C2
MGTTXN0_116
MGTTXP0_116
G2
F2
MGTTXP1_116
MGTTXN1_116
C1
D1
MGTRXN0_116
MGTRXP0_116
F1
E1
MGTRXP1_116
MGTRXN1_116
AB4
AB3
REFCLK_118_N
REFCLK_118_P
Y2
AA2
MGTTXN0_118
MGTTXP0_118
AE2
AD2
MGTTXP1_118
MGTTXN1_118
AA1
AB1
MGTRXN0_118
MGTRXP0_118
AD1
AC1
MGTRXP1_118
MGTRXN1_118
MGTRXP0_114
MGTRXN0_114
MGTRXP1_114
MGTRXN1_114
MGTRXP0_116
MGTRXN0_116
MGTRXP1_116
MGTRXN1_116
MGTRXP0_118
MGTRXN0_118
MGTRXP1_118
MGTRXN1_118
MGTTXP0_112 12
MGTTXN0_112 12
D
MGTTXP1_112 12
MGTTXN1_112 12
MGTTXP0_114 12
MGTTXN0_114 12
MGTTXP1_114 12
MGTTXN1_114 12
MGTTXP0_116 12
MGTTXN0_116 12
MGTTXP1_116 12
MGTTXN1_116 12
MGTTXP0_118 12
MGTTXN0_118 12
MGTTXP1_118 12
MGTTXN1_118 12
C
MGTRXP0_112 12
MGTRXN0_112 12
MGTRXP1_112 12
MGTRXN1_112 12
MGTRXP0_114 12
MGTRXN0_114 12
MGTRXP1_114 12
MGTRXN1_114 12
MGTRXP0_116 12
MGTRXN0_116 12
MGTRXP1_116 12
MGTRXN1_116 12
MGTRXP0_118 12
MGTRXN0_118 12
MGTRXP1_118 12
MGTRXN1_118 12
B
REFCLK_112_P
REFCLK_112_N
REFCLK_114_P
REFCLK_114_N
REFCLK_116_P
REFCLK_116_N
REFCLK_118_P
REFCLK_118_N
0.22uF
XC5VLX30T
REFCLK_112_P 6
REFCLK_112_N 6
REFCLK_114_P 6
REFCLK_114_N 6
REFCLK_116_P 6
REFCLK_116_N 6
REFCLK_118_P 6
REFCLK_118_N 6
DGND
CUSTOMER NOTICE
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
NOTES: UNLESS OTHERWISE SPECIFIED
SIZE
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
3. ALL FERRITE BEADS ARE MPZ1608S221A
5
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
7
OF 16
A
5
4
3
2
1
D
D
U1-3
XC5VLX30T
U1-4
DVCC25
R74
49.9 1%
OPT
D14
D13
VCCO_30
VCCO_31
IO_L0P_CC_GC_3
IO_L0N_CC_GC_3
IO_L1P_CC_GC_3
IO_L1N_CC_GC_3
IO_L3P_GC_3
IO_L3N_GC_3
IO_L4P_GC_3
IO_L4N_GC_VREF_3
IO_L5P_GC_3
IO_L5N_GC_3
IO_L6P_GC_3
IO_L6N_GC_3
IO_L7P_GC_3
IO_L7N_GC_3
IO_L8P_GC_3
IO_L8N_GC_3
IO_L2P_GC_VRN_3
IO_L9P_GC_3
IO_L2N_GC_VRP_3
IO_L9N_GC_3
BANK 3
D17
G18
C
D15
E15
D16
E16
E17
D18
E13
E12
E18
F19
F12
E11
E20
E21
E10
F10
F20
G21
AB13
AE14
LPC_CC_N17
LPC_CC_P17
LPC_CC_N18
LPC_CC_P18
USERIO12
USERIO13
CLK_116_N
CLK_116_P
HPC_CC_N24
HPC_CC_P24
DVCC25
USERIO14
USERIO15
CLK_IODLY_N
CLK_IODLY_P
R75
49.9 1%
OPT
AB14
AC14
CLK_112_P
CLK_112_N
EXT_TRIG0_P
EXT_TRIG0_N
R76
49.9 1%
OPT
VCCO_40
VCCO_41
IO_L8P_CC_GC_4
IO_L8N_CC_GC_4
IO_L9P_CC_GC_4
IO_L9N_CC_GC_4
IO_L0N_GC_D14_4
IO_L0P_GC_D15_4
IO_L1N_GC_D12_4
IO_L1P_GC_D13_4
IO_L2P_GC_D11_4
IO_L2N_GC_D10_4
IO_L3P_GC_D9_4
IO_L3N_GC_D8_4
IO_L4P_GC_4
IO_L4N_GC_VREF_4
IO_L5P_GC_4
IO_L5N_GC_4
IO_L7P_GC_VRN_4
IO_L6P_GC_4
IO_L7N_GC_VRP_4
IO_L6N_GC_4
AC17
AB16
AB15
AC16
AA20
Y21
AB11
AB10
AB21
AB20
AC11
AB12
AB19
AC19
AC12
AC13
AC18
AB17
HPC_CC_P17
HPC_CC_N17
HPC_CC_N1
HPC_CC_P1
CLK0_C2M_P
CLK0_C2M_N
CLK1_C2M_P
CLK1_C2M_N
CLK0_C2M_N
CLK0_C2M_P
CLK_118_N
CLK_118_P
CLK_114_P
CLK_114_N
HPC_CC_N0
HPC_CC_P0
LPC_CC_N0
LPC_CC_P0
LPC_CC_N1
LPC_CC_P1
CLK1_C2M_P
CLK1_C2M_N
R77
49.9 1%
OPT
DVCC25
DVCC25
DGND
LPC_CC_P0
LPC_CC_N0
LPC_CC_P1
LPC_CC_N1
LPC_CC_P17
LPC_CC_N17
LPC_CC_P18
LPC_CC_N18
HPC_CC_P0
HPC_CC_N0
HPC_CC_P1
HPC_CC_N1
HPC_CC_P17
HPC_CC_N17
HPC_CC_P24
HPC_CC_N24
HPC_CC_P30
HPC_CC_N30
HPC_CC_P41
HPC_CC_N41
DGND
C131
C132
C133
C134
0.1uF
0.01uF
0.1uF
0.01uF
DGND
B
XC5VLX30T
DVCC25
BANK 4
DVCC25
CLK_112_P
CLK_112_N
CLK_114_P
CLK_114_N
CLK_116_P
CLK_116_N
CLK_118_P
CLK_118_N
DGND
J3
SMA
CLK_IODLY_P
CLK_IODLY_N
CLK0_C2M_P
CLK0_C2M_N
CLK1_C2M_P
CLK1_C2M_N
12
12
12
12
LPC_CC_P0
LPC_CC_N0
LPC_CC_P1
LPC_CC_N1
LPC_CC_P17
LPC_CC_N17
LPC_CC_P18
LPC_CC_N18
HPC_CC_P0
HPC_CC_N0
HPC_CC_P1
HPC_CC_N1
HPC_CC_P17
HPC_CC_N17
HPC_CC_P24
HPC_CC_N24
HPC_CC_P30
HPC_CC_N30
HPC_CC_P41
HPC_CC_N41
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
9,12
9,12
10,12
10,12
CLK_112_P
CLK_112_N
CLK_114_P
CLK_114_N
CLK_116_P
CLK_116_N
CLK_118_P
CLK_118_N
6
6
6
6
6
6
6
6
C
B
CLK_IODLY_P 6
CLK_IODLY_N 6
EXT_TRIG0_P
USERIO[24:0]
USERIO[24:0]
1,3,10
DGND
J4
SMA
EXT_TRIG0_N
CUSTOMER NOTICE
DGND
A
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
5
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
8
OF 16
A
5
4
3
2
1
D
D
VCCO_160
VCCO_161
VCCO_162
IO_L0P_16
IO_L0N_16
IO_L1P_16
IO_L1N_16
IO_L2P_16
IO_L2N_16
IO_L3P_16
IO_L3N_16
IO_L4P_16
IO_L4N_VREF_16
IO_L5P_16
IO_L5N_16
IO_L6P_16
IO_L6N_16
IO_L7P_16
IO_L7N_16
IO_L8P_CC_16
IO_L8N_CC_16
IO_L9P_CC_16
IO_L9N_CC_16
IO_L10P_CC_16
IO_L10N_CC_16
IO_L11P_CC_16
IO_L11N_CC_16
IO_L13P_16
IO_L13N_16
IO_L14P_16
IO_L14N_VREF_16
IO_L15P_16
IO_L15N_16
IO_L16P_16
IO_L16N_16
IO_L17P_16
IO_L17N_16
IO_L18P_16
IO_L18N_16
IO_L12P_VRN_16
IO_L19P_16
IO_L12N_VRP_16
IO_L19N_16
BANK 16
D7
G8
C10
DVCC25
C
DVCC25
R78
49.9 1%
OPT
B6
A5
R81
49.9 1%
OPT
H7
G7
F7
F8
F9
G9
H8
J8
A9
A8
E8
E7
B9
C8
E6
D6
C9
D8
C7
C6
A7
B7
D9
D10
B10
A10
A4
A3
B11
A12
B4
B5
B12
C12
D5
E5
C11
D11
AA6
AD7
AC10
LPC_P23
LPC_N23
LPC_P25
LPC_N25
LPC_N27
LPC_P27
LPC_N29
LPC_P29
LPC_N31
LPC_P31
LPC_N33
LPC_P33
HPC_N3
HPC_P3
HPC_P5
HPC_N5
HPC_P7
HPC_N7
HPC_N9
HPC_P9
HPC_N11
HPC_P11
HPC_P13
HPC_N13
HPC_N15
HPC_P15
HPC_N19
HPC_P19
HPC_P21
HPC_N21
HPC_P23
HPC_N23
HPC_P25
HPC_N25
DVCC25
R79
49.9 1%
OPT
AC6
AD5
HPC_N27
HPC_P27
HPC_N29
HPC_P29
R82
49.9 1%
OPT
XC5VLX30T
U1-12
DVCC25
VCCO_180
VCCO_181
VCCO_182
IO_L0P_18
IO_L0N_18
IO_L1P_18
IO_L1N_18
IO_L2P_18
IO_L2N_18
IO_L3P_18
IO_L3N_18
IO_L4P_18
IO_L4N_VREF_18
IO_L5P_18
IO_L5N_18
IO_L6P_18
IO_L6N_18
IO_L7P_18
IO_L7N_18
IO_L8P_CC_18
IO_L8N_CC_18
IO_L9P_CC_18
IO_L9N_CC_18
IO_L10P_CC_18
IO_L10N_CC_18
IO_L11P_CC_18
IO_L11N_CC_18
IO_L13P_18
IO_L13N_18
IO_L14P_18
IO_L14N_VREF_18
IO_L15P_18
IO_L15N_18
IO_L16P_18
IO_L16N_18
IO_L17P_18
IO_L17N_18
IO_L18P_18
IO_L18N_18
IO_L12P_VRN_18
IO_L19P_18
IO_L12N_VRP_18
IO_L19N_18
BANK 18
DVCC25
U1-18
AF12
AE12
V8
V9
AE11
AD11
W9
W8
AD10
AE10
Y7
Y8
AF9
AF10
AA7
AA8
AF7
AF8
AA5
AB5
AB6
AB7
AE8
AE7
AE6
AF5
AE5
AD4
AF4
AF3
AD6
AC7
AC8
AD8
AD9
AC9
AB9
AA9
H5
L6
P7
LPC_P24
LPC_N24
LPC_N26
LPC_P26
LPC_P28
LPC_N28
LPC_P30
LPC_N30
LPC_N32
LPC_P32
HPC_P2
HPC_N2
HPC_N4
HPC_P4
VCCO_120
VCCO_121
VCCO_122
IO_L0P_12
IO_L0N_12
IO_L1P_12
IO_L1N_12
IO_L2P_12
IO_L2N_12
IO_L3P_12
IO_L3N_12
IO_L4P_12
IO_L4N_VREF_12
IO_L5P_12
IO_L5N_12
IO_L6P_12
IO_L6N_12
IO_L7P_12
IO_L7N_12
IO_L8P_CC_12
IO_L8N_CC_12
IO_L9P_CC_12
IO_L9N_CC_12
IO_L10P_CC_12
IO_L10N_CC_12
IO_L11P_CC_12
IO_L11N_CC_12
IO_L13P_12
IO_L13N_12
IO_L14P_12
IO_L14N_VREF_12
IO_L15P_12
IO_L15N_12
IO_L16P_12
IO_L16N_12
IO_L17P_12
IO_L17N_12
IO_L18P_12
IO_L18N_12
IO_L12P_VRN_12
IO_L19P_12
IO_L12N_VRP_12
IO_L19N_12
BANK 12
U1-16
HPC_P6
HPC_N6
HPC_N8
HPC_P8
HPC_N10
HPC_P10
HPC_N12
HPC_P12
HPC_P14
HPC_N14
HPC_N16
HPC_P16
HPC_P18
HPC_N18
HPC_P20
HPC_N20
HPC_P22
HPC_N22
HPC_P26
HPC_N26
DVCC25
R80
49.9 1%
OPT
K8
L7
HPC_N28
HPC_P28
HPC_P30
HPC_N30
Y6
Y5
G6
H6
Y4
W4
G5
F5
W5
W6
G4
H4
V6
V7
J5
J6
U7
T8
K5
L5
K6
K7
U6
U5
T5
R5
M7
L8
R6
T7
P6
N6
M6
N7
N8
P8
R8
R7
LPC_P2
LPC_N2
LPC_N3
LPC_P3
LPC_P4
LPC_N4
LPC_P5
LPC_N5
LPC_P6
LPC_N6
LPC_N7
LPC_P7
LPC_P8
LPC_N8
LPC_P9
LPC_N9
LPC_P10
LPC_N10
LPC_N11
LPC_P11
C
LPC_P12
LPC_N12
LPC_P13
LPC_N13
LPC_P14
LPC_N14
LPC_P15
LPC_N15
LPC_N16
LPC_P16
LPC_P19
LPC_N19
LPC_N20
LPC_P20
LPC_N21
LPC_P21
LPC_N22
LPC_P22
R83
49.9 1% XC5VLX30T
OPT
XC5VLX30T
B
B
DGND
DGND
DVCC25
DGND
DVCC25
DVCC25
C135
C138
C139
C140
C141
C142
C143
C144
C145
C146
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DGND
DGND
LPC_P[33:0]
LPC_N[33:0]
HPC_P[45:0]
HPC_N[45:0]
A
LPC_P[33:0]
8,12
LPC_N[33:0]
8,12
HPC_P[45:0]
8,10,12
HPC_N[45:0]
8,10,12
DGND
CUSTOMER NOTICE
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
5
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
DATE:
2
IC NO.
REV
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
1
9
OF 16
A
5
4
3
2
U1-15
DVCC25
1
U1-10
D
D
IO_L0P_15
IO_L0N_15
IO_L1P_15
IO_L1N_15
IO_L2P_15
IO_L2N_15
IO_L3P_15
IO_L3N_15
IO_L4P_15
IO_L4N_VREF_15
IO_L5P_15
IO_L5N_15
IO_L6P_15
IO_L6N_15
IO_L7P_15
IO_L7N_15
IO_L8P_CC_15
IO_L8N_CC_15
IO_L9P_CC_15
IO_L9N_CC_15
IO_L10P_CC_15
IO_L10N_CC_15
IO_L11P_CC_15
IO_L11N_CC_15
IO_L13P_15
IO_L13N_15
IO_L14P_15
IO_L14N_VREF_15
IO_L15P_15
IO_L15N_15
IO_L16P_15
IO_L16N_15
IO_L17P_15
IO_L17N_15
IO_L18P_15
IO_L18N_15
IO_L12P_VRN_15
IO_L19P_15
IO_L12N_VRP_15
IO_L19N_15
C
DVCC25
R86
49.9 1%
OPT
D23
C22
R87
49.9 1%
OPT
C13
C14
B14
A13
A14
A15
B15
C16
B16
C17
B17
A17
A18
A19
B19
C18
A20
B20
C19
D19
D21
D20
B21
C21
B22
A22
A23
A24
B24
C23
D24
C24
B25
A25
B26
C26
D26
D25
HPC_P31
HPC_N31
HPC_N33
HPC_P33
HPC_P35
HPC_N35
HPC_P37
HPC_N37
HPC_P39
HPC_N39
HPC_P41
HPC_N41
HPC_P42
HPC_N42
BANK 17B
VCCO_150
VCCO_151
VCCO_152
BANK 15
F21
B23
E24
HPC_N45
HPC_P45
CLK_112_SEL
CLK_112_ON
CLK_116_SEL
CLK_116_ON
CLK_114_SEL
CLK_114_ON
CLK_IODLY_ON
USERIO0
USERIO1
USERIO2
USERIO3
USERIO4
USERIO5
USERIO6
USERIO7
USERIO8
USERIO9
USERIO10
USERIO11
DPB2
DPB3
DPB4
CLK_112_SEL 6
CLK_112_ON 6
CLK_116_SEL 6
CLK_116_ON 6
CLK_114_SEL 6
CLK_114_ON 6
CLK_IODLY_ON 6
IO_L9N_CC_17
IO_L10P_CC_17
IO_L10N_CC_17
IO_L11P_CC_17
IO_L11N_CC_17
IO_L13P_17
IO_L13N_17
IO_L14P_17
IO_L14N_VREF_17
IO_L15P_17
IO_L15N_17
IO_L16P_17
IO_L16N_17
IO_L17P_17
IO_L17N_17
IO_L18P_17
IO_L18N_17
IO_L19P_17
IO_L19N_17
DGND
DVCC25
C150
C151
HPC_P[45:0]
0.1uF
0.1uF
0.1uF
HPC_N[45:0]
USERIO[24:0]
DPA[4:1]
DGND
DPB[4:1]
HPC_N34
HPC_P34
HPC_P36
HPC_N36
HPC_N38
HPC_P38
HPC_P40
HPC_N40
HPC_P43
HPC_N43
HPC_P44
HPC_N44
J7
DVCC25
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
USERIO1
USERIO3
USERIO5
USERIO7
USERIO9
USERIO11
CLK_112_SEL 6
CLK_112_ON 6
CLK_114_SEL 6
CLK_114_ON 6
CLK_116_SEL 6
CLK_116_ON 6
CLK_118_SEL 6
CLK_118_ON 6
CLK_IODLY_ON 6
DVCC33
USERIO17
USERIO19
USERIO21
USERIO23
DGND
C149
CLK_118_SEL 6
CLK_118_ON 6
C
USERIO13
USERIO15
B
DPA2
DPA3
DPA4
CLK_118_SEL
CLK_118_ON
HPC_P32
HPC_N32
XC5VLX30T
XC5VLX30T
CLK_112_SEL
CLK_112_ON
CLK_114_SEL
CLK_114_ON
CLK_116_SEL
CLK_116_ON
CLK_118_SEL
CLK_118_ON
CLK_IODLY_ON
AE20
AD19
AD20
AC21
AD21
AE18
AD18
AE17
AF17
AE16
AD16
AD15
AE15
AF15
AF14
AF13
AE13
AD13
AD14
HPC_P[45:0]
8,9,12
HPC_N[45:0]
8,9,12
USERIO[24:0]
1,3,8
DPA[4:1]
4
DPB[4:1]
4
CUSTOMER NOTICE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
HEADER 20X2
USERIO0
USERIO2
USERIO4
USERIO6
USERIO8
USERIO10
USERIO12
USERIO14
USERIO16
USERIO18
USERIO20
B
USERIO22
USERIO24
DGND
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
5
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
DATE:
2
IC NO.
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
REV
1
10 OF 16
A
5
4
AVCC25
3
2
1
DVCC10
DVCC10
C
GND127
GND126
GND125
GND124
GND123
GND122
GND121
GND120
GND119
GND118
GND117
GND116
GND115
GND114
GND113
GND112
GND111
GND110
GND109
GND108
GND107
GND106
GND105
GND104
GND103
GND102
GND101
GND100
GND99
GND98
GND97
GND96
GND95
GND94
GND93
GND92
GND91
GND90
GND89
GND88
GND87
GND86
L10
N10
R10
U10
M11
P11
T11
L12
N12
R12
K13
M13
P13
T13
J14
L14
U14
H15
K15
T15
V15
J16
L16
N16
R16
U16
H17
K17
M17
P17
T17
V17
J18
L18
N18
R18
U18
W18
K19
POWER
GN0
GN1
GN2
GN3
GN4
GN5
GN6
GN7
GN8
GN9
GN10
GN11
GN12
GN13
GN14
GN15
GN16
GN17
GN18
GN19
GN20
GN21
GN22
GN23
GN24
GN25
GN26
GN27
GN28
GN29
GN30
GN31
GN32
GN33
GN34
GN35
GN36
GN37
GN38
GN39
GN40
GN41
GN42
A2
D2
E2
K2
L2
T2
U2
AB2
AC2
AF2
C4
F4
J4
M4
R4
V4
AA4
AE4
C5
N5
V5
AC5
A6
F6
T6
AF6
J7
W7
B8
M8
AB8
E9
L9
N9
R9
U9
Y9
AE9
H10
K10
M10
P10
T10
C156
C157
C158
C159
C160
C161
C162
C163
C164
C165
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C166
C167
C168
C169
C170
C171
C172
C173
C174
C175
C176
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DVCC10
DGND
C
DVCC10
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186
C187
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C188
C189
C190
C191
C192
C193
C194
C195
C196
C197
C198
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DGND
DVCC10
B
DGND
AVCC25
L17
J17
AF16
V16
T16
P16
M16
K16
H16
F16
A16
AC15
W15
U15
L15
J15
C15
Y14
V14
T14
K14
H14
U13
R13
N13
L13
J13
G13
AD12
W12
T12
P12
M12
K12
D12
AF11
AA11
U11
R11
N11
L11
A11
V10
XC5VLX30T
C155
DGND
GND85
GND84
GND83
GND82
GND81
GND80
GND79
GND78
GND77
GND76
GND75
GND74
GND73
GND72
GND71
GND70
GND69
GND68
GND67
GND66
GND65
GND64
GND63
GND62
GND61
GND60
GND59
GND58
GND57
GND56
GND55
GND54
GND53
GND52
GND51
GND50
GND49
GND48
GND47
GND46
GND45
GND44
GND43
B
AF26
AA26
T26
L26
F26
A26
AC25
N25
C25
Y24
K24
U23
G23
AD22
P22
D22
AF21
AA21
T21
L21
A21
V20
H20
C20
AE19
W19
U19
R19
N19
L19
E19
AB18
V18
T18
P18
M18
K18
B18
W17
U17
R17
N17
D
VCCINT0
VCCINT1
VCCINT2
VCCINT3
VCCINT4
VCCINT5
VCCINT6
VCCINT7
VCCINT8
VCCINT9
VCCINT10
VCCINT11
VCCINT12
VCCINT13
VCCINT14
VCCINT15
VCCINT16
VCCINT17
VCCINT18
VCCINT19
VCCINT20
VCCINT21
VCCINT22
VCCINT23
VCCINT24
VCCINT25
VCCINT26
VCCINT27
VCCINT28
VCCINT29
VCCINT30
VCCINT31
VCCINT32
VCCINT33
VCCINT34
VCCINT35
VCCINT36
VCCINT37
VCCINT38
U1-6
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
U8
K9
M9
P9
T9
W10
M19
P19
T19
V19
Y19
N20
D
DGND
C199
C201
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
C212
C200
10uF/10V
0805XS
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF/10V
0805XS
DGND
CUSTOMER NOTICE
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
ALL CAPACITORS ARE 0402
5
4
3
DATE:
2
IC NO.
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
REV
1
11 OF 16
A
5
4
3
2
1
LOW PIN COUNT
J8H
PRSNT_FMC
PG_C2M_FMC
PG_M2C_FMC_B
TCK
TMS
TRST_B
TDI
TDO_FMC
SCL
SDA
D
J8G
PRSNT_FMC
1
PG_C2M_FMC 1
PG_M2C_FMC_B 1
TCK
3,4
TMS
3,4
TRST_B
3,4
TDI
3
TDO_FMC
3
SCL
1
SDA
1
CLK0_C2M_P
CLK0_C2M_N
CLK1_C2M_P
CLK1_C2M_N
CLK0_C2M_P
CLK0_C2M_N
CLK1_C2M_P
CLK1_C2M_N
LPC_CC_P0
LPC_CC_N0
LPC_CC_P1
LPC_CC_N1
LPC_CC_P17
LPC_CC_N17
LPC_CC_P18
LPC_CC_N18
HPC_CC_P0
HPC_CC_N0
HPC_CC_P1
HPC_CC_N1
HPC_CC_P17
HPC_CC_N17
HPC_CC_P24
HPC_CC_N24
HPC_CC_P30
HPC_CC_N30
HPC_CC_P41
HPC_CC_N41
CLK_112_EXTIN_P
CLK_112_EXTIN_N
CLK_114_EXTIN_P
CLK_114_EXTIN_N
CLK_116_EXTIN_P
CLK_116_EXTIN_N
CLK_118_EXTIN_P
CLK_118_EXTIN_N
8
8
8
8
LPC_CC_P0
8
LPC_CC_N0
8
LPC_CC_P1
8
LPC_CC_N1
8
LPC_CC_P17 8
LPC_CC_N17 8
LPC_CC_P18 8
LPC_CC_N18 8
HPC_CC_P0
8
HPC_CC_N0
8
HPC_CC_P1
8
HPC_CC_N1
8
HPC_CC_P17 8
HPC_CC_N17 8
HPC_CC_P24 8
HPC_CC_N24 8
HPC_CC_P30 9
HPC_CC_N30 9
HPC_CC_P41 10
HPC_CC_N41 10
CLK_112_EXTIN_P
CLK_112_EXTIN_N
CLK_114_EXTIN_P
CLK_114_EXTIN_N
CLK_116_EXTIN_P
CLK_116_EXTIN_N
CLK_118_EXTIN_P
CLK_118_EXTIN_N
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
VREF_A_M2C
PRSNT_M2C_N
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
6
6
6
6
6
6
6
6
J8D
GND
CLK0_C2M_P
CLK0_C2M_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
PRSNT_M2C
CLK_112_EXTIN_P
CLK_112_EXTIN_N
LPC_P24
LPC_N24
LPC_P28
LPC_N28
LPC_P8
LPC_N8
LPC_P26
LPC_N26
LPC_P21
LPC_N21
LPC_P20
LPC_N20
LPC_P29
LPC_N29
LPC_P27
LPC_N27
LPC_P9
LPC_N9
LPC_P5
LPC_N5
LPC_P31
LPC_N31
DVCCFMC
SEAF-40-06.5-10-A
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
SEAF-40-06.5-10-A
DGND
CLK0_C2M_P
CLK0_C2M_N
LPC_CC_P0
LPC_CC_N0
J8C
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_N
GA1
3P3V
GND
3P3V
GND
3P3V
LPC_P0
LPC_N0
LPC_P32
LPC_N32
LPC_P6
LPC_N6
LPC_P14
LPC_N14
LPC_P16
LPC_N16
LPC_P19
LPC_N19
LPC_P11
LPC_N11
LPC_P3
LPC_N3
LPC_P33
LPC_N33
LPC_P7
LPC_N7
LPC_P25
LPC_N25
DVCCFMC
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
CLK_118_EXTIN_P
CLK_118_EXTIN_N
LPC_CC_P1
LPC_CC_N1
LPC_P1
LPC_N1
LPC_P4
LPC_N4
LPC_P10
LPC_N10
LPC_P13
LPC_N13
LPC_CC_P18
LPC_CC_N18
LPC_P18
LPC_N18
LPC_P15
LPC_N15
LPC_P23
LPC_N23
TCK_C2M
TDI_C2M
TDO_M2C
TMS_C2M
TRST_N_C2M
DVCCFMC
DVCCFMC
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
MGTTXP0_112
MGTTXN0_112
MGTTXP1_112
MGTTXN1_112
MGTRXP0_112
MGTRXN0_112
MGTRXP1_112
MGTRXN1_112
MGTTXP0_114
MGTTXN0_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTRXP1_114
MGTRXN1_114
MGTTXP0_116
MGTTXN0_116
MGTTXP1_116
MGTTXN1_116
MGTRXP0_116
MGTRXN0_116
MGTRXP1_116
MGTRXN1_116
MGTTXP1_118
MGTTXN1_118
MGTTXP0_118
MGTTXN0_118
MGTRXP1_118
MGTRXN1_118
MGTRXP0_118
MGTRXN0_118
MGTTXP1_118
MGTTXN1_118
MGTRXP0_118
MGTRXN0_118
LPC_P2
LPC_N2
LPC_P30
LPC_N30
LPC_P22
LPC_N22
LPC_CC_P17
LPC_CC_N17
LPC_P17
LPC_N17
LPC_P12
LPC_N12
SCL
SDA
DVCC33
R176
R177
10K
10K
OPT
OPT
LPC_P[33:0]
LPC_N[33:0]
HPC_P[45:0]
DVCCFMC
HPC_N[45:0]
MGTTXP0_112
MGTTXN0_112
MGTTXP1_112
MGTTXN1_112
MGTRXP0_112
MGTRXN0_112
MGTRXP1_112
MGTRXN1_112
MGTTXP0_114
MGTTXN0_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTRXP1_114
MGTRXN1_114
MGTTXP0_116
MGTTXN0_116
MGTTXP1_116
MGTTXN1_116
MGTRXP0_116
MGTRXN0_116
MGTRXP1_116
MGTRXN1_116
MGTTXP1_118
MGTTXN1_118
MGTTXP0_118
MGTTXN0_118
MGTRXP1_118
MGTRXN1_118
MGTRXP0_118
MGTRXN0_118
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
D
LPC_P[33:0]
8,9
LPC_N[33:0]
8,9
HPC_P[45:0]
8,9,10
HPC_N[45:0]
8,9,10
SEAF-40-06.5-10-A
SEAF-40-06.5-10-A
DGND
PG_C2M
DGND
DGND
C
C
J8K
VREF_B_M2C
GND
GND
CLK1_M2C_P
CLK1_M2C_N
GND
HA02_P
HA02_N
GND
HA06_P
HA06_N
GND
HA10_P
HA10_N
GND
HA17_P_CC
HA17_N_CC
GND
HA21_P
HA21_N
GND
HA23_P
HA23_N
GND
HB00_P_CC
HB00_N_CC
GND
HB06_P_CC
HB06_N_CC
GND
HB10_P
HB10_N
GND
HB14_P
HB14_N
GND
HB17_P_CC
HB17_N_CC
GND
VIO_B_M2C
GND
CLK1_C2M_P
CLK1_C2M_N
GND
GND
HA03_P
HA03_N
GND
HA07_P
HA07_N
GND
HA11_P
HA11_N
GND
HA14_P
HA14_N
GND
HA18_P
HA18_N
GND
HA22_P
HA22_N
GND
HB01_P
HB01_N
GND
PB07_P
HB07_N
GND
HB11_P
HB11_N
GND
HB15_P
HB15_N
GND
HB18_P
HB18_N
GND
VIO_B_M2C
GND
CLK_114_EXTIN_P
CLK_114_EXTIN_N
HPC_P34
HPC_N34
HPC_P43
HPC_N43
HPC_P26
HPC_N26
HPC_CC_P30
HPC_CC_N30
HPC_P30
HPC_N30
HPC_P22
HPC_N22
HPC_P13
HPC_N13
HPC_CC_P0
HPC_CC_N0
HPC_P0
HPC_N0
HPC_CC_P17
HPC_CC_N17
HPC_P17
HPC_N17
HPC_P29
HPC_N29
HPC_P31
HPC_N31
HPC_CC_P41
HPC_CC_N41
HPC_P41
HPC_N41
VIO_B_M2C
SEAF-40-06.5-10-A
SEAF-40-06.5-10-A
DGND
J8F
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
CLK1_C2M_P
CLK1_C2M_N
HPC_P32
HPC_N32
HPC_P40
HPC_N40
HPC_P28
HPC_N28
HPC_P8
HPC_N8
HPC_P16
HPC_N16
HPC_P12
HPC_N12
HPC_P3
HPC_N3
HPC_P15
HPC_N15
HPC_P25
HPC_N25
HPC_P35
HPC_N35
HPC_P39
HPC_N39
VIO_B_M2C
DGND
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
PG_M2C
HPC_CC_P1
HPC_CC_N1
GND
HA01_P_CC
HA01_N_CC
GND
GND
HA05_P
HA05_N
GND
HA09_P
HA09_N
GND
HA13_P
HA13_N
GND
HA16_P
HA16_N
GND
HA20_P
HA20_N
GND
HB03_P
HB03_N
GND
HB05_P
HB05_N
GND
HB09_P
HB09_N
GND
HB13_P
HB13_N
GND
HB21_P
HB21_N
GND
HB20_P
HB20_N
GND
VADJ
GND
HPC_P1
HPC_N1
HPC_P38
HPC_N38
HPC_P10
HPC_N10
HPC_P6
HPC_N6
HPC_P20
HPC_N20
HPC_P2
HPC_N2
HPC_P27
HPC_N27
HPC_P11
HPC_N11
HPC_P21
HPC_N21
HPC_P33
HPC_N33
HPC_P37
HPC_N37
HPC_P42
HPC_N42
DVCCFMC
SEAF-40-06.5-10-A
DVCC33
VIO_B_M2C
DVCC33
VIO_B_M2C
DVCC33
VIO_B_M2C
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
SEAF-40-06.5-10-A
DGND
DVCC33
J8B
J8E
PG_M2C
GND
GND
HA00_P_CC
HA00_N_CC
GND
HA04_P
HA04_N
GND
HA08_P
HA08_N
GND
HA12_P
HA12_N
GND
HA15_P
HA15_N
GND
HA19_P
HA19_N
GND
HB02_P
HB02_N
GND
HB04_P
HB04_N
GND
HB08_P
HB08_N
GND
HB12_P
HB12_N
GND
HB16_P
HB16_N
GND
HB19_P
HB19_N
GND
VADJ
DVCC33
VIO_B_M2C
HPC_CC_P24
HPC_CC_N24
HPC_P44
HPC_N44
HPC_P4
HPC_N4
HPC_P14
HPC_N14
HPC_P18
HPC_N18
HPC_P5
HPC_N5
HPC_P7
HPC_N7
HPC_P19
HPC_N19
HPC_P23
HPC_N23
HPC_P9
HPC_N9
HPC_P45
HPC_N45
DVCCFMC
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
DVCC33
DVCC33
GND
DP1_M2C_P
DP1_M2C_N
GND
GND
DP2_M2C_P
DP2_M2C_N
GND
GND
DP3_M2C_P
DP3_M2C_N
GND
GND
DP4_M2C_P
DP4_M2C_N
GND
GND
DP5_M2C_P
DP5_M2C_N
GND
GND
DP1_C2M_P
DP1_C2M_N
GND
GND
DP2_C2M_P
DP2_C2M_N
GND
GND
DP3_C2M_P
DP3_C2M_N
GND
GND
DP4_C2M_P
DP4_C2M_N
GND
GND
DP5_C2M_P
DP5_C2M_N
GND
MGTRXP1_114
MGTRXN1_114
MGTRXP1_112
MGTRXN1_112
MGTRXP1_116
MGTRXN1_116
CLK_116_EXTIN_P
CLK_116_EXTIN_N
MGTTXP1_112
MGTTXN1_112
MGTTXP1_116
MGTTXN1_116
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
MGTRXP1_118
MGTRXN1_118
MGTRXP0_114
MGTRXN0_114
MGTRXP0_112
MGTRXN0_112
MGTRXP0_116
MGTRXN0_116
MGTTXP0_118
MGTTXN0_118
MGTTXP1_114
MGTTXN1_114
MGTTXP0_114
MGTTXN0_114
B
MGTTXP0_112
MGTTXN0_112
MGTTXP0_116
MGTTXN0_116
SEAF-40-06.5-10-A
SEAF-40-06.5-10-A
DGND
DVCC33
J8A
RES1
GND
GND
DP9_M2C_P
DP9_M2C_N
GND
GND
DP8_M2C_P
DP8_M2C_N
GND
GND
DP7_M2C_P
DP7_M2C_N
GND
GND
DP6_M2C_P
DP6_M2C_N
GND
GND
GBTCLK1_M2C_P
GBTCLK1_M2C_N
GND
GND
DP9_C2M_P
DP9_C2M_N
GND
GND
DP8_C2M_P
DP8_C2M_N
GND
GND
DP7_C2M_P
DP7_C2M_N
GND
GND
DP6_C2M_P
DP6_C2M_N
GND
GND
RES0
HPC_P24
HPC_N24
HPC_P36
HPC_N36
DGND
DGND
VIO_B_M2C
DVCC33
DVCC33
DVCC33
R88
R89
R90
R91
R92
R93
R94
R95
R96
R99
R97
R100
R98
R101
R173
R103
10K
10K
10K
330
330
330
330
330
330
330
330
10K
10K
10K
10K
10K
DGND
DGND
DGND
1
Q14
DGND
DGND
DGND
Q15
DGND
PG_M2C
1
3
PRSNT_M2C
Q16
PDTC144EU
DGND
PRSNT_FMC
3
PDTC144EU
3
PG_C2M_FMC 1
Si1300BDL
PG_M2C_FMC_B
Q9
2
TDO_M2C
Si1300BDL
3
3
Si1300BDL
1
Q17
PDTC144EU
2
Q13
1
Q8
3
Si1300BDL
3
1
1
Q7
DGND
PDTC144EU
2
DGND
TDI
PG_C2M
2
DGND
Q12
Si1300BDL
2
DGND
3
3
3
1
TMS
Si1300BDL
TDO_FMC
2
Q11
Si1300BDL
2
1
1
Q6
2
TCK
PDTC144EU
2
Si1300BDL
2
Q10
TDI_C2M
2
2
1
1
Q5
3
PDTC144EU
3
TRST_B
1
Q4
2
1
TMS_C2M
3
TCK_C2M
3
TRST_N_C2M
2
B
HIGH PIN COUNT
J8J
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K40
DGND
DGND
A
A
CUSTOMER NOTICE
C279
C281
CHASSIS_GND
0.1uF
0.1uF
C280
C282
DGND
CHASSIS_GND
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
TITLE:
SCHEMATIC
GARY YU
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
0.1uF
0.1uF
SIZE
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0402
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
DGND
NOTES: UNLESS OTHERWISE SPECIFIED
5
CONTRACT NO.
3
2
B
DATE:
IC NO.
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
REV
1
12 OF 16
5
C217
10uF/10V
0805XS
U20
E8
C1
C8
C9
D1
D3
D4
D5
D7
D8
D9
C218
0.1uF
D
DGND
F4
E5
TP17
DVCC50
F1
RUN33V
OPT
10K
10K
0
0.01uF
R104
R110
R113
C227
B5
B4
E3
E1
DGND
A1
G5
G4
G3
G2
G1
F8
F7
F3
B11
A9
A8
A7
A6
A5
A2
A3
C
LTM4608EV
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
SVIN
TRACK
RUN
MODE
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
MGN
BSEL
PGOOD
PHMODE
PLLLPF
SGND
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
FB
CLKIN
CLKOUT
SW0
SW1
SW2
ITH
TIHM
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
DGND
G11
C10
C11
D10
D11
E9
E10
E11
F9
F10
F11
G9
G10
B
DGND
C7
R125
R123
R124
R126
8.45K 1%
12.1K 1%
36.5K 1%
51.1K 1%
R130
R131
R132
R133
10K 1%
10K 1%
10K 1%
10K 1%
22
23
1
DGND
R161
R162
3
38
32
30
25
10
11
0
0
DGND
12
13
14
DVCC50
DVCC50
C220
0.1uF
C214
100uF
1210
DGND
U21
C221
10uF/10V
0805XS
F4
E5
TP18
DVCC50
OK33V
C247
C249
B3
F2
R105
100pF
R114
22pF
10K
2.21K 1%
R106
R111
R115
C228
DVCC50
DVCC33
DGND
R163
R137
R138
R140
95.3K 1%
15K 1%
42.2K 1%
24.3K 1%
R164
10K
C287
1uF
A
6
7
8
9
POWER_ON 16
17
REF
EN1
EN2
EN3
EN4
RTMR
PTMR
STMR
VSEL
RDIS
RT1
RT2
RT3
RT4
ON
NC
B4
E3
LTM4608EV
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
SVIN
TRACK
CPM1
CPM2
CPM3
CPM4
RST
OV
FLT
DONE
CAS
GND
PAD
MODE
PHMODE
PLLLPF
SGND
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
PGOOD
FB
CLKIN
CLKOUT
SW0
SW1
SW2
ITH
TIHM
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
C215 DVCC25
100uF
FB28
1210
BLM31PG121SN1L
G11
C10
C11
D10
D11
E9
E10
E11
F9
F10
F11
G9
G10
AVCC25
C223
0.1uF
C252
0.1uF
C251
100uF
1210
DGND
1
DVCC50
U22
C224
10uF/10V
0805XS
E8
C1
C8
C9
D1
D3
D4
D5
D7
D8
D9
C225
0.1uF
DGND
TP12
TP15
F4
E5
B8
B7
TP19
DVCC50
C7
OK25V
C248
R107
100pF
R116
22pF
E7
C250
B3
F2
10K
3.09K 1%
R108
R112
R117
C229
DVCC50
DVCC25
RUN10V
OPT
10K
10K
0
0.01uF
F1
B5
B4
E3
E1
CLKOUT33V
CLKOUT25V
DGND
DGND
A1
G5
G4
G3
G2
G1
F8
F7
F3
B11
A9
A8
A7
A6
A5
A2
A3
C5
C4
C3
F6
F5
A4
A10
A11
B1
B9
B10
G6
G7
G8
DGND
DVCC50
LTM4608EV
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
SVIN
TRACK
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
MGN
BSEL
RUN
MODE
PGOOD
PHMODE
PLLLPF
SGND
FB
CLKIN
CLKOUT
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
SW0
SW1
SW2
ITH
TIHM
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
DVCC10
G11
C10
C11
D10
D11
E9
E10
E11
F9
F10
F11
G9
G10
C216
100uF
1210
C246
100uF
1210
C226
0.1uF
D
DGND
TP13
TP16
B8
B7
C7
OK10V R109
E7
R118
B3
F2
10K
DVCC50
14.7K 1%
CLKOUT25V
DGND
C5
C4
C3
F6
F5
C
A4
A10
A11
B1
B9
B10
G6
G7
G8
DGND
DGND
DC 5.0V 2A
DVCC50
5
2
37
31
29
RUN10V
RUNMGTV
RUN25V
RUN33V
C230
1uF
C231
R122
287
0805XS LED5
0.1uF
1
28
27
26
C241
C242
C243
0.047uF
0.1uF
3300pF
35
36
33
34
GREEN
21
POWER_RESET R134
10K
20
19
POWER_FAULT
R135
10K
18
POWER_DONE
R139
10K
DGND
POWER_RESET
POWER_DONE
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0603
LED6
1
C244
C245 0805XS
100uF
1210
0.1uF
B
2
GREEN
DGND
POWER_DONE
Q20 OPT
PDTC144EU
DGND
RUNMGTV
14
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
POWER_RESET 1
POWER_DONE 1
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
R136
287
0
CUSTOMER NOTICE
24
39
RUNMGTV
DVCC50
DGND
15
NOTES: UNLESS OTHERWISE SPECIFIED
R178
1
DVCC50
J9
POWER JACK
1
3
2
POWER GOOD
2
DGND
DGND
DGND
5
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
MGN
BSEL
RUN
DGND
U23
LTC2928
MS1
MS2
B5
A1
G5
G4
G3
G2
G1
F8
F7
F3
B11
A9
A8
A7
A6
A5
A2
A3
A4
A10
A11
B1
B9
B10
G6
G7
G8
SQT1
SQT2
F1
DGND
F6
F5
V1
V2
V3
V4
RUN25V
OPT
10K
10K
0
0.01uF
E1
TP2
CLKOUT33V
C5
C4
C3
OVA
C222
0.1uF
TP11
TP14
E7
VCC
HVCC
E8
C1
C8
C9
D1
D3
D4
D5
D7
D8
D9
DGND
DGND
DGND
DVCC50
C219
0.1uF
B8
B7
DVCC50
DVCC10
DVCC12
DVCC25
DVCC33
C213 DVCC33
DVCCFMC
100uF
FB27
1210
BLM31PG121SN1L
2
3
TP10
3
2
DVCC50
4
3
DATE:
2
IC NO.
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
REV
1
13 OF 16
A
5
4
3
DVCC12
TP20
C259
C260
C261
10uF/10V
0805XS
10uF/10V
0805XS
0.1uF
DGND
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
VIN16
VIN17
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
VOUT16
VOUT17
VOUT18
VOUT19
D
DVCC50
TP21
B9
A10
RUNMGTV
A11
D11
C10
E11
E12
A7
A8
TP3
C267
C268
10uF/10V
0805XS
C7
B7
0.01uF
A9
D9
H12
DGND
H11
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G11
G10
G9
AVPLL12
COMP1
COMP2
DRVCC0
DRVCC1
DRVCC2
VOUT20
VOUT21
VOUT22
VOUT23
VOUT24
VOUT25
VOUT26
VOUT27
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VOUT33
VOUT34
VOUT35
VOUT36
VOUT37
VOUT38
VOUT39
VOUT40
VOUT41
VOUT42
VOUT43
VFB
MPGM0
MPGM1
INTVCC
MARG00
MARG10
MARG11
PLLIN
VD0
VD1
FCB
TRACK/SS
FSET
SGND0
SGND1
GND44
GND43
GND42
GND41
GND40
GND39
GND38
GND37
GND36
GND35
GND34
GND33
GND32
GND31
PGOOD
NC2
NC1
NC0
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
F12
C255
C256
C257
100uF
1210
100uF
1210
0.1uF
330uF/10V
7343
+ C254
D
C258
330uF/10V
7343
0.1uF
DGND
AVTT12
U27
1
2
C263
6
TP22
TP23
C262
R141
R142
100pF
60.4K 1%
392K
C12
C11
D12
R144
R146
0
0
M12
R148
0
B12
C269
1000pF
G12
OKMGTV
B11
A12
+ C253
L2
10uF/10V
0805XS
10uH
4
5
C266 10uF/10V 3
0805XS
11
DVCC12
DGND
DGND
AVCC10
LTC3026
IN0
IN1
OUT0
OUT1
10
9
R143
SHDN
8
ADJ
SW
BST
PG
7
C264
C265
10uF/10V
0805XS
0.1uF
C
6.04K 1%
R145
4.02K 1%
R147
10K
AVTT12
DGND
GND
PAD
DGND
L12
K12
J12
DVCC50
R149
10K
B
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
RUNMGTV
RUNMGTV
13
G8
G7
G6
G5
G4
G3
G2
G1
F9
F8
F7
F6
F5
F4
F3
F2
F1
E8
E7
E6
E5
B
RUN0
RUN1
GND30
GND29
GND28
GND27
GND26
GND25
GND24
GND23
GND22
GND21
GND20
GND19
GND18
GND17
GND16
GND15
GND14
GND13
GND12
GND11
GND10
C
AVTT12
1
LTM4606
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
U28
L1
0.27uH
2
CUSTOMER NOTICE
DGND
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE IN OHMS, 0603.
2. ALL CAPACITORS ARE 0603
5
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
4
3
DATE:
2
IC NO.
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
REV
1
14 OF 16
A
5
4
3
2
1
D
D
U28
U27
K1
U21
U20
U22
J9
A1
Y5
Y3
U16
U11
U23
D1.2
P1
U2
U9
FB2-FB26
Q4-Q17
MEZZANINE CARD MOUNTING
POSITION
56.55
63.0
110.0
C
120.0
C
J8
U5
J1
U1
U3
Y4
U15
U10
Y6
Y2
U7
SW1
SW2
BOTTOM
4.3
J3
U4
J11
D1.2
A1
TOP
B
B
J2
D2.7 4 POS
J4
2.0
D2.7 2 POS
P2
9.5
J7
115.0
54.6
CUSTOMER NOTICE
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
NOTES:
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
UNIT: mm
5
4
3
DATE:
2
IC NO.
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
REV
1
15 OF 16
A
5
4
3
2
1
Revison History
Revison
A:
Initial version
D
D
Revison
A - 1:
1) Added SDCARD for a flash memory option(P2).
2) Removed standby power mode.
3) Moved "MGTRXP/N0_118 to FMC low pin count.
4) Enabled CPU auto detecting USB cable plugging feature.
5) Expanded 4M bits SRAM space.
6) Fixed P1 pin assignment layout error.
7) Tied U1.V10 to ground.
8) Re-assigned HPC32, 34, 36, 38, 40, 43, 44.
9) Re-assigned CLK_118_SEL, CLK_118_ON, CLK_114_SEL, CLK_114_ON, CLK_IODLY_ON.
10) Re-assigned USERIO[23:0]. Two of them has been connected to CPLD.
C
C
11) Removed USERIO[36:24].
12) Added dedicated JTAG interface for CPU.
13) Fixed DCI issues.
14) Fixed FPGA configuration pin issues.
15) Added pullup resistors option for I2C.
16) Swapped CLK_112_EXTIN_P/N and CLK_118_EXTIN_P/N on FMC connector.
Revison
A - 2:
1) Added Two tool mounting holes for J8 installation issue.
2) Added test points TP10-TP23.
3) Removed Test points TP6-TP9. Open solder mask on pin E4, K4 of U2 and E4, K4 of U3 on bottom side for probing.
4) Do not install Q20 and added R178.
B
B
Revison
B - 1:
1) Replace IDT SRAM with ISSI SRAM
CUSTOMER NOTICE
CONTRACT NO.
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
APPROVALS
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
TECHNOLOGY
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. KIM T.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
GARY YU TITLE: SCHEMATIC
ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
A
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
PSTACHE
SIZE
B
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
5
4
3
DATE:
2
IC NO.
DC1371B - HSDAACS
Friday, October 10, 2014
SHEET
1
REV
1
16 OF 16
A
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