DC1763A - Demo Manual

DEMO MANUAL DC1763A
LTC2195, LTC2194, LTC2193,
LTC2192, LTC2191, LTC2190, LTC2271
16-Bit, 20Msps to 125Msps Dual ADCs
Description
Demonstration circuit 1763A supports a family of 16-Bit
20Msps to 125Msps ADCs. Each assembly features one
of the following devices: LTC®2195, LTC2194, LTC2193,
LTC2192, LTC2191, LTC2190, LTC2271 high speed, dual
ADCs.
The versions of the 1763A demo board are listed in Table 1.
Depending on the required resolution and sample rate,
the DC1763A is supplied with the appropriate ADC. The
circuitry on the analog inputs is optimized for analog input
frequencies from 5MHz to 140MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1763A
L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and PScope is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Table 1. DC1763A Variants
DC1763A VARIANTS
ADC PART NUMBER
RESOLUTION
MAXIMUM SAMPLE RATE
INPUT FREQUENCY
1763A-A
LTC2195
16-Bit
125Msps
5MHz to 140MHz
1763A-B
LTC2194
16-Bit
105Msps
5MHz to 140MHz
1763A-C
LTC2193
16-Bit
80Msps
5MHz to 140MHz
1763A-D
LTC2192
16-Bit
65Msps
5MHz to 140MHz
1763A-E
LTC2191
16-Bit
40Msps
5MHz to 140MHz
1763A-F
LTC2190
16-Bit
25Msps
5MHz to 140MHz
1763A-G
LTC2271
16-Bit
20Msps
5MHz to 140MHz
PERFORMANCE SUMMARY
(TA = 25°C)
PARAMETER
CONDITIONS
MIN
TYP
MAX
Supply Voltage – DC1763A
Depending on Sampling Rate and the A/D Converter
Provided, this Supply Must Provide up to 500mA.
3
3.6
6
V
Analog Input Range
Depending on SENSE Pin Voltage
1
2
VP-P
Logic Input Voltages
Minimum Logic High
Maximum Logic Low
1.3
0.6
V
V
Logic Output Voltages (Differential)
Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
350
1.25
247
1.25
mV
V
mV
V
Sampling Frequency (Convert Clock Frequency)
Encode Clock Level
Resolution
Input Frequency Range
UNITS
See Table 1
Single-Ended Encode Mode (ENC– Tied to GND)
Differential Encode Mode (ENC– Not Tied to GND)
0
0.2
3.6
3.6
V
V
See Table 1
See Table 1
SFDR
See Applicable Data Sheet
SNR
See Applicable Data Sheet
dc1763afb
1
DEMO MANUAL DC1763A
quick start procedure
Demonstration circuit 1763A is easy to set up to evaluate
the performance of the LTC2195 A/D converter family. Refer
to Figure 1 for proper measurement equipment setup and
follow the procedure below:
Setup
If a DC1371 PStache Data Acquisition and Collection
System was supplied with the DC1763A demonstration
circuit, follow the DC1371 Quick Start Guide to install the
required software and for connecting the DC1371 to the
DC1763A and to a PC.
DC1763A Demonstration Circuit Board Jumpers
Optional Jumpers:
JP5: ILVDS: Selects either 1.75mA or 3.5mA of output
current for the LVDS drivers. (Default: 3.5mA)
JP15: SHDN: Enables and disables the LTC2195. (Default: SHDN)
JP2: WP: Enable/Disables write protect for the EEPROM.
(Default: EN)
JP14/JP8: LANE/TERM: Two bits that select between
one, two and four lanes.
JP14 – LANE
JP8 TERM
NUMBER OF LANES
2
DIS
2
2
EN
4
1
DIS
1
1
EN
Not Used
The DC1763 demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1)
JP13: PAR/SER : Selects parallel or serial programming
mode. (Default: serial)
(Default: JP8: EN, JP14: 1)
3V TO 6V
TO PROVIDED
POWER SUPPLY
ANALOG INPUTS
TO PROVIDED
USB CABLE
CHANNEL 1
CHANNEL 2
dc1763a F01
PARALLEL/SERIAL
SINGLE-ENDED
ENCODE CLOCK
(USE PROVIDED DC1075,
DIVIDE BY 4-CLOCK BOARD)
Figure 1. Demo Board Setup
dc1763afb
2
DEMO MANUAL DC1763A
quick start procedure
Notes:
1.The DC1371 does not support 1- or 4-lane operation.
2.Optional jumper should be left open to ensure proper
serial configuration.
3.In the first revision of this demo board the jumpers
were mislabeled. For boards labeled with a Rev 1 use
the following jumper positions:
a. JP8: Term: Selects either 1.75mA or 3.5mA of output
current for the LVDS drivers. (Default: 3.5mA)
b. JP14/JP5: ILVDS/LANE: Two bits that select between
one, two and four lanes.
JP14 – ILVDS
JP5 LANE
NUMBER OF LANES
3.5mA
2
2
3.5mA
1
1
1.75mA
2
4
1.75mA
1
Not Used
Applying Power and Signals to the DC1763A
Demonstration Circuit
If a DC1371 is used to acquire data from the DC1763A, the
DC1371 must FIRST be connected to a powered USB port
and have 5V applied BEFORE applying 3.0V to 6V across
the pins marked V+ and GND on the DC1763A. DC1763A
requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1763A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC1763A should not be removed, or connected to
the DC1371 while power is applied.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequencies above 140MHz, refer to the LTC2195 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a gallium arsenide gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA connectors on the DC1763A demonstration circuit board
marked J3 AIN1 and J4 AIN2. These inputs correspond
with channels one and two of the ADC respectively. These
inputs are capacitively coupled to balun transformers
ETC1-1-13 (lead free part number MABA007159-000000).
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1763A demonstration circuit board marked J12
CLK+. As a default the DC1763A is populated to have a
single-ended input.
For the best noise performance, the encode clock must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3VP-P or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2195. Using band pass filters on the clock and
the analog input will improve the noise performance by
reducing the wideband noise power of the signals. In
the case of the DC1763A a band pass filter used for the
clock should be used prior to the DC1075. Data sheet FFT
plots are taken with 10-pole LC filters made by TTE (Los
Angeles, CA) to suppress signal generator harmonics,
non-harmonically related spurs and broadband noise.
Low phase noise Agilent 8644B generators are used for
both the clock input and the analog input.
dc1763afb
3
DEMO MANUAL DC1763A
quick start procedure
Digital Outputs
The data outputs, data clock, and frame clock signals are
available on J1 of the DC1763A. This connector follows the
VITA-57/FMC standard, but all signals should be verified
when using an FMC carrier card other than the DC1371.
Figure 2. PScope Toolbar
Software
The DC1371 is controlled by the PScope™ System Software provided or downloaded from the Linear Technology
website at http://www.linear.com/software/.
To start the data collection software if PScope.exe, is installed (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1763A demonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC1763A, and configure itself accordingly. If everything is
hooked up properly, powered and a suitable convert clock
is present, clicking the Collect button should result in time
and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the
DC1371 Quick Start Guide and in the online help available
within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1763A board
serially through the DC1371. There are several options
available in the LTC2195 family that are only available
through serially programming. PScope allows all of these
features to be tested.
Figure 3. Demobd Configuration Options
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 2).
This will bring up the menu shown in Figure 3.
dc1763afb
4
DEMO MANUAL DC1763A
quick start procedure
This menu allows any of the options available for the
LTC2195 family to be programmed serially. The LTC2195
family has the following options:
Randomizer: Enables data output randomizer
• Off (Default): Disables data output randomizer
• On: Enables data output randomizer
Two’s Complement: Enables two’s complement mode
• Off (Default): Selects offset binary mode
• On: Selects two’s complement mode
Sleep Mode: Selects between normal operation, sleep
mode:
Output Current: Selects the LVDS output drive current
• 1.75mA (Default): LVDS output driver current
• 2.1mA: LVDS output driver current
• 2.5mA: LVDS output driver current
• 3.0mA: LVDS output driver current
• 3.5mA: LVDS output driver current
• 4.0mA: LVDS output driver current
• 4.5mA: LVDS output driver current
Internal Termination: Enables LVDS internal termination
• Off (Default): Disables internal termination
• Off (Default): Entire ADC is powered, and active
• On: Enables internal termination
• On: The entire ADC is powered down.
Outputs: Enables digital outputs
Channel 1 Nap: Selects between normal operation and
putting channel 1 in nap mode.
• Enabled (Default): Enables digital outputs
• Off (Default): Channel one is active
Test Pattern: Selects digital output test patterns. The
desired test pattern can be entered into the text boxes
provided.
• On: Channel one is in nap mode
Channel 2 Nap: Selects between normal operation and
putting channel 2 in nap mode.
• Disabled: Disables digital outputs
• Off (Default): ADC input data is displayed
• Off (Default): Channel two is active
• On: Test pattern is displayed.
• On: Channel two is in nap mode
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC1763A demo board.
dc1763afb
5
DEMO MANUAL DC1763A
parts list
ITEM
QTY
REFERENCE
PART DESCRIPTION
MANUFACTURER/PART NUMBER
CAP, ARRAY, 0508 2.2µF 20% 4V X5R
AVX, W2L14D225MAT1A
General BOM
1
1
CN1
2
11
C5, C7, C8, C9, C15, C16, C18, C28, CAP., X5R, 0.1µF, 10V, 10% 0402
C36, C48, C52
AVX, 0402ZD104KAT2A
3
1
C4
CAP., X5R, 1µF, 10V, 10% 0402
AVX, 0402ZD105KAT2A
4
1
C6
CAP., TANT., 100µF, 16V, 10% 6032
AVX, TPSC107K016R0200
5
3
C10, C53, C54
CAP., X7R, 1µF,10V, 10% 0603
AVX, 0603ZC105KAT2A
6
1
C17
CAP., X5R, 2.2µF, 10V, 20% 0603
AVX, 0603ZD225MAT2A
7
2
C29, C37
CAP., X5R, 2.2µF, 6.3V, 20% 0402
AVX, 04026D225MAT2A
8
7
C30, C38, C43-C47
CAP., X7R, 0.01µF, 16V, 10% 0402
AVX, 0402YC103KAT2A
9
4
C31, C32, C39, C40
CAP., COG, 8.2pF, 50V, 5% 0402
AVX, 04025A8R2JAT2A
10
1
C49
CAP., X7R, 0.01µF, 25V, 10% 0402
AVX, 04023C103KAT2A
11
1
C51
CAP., X5R, 4.7µF, 6.3V 20% 0603
AVX, 06036D475MAT2A
12
1
J1
BGA CONNECTOR, 40X10
SAMTEC, SEAM-40-02.0-S-10-2-A
13
6
JP2, JP5, JP8, JP13, JP14, JP15
HEADER, 3-PIN 0.079 SINGLE ROW
SAMTEC, TMM-103-02-L-S
14
2
J3, J4
CON., SMA 50Ω, EDGE-LAUNCH
EF JOHNSON, 142-0701-851
15
2
J11, J12
CON.,SMA JACK, STRAIGHT, THRU-HOLE
AMPHENOL CONNEX, 132134
16
2
L4, L5
INDUCTOR, 56nH 0603
MURATA, LQP18MN56NG02D
17
1
L7
FERRITE BEAD, 0603
MURATA, BLM18BB470SN1D
18
2
L9, L11
FERRITE BEAD, 1206
MURATA, BLM31PG330SN1L
19
2
R1, R63
RES., CHIP, 0Ω 0402
YAGEO, RC0402FR-070RL
20
0
R2, R57-R59, R61, R62, R64, R65
OPT, RES, CHIP, 0402
21
12
R4, R5, R10, R36, R102-R109
RES., CHIP, 10k, 1/16W, 5% 0402
YAGEO, RC0402JR-0710KL
22
2
R8, R92
RES., CHIP, 100Ω, 1/16W, 1% 0402
YAGEO, RC0402FR-07100RL
23
6
R9, R11, R14, R72, R73, R74
RES., CHIP, 1k, 1/16W, 5% 0402
YAGEO, RC0402JR-071KL
24
1
R12
RES., CHIP, 31.6k, 1/16W, 1% 0402
YAGEO, RC0402FR-0731K6L
25
4
R26, R29, R39, R46
RES., CHIP, 64.9Ω, 1/16W, 1% 0402
VISHAY, CRCW040264R9FKED
26
9
R30, R47, R56, R60, R95-R99
RES., CHIP, 100Ω, 1/16W, 5% 0402
YAGEO, RC0402JR-07100RL
27
8
R31, R32, R33, R34, R48-R51
RES., CHIP, 10.0Ω, 1/16W, 1% 0402
YAGEO, RC0402FR-0710RL
28
2
R35, R52
RES., CHIP, 86.6Ω, 1/16W, 1%, 0402
YAGEO, RC0402FR-0786R6L
29
4
R37, R38, R53, R54
RES., CHIP, 86.6Ω, 1/16W, 1% 0603
YAGEO, RC0603FR-0786R6L
30
2
R40, R41
RES., CHIP, 49.9Ω, 1/16W, 1% 0402
YAGEO, RC0402FR-0749R9L
31
2
R42, R43
RES., CHIP, 5.1Ω,, 1/16W, 1% 0402
YAGEO, RC0402FR-075R1L
32
8
R110-R117
RES., CHIP, 33k, 1/16W, 1% 0402
YAGEO, RC0402FR-0733KL
33
3
TP1, TP6, TP7
TESTPOINT, TURRET, 0.094, PBF
MILL- MAX, 2501-2-00-80-00-00-07-0
34
3
T5, T9, T11
TRANSFORMER, RF~SMT~1:1BALUN
MACOM, MABA-007159-000000
35
2
T8, T10
TRANSFORMER, FLUX-COUPLED BALUN
MACOM, MABAES0060
36
1
U2
IC, LT1763CS8-1.8 SO8
LINEAR TECH., LT1763CS8-1.8#PBF
37
1
U3
I.C. EEPROM 32KBIT 400kHz 8TSSOP
MICROCHIP, 24LC32A-I/ST
38
6
XJ2, XJ5, XJ8, XJ13, XJ14, XJ15
SHUNT, 0.079" CENTER
SAMTEC, 2SN-BK-G
dc1763afb
6
DEMO MANUAL DC1763A
parts list
ITEM
QTY
DC1763A-A
1
1
2
2
3
4
4
2
5
1
DC1763A-B
1
1
2
2
3
4
4
2
5
1
DC1763A-C
1
1
2
2
3
4
4
2
5
1
DC1763A-D
1
1
2
2
3
4
4
2
5
1
DC1763A-E
1
1
2
2
3
4
4
2
5
1
DC1763A-F
1
1
2
2
3
4
4
2
5
1
DC1763A-G
1
1
2
2
3
4
4
2
5
1
REFERENCE
PART DESCRIPTION
MANUFACTURER/PART NUMBER
C2, C3
C25, C26, C33, C34
C27, C35
U1
GENERAL BOM
CAP., X5R, 0.1µF, 10V, 10% 0402
CAP., X7R, 0.01µF, 50V, 10% 0603
CAP, COG, 4.7pF, 50V, 5% 0402
DUAL A/D CONVERTER
DC1763A
AVX, 0402ZD104KAT2A
AVX, 06035C103KAT2A
AVX, 04025A4R7JAT2A
LINEAR TECH., LTC2195CUKG
C2, C3
C25, C26, C33, C34
C27, C35
U1
GENERAL BOM
CAP., X5R, 0.1µF, 10V, 10% 0402
CAP., X7R, 0.01µF, 50V, 10% 0603
CAP, COG, 4.7pF, 50V, 5% 0402
DUAL A/D CONVERTER
DC1763A
AVX, 0402ZD104KAT2A
AVX, 06035C103KAT2A
AVX, 04025A4R7JAT2A
LINEAR TECH., LTC2194CUKG
C2, C3
C25, C26, C33, C34
C27, C35
U1
GENERAL BOM
CAP., X5R, 0.1µF, 10V, 10% 0402
CAP., X7R, 0.01µF, 50V, 10% 0603
CAP, COG, 4.7pF, 50V, 5% 0402
DUAL A/D CONVERTER
DC1763A
AVX, 0402ZD104KAT2A
AVX, 06035C103KAT2A
AVX, 04025A4R7JAT2A
LINEAR TECH., LTC2193CUKG
C2, C3
C25, C26, C33, C34
C27, C35
U1
GENERAL BOM
CAP., X5R, 0.1µF, 10V, 10% 0402
CAP., X7R, 0.01µF, 50V, 10% 0603
CAP, COG, 4.7pF, 50V, 5% 0402
DUAL A/D CONVERTER
DC1763A
AVX, 0402ZD104KAT2A
AVX, 06035C103KAT2A
AVX, 04025A4R7JAT2A
LINEAR TECH., LTC2192CUKG
C2, C3
C25, C26, C33, C34
C27, C35
U1
GENERAL BOM
CAP., X5R, 0.1µF, 10V, 10% 0402
CAP., X7R, 0.01µF, 50V, 10% 0603
CAP, COG, 4.7pF, 50V, 5% 0402
DUAL A/D CONVERTER
DC1763A
AVX, 0402ZD104KAT2A
AVX, 06035C103KAT2A
AVX, 04025A4R7JAT2A
LINEAR TECH., LTC2191CUKG
C2, C3
C25, C26, C33, C34
C27, C35
U1
GENERAL BOM
CAP., X5R, 0.1µF, 10V, 10% 0402
CAP., X7R, 0.01µF, 50V, 10% 0603
CAP, COG, 4.7pF, 50V, 5% 0402
DUAL A/D CONVERTER
DC1763A
AVX, 0402ZD104KAT2A
AVX, 06035C103KAT2A
AVX, 04025A4R7JAT2A
LINEAR TECH., LTC2190CUKG
C2, C3
C25, C26, C33, C34
C27, C35
U1
GENERAL BOM
CAP, 0402 1µF 20% 10V X5R
CAP, 0402 0.1µF 10% 10V X5R
CAP, 0402 10pF 5% 50V NPO
DUAL A/D CONVERTER
DC1763A
TDK C1005X5R1A105M
TDK C1005X5R1A104K
AVX 04025A100JAT2A
LINEAR TECH., LTC2271CUKG
dc1763afb
7
A
B
C
D
CLK-
CLK+
AIN2
AIN1
GND
V+
3V - 6V
J12
J11
J4
J3
TP7
TP6
C25*
C49
0.01uF
0603
0.01uF
C33*
0603
0.01uF
86.6
5
R63 0
C40
8.2pF
C39
8.2pF
L5
R54
86.6
56nH
R52
R53
86.6
86.6
C32
8.2pF
SHDN
C31
8.2pF
5
R38
86.6
56nH
L4
R35
C53
1uF
0603
IN
R37
86.6
C51
4.7uF
0603
8
4
1
2
T11
3
2
1
0603
C34*
0.01uF
4
5
0.01uF
C43
0.01uF
C44
R61
OPT
3
2
1
T8
3
2
1
C54
1uF
0603
4
5
T10
3
2
1
C30
0.01uF
MABAES0060
4
5
C10
1uF
0603
T5
R62
OPT
C38
0.01uF
4
5
R64
OPT
C45
0.01uF
3
2
1
6032
R46
64.9
R39
64.9
4
BEAD
L7
R40
49.9
10
R50
R42
5.1
R43
5.1
C37
2.2uF
C35*
4.7pf
10
R51
10
R33
10
R34
VDD
C29
2.2uF
C27*
4.7pf
BEAD
L11
BEAD
L9
R41
49.9
R65
OPT
100
R47
VDD
10
R49
10
R48
100
C28
0.1uF
R30
10
R32
R29
64.9
R26
64.9
10
R31
+ C6
100uF
MABA-007159-000000
C36
0.1uF
MABAES0060
MABA-007159-000000
0603
C26*
0.01uF
4
5
MABA-007159-000000
T9
BYP
OUT
SEN/ADJ
U2
LT1763CS8-1.8
GND
GND
GND
3
6
7
4
100
R60
C52
0.1uF
OVDD
R59
OPT
R57
OPT
R58
OPT
R92
100
R8
100
C46
C47
C2*
0.1uF
0.01uF
0.01uF
PAR/!SER
12
3
2. INSTALL SHUNTS AS SHOWN.
1. ALL RESISTORS ARE IN OHMS, 0402.
ALL CAPACITORS ARE IN MICROFARADS, 0402.
VDD
14
13
11
10
9
8
AIN2-
5
6
3
4
7
7
5
4
3
2
1
MISO
2
U1*
44
43
48
CUSTOMER NOTICE
-G
-F
-E
-D
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
0.01uF
20
25
40
65
SCALE = NONE
APPROVED
DATE
CLARENCE M. 10/22/2010
1.0uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C2,C3
DATE:
N/A
SIZE
1
DEMO CIRCUIT 1763A
SHEET 1
LTC219XCUKG FAMILY
3/04/2013
IC NO.
1
OF 2
REV.
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
10pF
4.7pF
4.7pF
4.7pF
4.7pF
4.7pF
4.7pF
TECHNOLOGY
0.1uF
0.01uF
0.01uF
0.01uF
0.01uF
0.01uF
105
80
C16
0.1uF
C25.C26.C33.C34 C27,C35
125
Msps
CLARENCE M. TITLE: SCHEMATIC
M.H.
APPROVALS
LTC2271CUKG
LTC2190CUKG
LTC2191CUKG
LTC2192CUKG
LTC2193CUKG
LTC2194CUKG
-B
-C
U1
LTC2195CUKG
-A
C15
0.1uF
C9
0.1uF
OUT2D-
OUT2D+
OUT2C-
OUT2C+
OUT2B-
OUT2B+
OUT2A-
OUT2A+
FR-
FR+
OVDD
C7
0.1uF
C8
0.1uF
OUT1D-
OUT1D+
OUT1C-
DCO-
FIRST PROTOTYPE
ADDED -G ASS'Y OPTION CLARENCE M. 3/04/2013
OUT1C+
DCO+
1
DESCRIPTION
REVISION HISTORY
OVDD
27
28
29
30
31
32
33
34
35
36
37
ASSY
*
39
38
1
N/A
REV
ECO
VDD
OUT2B-
OUT2B+
OUT2A-
OUT2A+
FR-
FR+
OGND
OVdd
DCO-
DCO+
OUT1D-
OUT1D+
OUT1C-
40
OUT1B-
OUT1B+
OUT1A-
OUT1A+
OUT1C+
ASSEMBLY TABLE
CS0
SCK
MOSI
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APP ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
VCM2
GND
AIN2-
AIN2+
PAR/SER
REFL
REFH
REFL
REFH
GND
AIN1-
AIN1+
GND
VCM1
C4
1uF
2
C5
0.1uF
VDD
6
R14
1K
CN1
2.2uF
1
8
C17
2.2uF
0603
AIN2+
0508
TP1
NOTE: UNLESS OTHERWISE SPECIFIED
100
R56
C48
0.1uF
C3*
0.1uF
AIN1-
AIN1+
EXT REF
3
52
Vdd
51
Vdd
15
Vdd
50
Vdd
16
49
GND
SENSE
ENC+
17
47
GND
SCK
20
ENC-
18
46
SDO
SDI
21
Vref
CS
19
45
GND
GND
22
42
OUT1A-
OUT1A+
OUT2D-
23
OUT1B+
24
OUT2D+
25
OUT2C-
41
OUT1BOUT2C+
53
EP
8
26
5
A
B
C
D
DEMO MANUAL DC1763A
Schematic Diagram
dc1763afb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
A
B
C
D
R2
OPT
0
R1
C0
JP13
R110
33K
5
R95
100
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
PAR/SER
R102
10K
2
R72
1K
GND
DP1_M2C_P
DP1_M2C_N
GND
GND
DP2_M2C_P
DP2_M2C_N
GND
GND
DP3_M2C_P
DP3_M2C_N
GND
GND
DP4_M2C_P
DP4_M2C_N
GND
GND
DP5_M2C_P
DP5_M2C_N
GND
GND
DP1_C2M_P
DP1_C2M_N
GND
GND
DP2_C2M_P
DP2_C2M_N
GND
GND
DP3_C2M_P
DP3_C2M_N
GND
GND
DP4_C2M_P
DP4_C2M_N
GND
GND
DP5_C2M_P
DP5_C2M_N
GND
SEAM-10X40PIN
J1A
3.3_AUX
SER
PAR
1
3
C1
R111
33K
R103
10K
C2
R112
33K
R104
10K
R12
31.6K
DIS
EN
SEAM-10X40PIN
RES1
GND
GND
DP9_M2C_P
DP9_M2C_N
GND
GND
DP8_M2C_P
DP8_M2C_N
GND
GND
DP7_M2C_P
DP7_M2C_N
GND
GND
DP6_M2C_P
DP6_M2C_N
GND
GND
GBTCLK1_M2C_P
GBTCLK1_M2C_N
GND
GND
DP9_C2M_P
DP9_C2M_N
GND
GND
DP8_C2M_P
DP8_C2M_N
GND
GND
DP7_C2M_P
DP7_C2M_N
GND
GND
DP6_C2M_P
DP6_C2M_N
GND
GND
RES0
J1B
PAR/!SER
R10
10K
3.3_AUX
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
C3
R113
33K
R105
10K
TERM
JP8
2
R11
1K
VDD
R114
33K
GND
CLK0_C2M_P
CLK0_C2M_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
C4
R106
10K
RUN
4
SEAM-10X40PIN
J1G
MISO
SHDN
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
C5
MOSI
R115
33K
R107
10K
SHDN
JP15
2
R74
1K
VDD
1
3
VDD
1
3
R116
33K
OUT2D-
OUT2C-
OUT2B-
OUT2A-
OUT1D-
OUT1C-
OUT1B-
OUT1A-
C6
2
JP5
ILVDS
OUT2D+
OUT2C+
OUT2B+
OUT2A+
OUT1D+
OUT1C+
OUT1B+
CHANNEL 2
CHANNEL 1
R117
33K
R109
10K
CS0
SCK
OUT1A+
C7
JP14
LANE
2
R73
1K
VDD
R108
10K
2
1
3.5mA
1.75mA
R9
1K
VDD
1
3
1
3
4
3
VREF_A_M2C
PRSNT_M2C_N
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
SEAM-10X40PIN
J1H
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
SEAM-10X40PIN
J1C
3
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
100
2
SCK
MOSI
FR-
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
VDD
R5 R4
10K 10K
FR+
GND
HA01_P_CC
HA01_N_CC
GND
GND
HA05_P
HA05_N
GND
HA09_P
HA09_N
GND
HA13_P
HA13_N
GND
HA16_P
HA16_N
GND
HA20_P
HA20_N
GND
HB03_P
HB03_N
GND
HB05_P
HB05_N
GND
HB09_P
HB09_N
GND
HB13_P
HB13_N
GND
HB21_P
HB21_N
GND
HB20_P
HB20_N
GND
VADJ
GND
SCL
SDA
WP
A2
A1
A0
SEAM-10X40PIN
J1E
6
5
7
3
2
1
R36
10K U3
24LC32A-I /ST
MISO
CS0
2
2
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
C18
0.1uF
SCALE = NONE
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
1
C7
C6
C5
C4
C3
C2
C1
C0
DATE:
N/A
SIZE
1
DEMO CIRCUIT 1763A
SHEET 2
LTC219XCUKG FAMILY
3/04/2013
IC NO.
1
OF 2
REV.
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900 www.linear.com
Fax: (408)434-0507
LTC Confidential-For Customer Use Only
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K40
3.3_AUX
DCO-
DCO+
DATA
CLOCK
VREF_B_M2C
GND
GND
CLK1_M2C_P
CLK1_M2C_N
GND
HA02_P
HA02_N
GND
HA06_P
HA06_N
GND
HA10_P
HA10_N
GND
HA17_P_CC
HA17_N_CC
GND
HA21_P
HA21_N
GND
HA23_P
HA23_N
GND
HB00_P_CC
HB00_N_CC
GND
HB06_P_CC
HB06_N_CC
GND
HB10_P
HB10_N
GND
HB14_P
HB14_N
GND
HB17_P_CC
HB17_N_CC
GND
VIO_B_M2C
SEAM-10X40PIN
J1K
TECHNOLOGY
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
CLARENCE M. TITLE: SCHEMATIC
M.H.
GND
CLK1_C2M_P
CLK1_C2M_N
GND
GND
HA03_P
HA03_N
GND
HA07_P
HA07_N
GND
HA11_P
HA11_N
GND
HA14_P
HA14_N
GND
HA18_P
HA18_N
GND
HA22_P
HA22_N
GND
HB01_P
HB01_N
GND
PB07_P
HB07_N
GND
HB11_P
HB11_N
GND
HB15_P
HB15_N
GND
HB18_P
HB18_N
GND
VIO_B_M2C
GND
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_N
GA1
3P3V
GND
3P3V
GND
3P3V
SEAM-10X40PIN
J1D
SEAM-10X40PIN
J1J
APPROVALS
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
PCB DES.
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APP ENG.
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
CUSTOMER NOTICE
PG_M2C
GND
GND
HA00_P_CC
HA00_N_CC
GND
HA04_P
HA04_N
GND
HA08_P
HA08_N
GND
HA12_P
HA12_N
GND
HA15_P
HA15_N
GND
HA19_P
HA19_N
GND
HB02_P
HB02_N
GND
HB04_P
HB04_N
GND
HB08_P
HB08_N
GND
HB12_P
HB12_N
GND
HB16_P
HB16_N
GND
HB19_P
HB19_N
GND
VADJ
SEAM-10X40PIN
J1F
JP2
EN
WP
DIS
R99
100
R98100
R97
R96 100
FRAME
CLOCK
1
3
8
VCC
VSS
4
5
A
B
C
D
DEMO MANUAL DC1763A
Schematic Diagram
dc1763afb
9
DEMO MANUAL DC1763A
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
dc1763afb
10 Linear Technology Corporation
LT 0815 REV B • PRINTED IN USA08
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2011
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