TOSHIBA TMP19A64F20AXBG

32 bit TX System RISC
TX19A Family
TMP19A64F20AXBG
Rev1.1
2007.March.16
TMP19A64F20AXBG
Contents
TMP19A64F20AXBG
1.
2.
3.
4.
・Overview and Features
・Pin Layout and Pin Functions
・Flash Memory Operation
・Electrical Characteristics
TMP19A64(rev1.1)-1
TMP19A64F20AXBG
32-bit RISC Microprocessor - TX19 Family
TMP19A64F20AXBG
1.
Overview and Features
The TX19 family is a high-performance 32-bit RISC processor series that TOSHIBA originally developed by
integrating the MIPS16TMASE (Application Specific Extension), which is an extended instruction set of high code
efficiency.
TMP19A64 is a 32-bit RISC microprocessor with a TX19A processor core and various peripheral functions
integrated into one package. It can operate at low voltage with low power consumption.
Features of TMP19A64 are as follows:
(1) TX19A processor core
1)
2)
Improved code efficiency and operating performance have been realized through the use of two ISA
(Instruction Set Architecture) modes - 16- and 32-bit ISA modes.
•
The 16-bit ISA mode instructions are compatible with the MIPS16 TMASE instructions of superior
code efficiency at the object level.
•
The 32-bit ISA mode instructions are compatible with the TX39 instructions of superior operating
performance at the object level.
Both high performance and low power consumption have been achieved.
z High performance
RESTRICTIONS ON PRODUCT USE
070122EBP
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility
of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire
system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life,
bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in
the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the
“Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products
are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a
malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include
atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products
listed in this document shall be made at the customer’s own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture,
use and/or sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed
by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is
granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C
• The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled
Quality and Reliability Assurance/Handling Precautions. 030619_S
TMP19A64(rev1.0)1-1
TMP19A64F20AXBG
•
Almost all instructions can be executed with one clock.
•
High performance is possible via a three-operand operation instruction.
•
5-stage pipeline
•
Built-in high-speed memory
•
DSP function: A 32-bit multiplication and accumulation operation can be executed with one clock.
z Low power consumption
3)
•
Optimized design using a low power consumption library
•
Standby function that stops the operation of the processor core
High-speed interrupt response suitable for real-time control
•
Independency of the entry address
•
Automatic generation of factor-specific vector addresses
•
Automatic update of interrupt mask levels
(2) On Chip program memory and data memory
Product name
On chip ROM
On chip RAM
TMP19A64F20AXBG
2 Mbytes (Flash)
64 Kbytes
TMP19A64C1DXBG
1.5 Mbytes
56 Kbytes
•
ROM correction function: 1 word × 8 blocks, 8 words × 4 blocks
•
Backup RAM: 512 bytes
(3) External memory expansion
•
16-Mbyte off-chip address for code and date
•
External data bus:
Separate bus/multiplexed bus
•
Chip select/wait controller
(4) DMA controller
•
: Dynamic bus sizing for 8- and 16-bit widths ports.
: 6 channels
: 8 channels
Data to be transferred to internal memory, internal I/O, external memory, and external I/O
(5) 16-bit timer
: 11 channels
•
16-bit interval timer mode
•
16-bit event counter mode
•
16-bit PPG output
•
Event capture function
•
2-phase pulse input counter function (1 channel assigned to perform this function):
Multiplication-by-4 mode
(6) 32-bit timer
•
32-bit input capture register
: 4 channels
•
32-bit compare register
: 10 channels
•
32-bit time base timer
: 1 channel
(7) Clock timer
: 1 channel
(8) General-purpose serial interface: 7 channels
•
Either UART mode
(9) Serial bus interface
•
or synchronous mode can be selected.
: 1 channel
2
Either I C bus mode or clock synchronous mode can be selected
TMP19A64(rev1.0)1-2
TMP19A64F20AXBG
(10) 10-bit A/D converter with (S/H)
: 24 channels
•
Conversion speed: 54 clocks (7.85 μ[email protected] MHz)
•
Start by an internal timer trigger
•
Fixed channel/scan mode
•
Single/repeat mode
•
High-priority conversion mode
•
Timer monitor function
(11) Watchdog timer
: 1 channel
(12) Interrupt source
•
CPU: 2 factors ............. software interrupt instruction
•
Internal: 50 factors....... The order of precedence can be set over 7 levels
(except the watchdog timer interrupt).
•
External: 20 factors...... The order of precedence can be set over 7 levels
(except the NMI interrupt).
Because 8 factors are associated with KWUP, the number of interrupt
factors is one.
(13) 209 pins Input/output ports
(14) Standby mode
•
4 standby modes (IDLE, SLEEP, STOP and BACKUP)
(15) Clock generator
•
On-chip PLL (multiplication by 4)
•
Clock gear function: The high-speed clock can be divided into 8/8, 7/8, 6/8, 5/8, 4/8, 2/8 or 1/8.
•
Sub-clock: SLOW, SLEEP and BACKUP modes (32.768 kHz)
(16) Endian: Bi-endian (big-endian/little-endian)
(17) Maximum operating frequency
•
54 MHz (PLL multiplication)
(18) Operating voltage range
Core: 1.35 V to 1.65 V
I/O: 1.65 V to 3.3 V
ADC: 2.7 V to 3.3 V
Backup block : 2.3 V to 3.3 V (under normal operating conditions)
: 1.8 V to 3.3 V (in BACKUP mode)
(19) Package
•
P-FBGA281 (13 mm × 13 mm, 0.65 mm pitch)
TMP19A64(rev1.0)1-3
TMP19A64F20AXBG
TX19 Processor Core
TX19A CPU
MAC
EJTAG
2-Mbyte
Flash
64-Kbyte
RAM
ROM correction
DMAC
(8ch)
CG
INTC
EBIF
Backup block
Clock timer (1ch)
Backup RAM
(512 bytes)
I/O bus I/F
PORT0
to
PORT6
(also function as
external bus I/F)
PORT7
to
PORT9
(also function to
receive ADC inputs)
16-bit TMRB
0 to A (11ch)
32-bit TMRC
TBT (1ch)
32-bit TMRC
Input Capture
0 to 3 (4ch)
PORTA
to
PORTK, PORTO
(also function as
functional pins)
32-bit TMRC
Compare
0 to 9 (10ch)
PORTL to PORTN
PORTP to PORTQ
(General-purpose ports)
10-bit ADC (24ch)
SIO/UART
0 to 6 (7ch)
KWUP
0 to 7 (8ch)
WDT
I2C/SIO
(1ch)
Fig. 1-1 TMP19A64F20AXBG Block Diagram
TMP19A64(rev1.0)1-4
TMP19A64F20AXBG
2.
2.1
Pin Layout and Pin Functions
Pin Layout
Fig. 2.1.1 shows the pin layout of TMP19A64.
Fig. 2.1.1 Pin Layout Diagram (P-FBGA281)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 A11
A12 A13 A14 A15 A16 A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11
B12 B13 B14 B15 B16 B17 B18
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10 C11 C12 C13 C14 C15 C16 C17 C18
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15 D16 D17 D18
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10 E11
E12 E13 E14 E15 E16 E17 E18
F1
F2
F3
F4
F5
F7
F8
F9
F10 F11
F12
G1
G2
G3
G4
G5
G6
G13 G14 G15 G16 G17 G18
H1
H2
H3
H4
H5
H6
H13 H14 H15 H16 H17 H18
J1
J2
J3
J4
J5
J6
J13
K1
K2
K3
K4
K5
K6
K13 K14 K15 K16 K17 K18
L1
L2
L3
L4
L5
L6
L13
M1
M2
M3
M4
M5
M6
M13 M14 M15 M16 M17 M18
N1
N2
N3
N4
N5
P1
P2
P3
P4
P5
R1
R2
R3
R4
T1
T2
T3
U1
U2
V2
F14 F15 F16 F17
J14
L14
J15
L15
J16
L16
J17
L17
F18
J18
L18
N7
N8
N9
N10 N11 N12
N14 N15 N16 N17 N18
P6
P7
P8
P9
P10 P11
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 R15 R16 R17 R18
T4
T5
T6
T7
T8
T9
T10 T11
U3
U4
U5
U6
U7
U8
U9
U10 U11 U12 U13 U14 U15 U16 U17 U18
V3
V4
V5
V6
V7
V8
V9
V10 V11
P12 P13 P14 P15 P16 P17 P18
T12 T13 T14 T15 T16 T17 T18
V12 V13 V14 V15 V16 V17
Table 2.1.2 shows the pin numbers and names of TMP19A64.
Table 2.1.2 Pin Numbers and Names (1 of 2)
Pin
No.
Pin name
Pin
No.
Pin name
Pin
No.
Pin name
Pin
No.
Pin name
Pin
No.
Pin name
A1
A2
A3
A4
A5
A6
A7
A8
N.C.
VREFL
P90/AN16
P93/AN19
P80/AN8
P83/AN11
P70/AN0
P74/AN4
A13
A14
A15
A16
A17
B1
B2
B3
PN2
PN0
PM5
PM1
X2
AVCC31
VREFH
P91/AN17
B8
B9
B10
B11
B12
B13
B14
B15
P75/AN5
PL0
PL3
PO5/TXD6
PO1/INT1
PN3
PN1
PM4
C2
C3
C4
C5
C6
C7
C8
C9
PCST3 (EJTAG)
P92/AN18
P95/AN21
P82/AN10
P85/AN13
P72/AN2
AVSS
PL1
C14
C15
C16
C17
C18
D1
D2
D3
PM7
PM3
PK3/KEY3
CVCC15
XT2
TDO (EJTAG)
PCST2 (EJTAG)
DINT (EJTAG)
A9
A10
A11
A12
PO7/SCLK6/CTS6
PL2
PO6/RXD6
PO0/INT0
B4
B5
B6
B7
P94/AN20
P81/AN9
P84/AN12
P71/AN1
B16
B17
B18
C1
PM0
CVSS/BVSS
X1
PCST0 (EJTAG)
C10
C11
C12
C13
PL4
PO4/INT4
PN6
PN4
D4
D5
D6
D7
DVCC15
P96/AN22
P86/AN14
P73/AN3
TMP19A64(rev1.1)2-1
TMP19A64F20AXBG
Table 2.1.1 Pin Numbers and Names (2 of 2)
Pin
No.
Pin name
Pin
No.
D8
D9
D10
D11
D12
D13
DVCC15
DVSS
PL5
PO3/INT3
PN7
PN5
F18
G1
G2
G3
G4
G5
D14
PM2
D15
Pin
No.
Pin name
Pin
No.
Pin name
Pin
No.
Pin name
K14
K15
K16
K17
K18
L1
PI1/INT1
PI3/INT3
PI4/INT4
DVCC30
PI2/INT2
FVCC3
N18
P1
P2
P3
P4
P5
P14/D12/AD12/A12
PE4
PA2/TB0OUT
PA3/TB1IN0/INT7
PA4/TB1IN1/INT8
PA5/TB1OUT
T8
T9
T10
T11
T12
T13
PD4/TXD4
PC0/TXD0
PC3/TXD1
PH4/TCOUT8
PH6
P53/A3
G6
P46/SCOUT
RESET
TDI (EJTAG)
FVCC15
DVSS
TOVR/TSTA
(EJTAG)
BW0
L2
P6
PB6/TBAIN0
T14
P61/A9
DVCC34
G13
PK7/KEY7
L3
P7
PG2/TC2IN
T15
P21/A17/A1/A17
D16
PK2/KEY2
G14
BRESET
L4
PQ1/TPD1/TPC1
(EJTAG)
PQ2/TPD2/TPC2
(EJTAG)
PQ3/TPD3/TPC3
(EJTAG)
P8
PD6/SCLK4/CTS4
T16
P23/A19/A3/A19
D17
D18
E1
E2
E3
E4
E5
E6
E7
PK4/KEY4
XT1
DCLK (EJTAG)
PCST1 (EJTAG)
TRST (EJTAG)
PCST4 (EJTAG)
ENDIAN
P97/AN23
P87/AN15
G15
G16
G17
G18
H1
H2
H3
H4
H5
P41/CS1
P37/ALE
P35/BUSAK
FVCC15
NMI
DVCC31
PP7/TPD7 (EJTAG)
BW1
PLLOFF
L5
L6
L13
L14
L15
L16
L17
L18
M1
P9
P10
P11
P12
P13
P14
P15
P16
P17
PC2/SCLK0/CTS0
PC5/SCLK1/CTS1
P52/A2
P62/A10
P65/A13
P26/A22/A6/A22
P02/D2/AD2
P10/D8/AD8/A8
P12/D10/AD10/A10
T17
T18
U1
U2
U3
U4
U5
U6
U7
P00/D0/AD0
P01/D1/AD1
PB4/TB8OUT
PB3/TB7OUT
PB7/TBAIN1
PF1/SI/SCL
PF5/DREQ3
PG1/TC1IN
PD2/RXD3
E8
P76/AN6
H6
TCK (EJTAG)
M2
P18
P11/D9/AD9/A9
U8
DVCC32
E9
P77/AN7
H13
TEST1
M3
R1
PA0/TB0IN0/INT5
U9
PC7/RXD2
E10
E11
E12
E13
E14
E15
E16
E17
E18
F1
F2
F3
F4
F5
F7
F8
F9
F10
F11
F12
PL6
PL7
PM6
PK6/KEY6
PK5/KEY5
BVCC
PK1/KEY1
PK0/KEY0
DVCC15
DVSS
TMS (EJTAG)
EJE (EJTAG)
BUSMD
BOOT
AVSS
AVSS
AVCC32
DVCC34
PO2/INT2
DVSS
H14
H15
H16
H17
H18
J1
J2
J3
J4
J5
J6
J13
J14
J15
J16
J17
J18
K1
K2
K3
P31/WR
P32/HWR
P33/WAIT/RDY
P30/RD
P40/CS0
PP2/TPD2 (EJTAG)
PP3/TPD3 (EJTAG)
PP4/TPD4 (EJTAG)
PP5/TPD5 (EJTAG)
PP6/TPD6 (EJTAG)
FVCC15
DVSS
P47
N.C.
P44/CS4
P36/ R/W
P34/BUSRQ
PP0/TPD0 (EJTAG)
PP1/TPD1 (EJTAG)
PQ5/TPD5/TPC5
(EJTAG)
PQ6/TPD6/TPC6
(EJTAG)
DVSS
DVSS
TEST2
M4
M5
M6
M13
M14
M15
M16
M17
M18
N1
N2
N3
N4
N5
N7
N8
N9
N10
N11
N12
PE6/INTA
PE7/INTB
P13/D11/AD11/A11
P17/D15/AD15/A15
FVCC15
PI0/INT0
P45/CS5
PJ3/DACK3
PQ0/TPD0/TPC0
(EJTAG)
PQ7/TPD7/TPC7
(EJTAG)
PQ4/TPD4/TPC4
(EJTAG)
PE3
PA7/TB3OUT
DVCC32
P06/D6/AD6
P07/D7/AD7
DVSS
PJ0/DREQ2
PJ2/DREQ3
PJ1/DACK2
PE5
PE0/TXD5
PE2/SCLK5/CTS5
PE1/RXD5
PA6/TB2OUT
DVSS
PD7/INT9
DVCC15
DVSS
P56/A6
DVSS
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
T1
T2
T3
PA1/TB0IN1/INT6
PF3/DREQ2
PF4/DACK2
PF7/TBTIN
PG7/TCOUT3
PG4/TCOUT0
PD5/RXD4
PC1/RXD0
PC4/RXD1
PH3/TCOUT7
P51/A1
P57/A7
P66/A14
P25/A21/A5/A21
P03/D3/AD3
P04/D4/AD4
P05/D5/AD5
PB0/TB4OUT
PB1/TB5OUT
PB2/TB6OUT
U10
U11
U12
U13
U14
U15
U16
U17
U18
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
PH1/TCOUT5
PH5/TCOUT9
P50/A0
P55/A5
DVCC33
P64/A12
P20/A16/A0/A16
P24/A20/A4/A20
FVCC3
PB5/TB9OUT
PG0/TC0IN
PF0/SO/SDA
PG3/TC3IN
PG6/TCOUT2
PD1/TXD3
PD0/SCLK2/CTS2
PC6/TXD2
PH2/TCOUT6
PH0/TCOUT4
PH7
N14
P27/A23/A7/A23
T4
PF2/SCK
V13
P54/A4
N15
N16
N17
P15/D13/AD13/A13
TEST3
P16/D14/AD14/A14
T5
T6
T7
PF6/DACK3
PG5/TCOUT1
PD3/SCLK3/CTS3
V14
V15
V16
P60/A8
P63/A11
P67/A15
V17
P22/A18/A2/A18
F14
F15
F16
F17
K4
BUPMD
P42/CS2
P43/CS3
DVCC33
K5
K6
K13
Pin name
TMP19A64(rev1.1)2-2
TMP19A64F20AXBG
2.2
Pin Names and Functions
Table 2.2.1 shows the names and functions of input/output pins.
Table 2.2.1 Pin Names and Functions (1 of 6)
Pin name
Number
of pins
Input or
output
Function
P00-P07
D0-D7
AD0-AD7
8
Input/output
Input/output
Input/output
Port 0: Input/output port that allows input/output to be set in units of bits
Data (lower): Data buses 0 to 7 (separate bus mode)
Address data (lower): Address data buses 0 to 7 (multiplexed bus mode)
P10-P17
D8-D15
AD8-AD15
A8-A15
P20-P27
A16-A23
A0-A7
A16-A23
P30
RD
P31
WR
8
Input/output
Input/output
Input/output
Output
Input/output
Output
Output
Output
Output
Output
Output
Output
Port 1: Input/output port that allows input/output to be set in units of bits
Data (upper): Data buses 8 to 15 (separate bus mode)
Address data (upper): Address data buses 8 to 15 (multiplexed bus mode)
Address: Address buses 8 to 15 (multiplexed bus mode)
Port 2: Input/output port that allows input/output to be set in units of bits
Address: Address buses 16 to 23 (separate bus mode)
Address: Address buses 0 to 7 (multiplexed bus mode)
Address: Address buses 16 to 23 (multiplexed bus mode)
Port 30: Port used exclusively for output
Read: Strobe signal for reading external memory
Port 31: Port used exclusively for output
Write: Strobe signal for writing data of D0 to D7 pins
P32
HWR
P33
WAIT
RDY
P34
BUSRQ
P35
BUSAK
1
Input/output
Output
Input/output
Input
Input
Input/output
Input
Input/output
Output
Port 32: Input/output port (with pull-up)
Write upper-pin data: Strobe signal for writing data of D8 to D15 pins
Port 33: Input/output port (with pull-up)
Wait: Pin for requesting CPU to put a bus in a wait state
Ready: Pin for notifying CPU that a bus is ready
Port 34: Input/output port (with pull-up)
Bus request: Signal requesting CPU to allow an external master to take the bus control authority
Port 35: Input/output port (with pull-up)
Bus acknowledge: Signal notifying that CPU has released the bus control authority in response
to BUSRQ
P36
R/W
1
Input/output
Output
Port 36: Input/output port (with pull-up)
Read/write: "1" shows a read cycle or a dummy cycle. "0" shows a write cycle.
P37
ALE
P40
CS0
P41
CS1
P42
CS2
P43
CS3
P44
CS4
P45
CS5
P46
SCOUT
1
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
P47
1
Input/output
Port 37: Input/output port
Address latch enable (address latch is enabled only if access to external memory is taking place)
Port 40: Input/output port (with pull-up)
Chip select 0: "0" is output if the address is in a designated address area.
Port 41: Input/output port (with pull-up)
Chip select 1: "0" is output if the address is in a designated address area.
Port 42: Input/output port (with pull-up)
Chip select 2: "0" is output if the address is in a designated address area.
Port 43: Input/output port (with pull-up)
Chip select 3: "0" is output if the address is in a designated address area.
Port 44: Input/output port (with pull-up)
Chip select 4: "0" is output if the address is in a designated address area.
Port 45: Input/output port (with pull-up)
Chip select 5: "0" is output if the address is in a designated address area.
Port 46: Input/output port
System clock output: Selectable between high- and low-speed clock outputs, as in the case of
CPU
Port 47: Input/output port
P50-P57
A0-A7
P60-P67
A8-A15
8
Input/output
Output
Input/output
Output
Port 5: Input/output port that allows input/output to be set in units of bits
Address: Address buses 0 to 7 (separate bus mode)
Port 6: Input/output port that allows input/output to be set in units of bits
Address: Address buses 8 to 15 (separate bus mode)
8
1
1
1
1
1
1
1
1
1
1
1
1
8
TMP19A64(rev1.1)2-3
TMP19A64F20AXBG
Table 2.2.1 Pin Names and Functions (2 of 6)
Pin name
Number
of pins
Input or
output
Function
P70-P77
AN0-AN7
8
Input
Input
Port 7: Port used exclusively for input
Analog input: Input from A/D converter
P80-P87
AN8-AN15
P90-P97
AN16-AN23
PA0
TB0IN0
INT5
8
Input
Input
Input
Input
Input/output
Input
Input
PA1
TB0IN1
INT6
1
Input/output
Input
Input
PA2
TB0OUT
PA3
TB1IN0
INT7
1
Input/output
Output
Input/output
Input
Input
PA4
TB1IN1
INT8
1
Input/output
Input
Input
PA5
TB1OUT
PA6
TB2OUT
1
Input/output
Output
Input/output
Output
Port 8: Port used exclusively for input
Analog input: Input from A/D converter
Port 9: Port used exclusively for input
Analog input: Input from A/D converter
Port A0: Input/output port
16-bit timer 0 input 0: For inputting the count/capture trigger of a 16-bit timer 0
Interrupt request pin 5: Selectable between "H" level, "L" level, rising edge, and falling edge
Input pin with Schmitt trigger
Port A1: Input/output port
16-bit timer 0 input 1: For inputting the count/capture trigger of a 16-bit timer 0
Interrupt request pin 6: Selectable "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port A2: Input/output port
16-bit timer 0 output: 16-bit timer 0 output pin
Port A3: Input/output port
16-bit timer 1 input 0: For inputting the count/capture trigger of a 16-bit timer 1
Interrupt request pin 7: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port A4: Input/output port
16-bit timer 1 input 1: For inputting the count/capture trigger of a 16-bit timer 1
Interrupt request pin 8: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port A5: Input/output port
16-bit timer 1 output: 16-bit timer 1 output pin
Port A6: Input/output port
16-bit timer 2 output: 16-bit timer 2 output pin
PA7
TB3OUT
PB0
TB4OUT
PB1
TB5OUT
PB2
TB6OUT
PB3
TB7OUT
1
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Port A7: Input/output port
16-bit timer 3 output: 16-bit timer 3 output pin
Port B0: Input/output port
16-bit timer 4 output: 16-bit timer 4 output pin
Port B1: Input/output port
16-bit timer 5 output: 16-bit timer 5 output pin
Port B2: Input/output port
16-bit timer 6 output: 16-bit timer 6 output pin
Port B3: Input/output port
16-bit timer 7 output: 16-bit timer 7 output pin
PB4
TB8OUT
PB5
TB9OUT
PB6
TBAIN0
1
Input/output
Output
Input/output
Output
Input/output
Input
PB7
TBAIN1
1
Port B4: Input/output port
16-bit timer 8 output: 16-bit timer 8 output pin
Port B5: Input/output port
16-bit timer 9 output: 16-bit timer 9 output pin
Port B6: Input/output port
16-bit timer A input 0: for inputting the count/capture trigger of a 16-bit timer A
2-phase pulse counter input 0
Port B7: Input/output port
16-bit timer A input 1: For inputting the count/capture trigger of a 16-bit timer A
2-phase pulse counter input 1
8
1
1
1
1
1
1
1
1
1
Input/output
Input
TMP19A64(rev1.1)2-4
TMP19A64F20AXBG
Table 2.2.1 Pin Names and Functions (3 of 6)
Pin name
Number
of pins
Input or
output
Function
PC0
TXD0
1
Input/output
Output
Port C0: Input/output port
Sending serial data 0: Open drain output pin depending on the program used
PC1
RXD0
PC2
SCLK0
CTS0
1
Input/output
Input
Input/output
Input/output
Input
Port C1: Input/output port
Receiving serial data 0
Port C2: Input/output port
Serial clock input/output 0
Ready to send serial data 0 (Clear To Send): Open drain output pin depending on the program
used
PC3
TXD1
1
Input/output
Output
Port C3: Input/output port
Sending serial data 1: Open drain output pin depending on the program used
PC4
RXD1
PC5
SCLK1
CTS1
1
Input/output
Input
Input/output
Input/output
Input
PC6
TXD2
PC7
RXD2
PD0
SCLK2
CTS2
1
PD1
TXD3
PD2
RXD3
PD3
SCLK3
CTS3
1
Port C4: Input/output port
Receiving serial data 1
Port C5: Input/output port
Serial clock input/output 1
Ready to send serial data 1 (Clear To Send): Open drain output pin depending on the program
used
Port C6: Input/output port
Sending serial data 2: Open drain output pin depending on the program used
Port C7: Input/output port
Receiving serial data 2
Port D0: Input/output port
Serial clock input/output 2
Ready to send serial data 2 (Clear To Send): Open drain output pin depending on the program
used
Port D1: Input/output port
Sending serial data 3: Open drain output pin depending on the program used
Port D2: Input/output port
Receiving serial data 3
Port D3: Input/output port
Serial clock input/output 3
Ready to send serial data 3 (Clear To Send): Open drain output pin depending on the program
used
PD4
TXD4
PD5
RXD4
1
PD6
SCLK4
CTS4
PD7
INT9
1
1
1
1
1
1
Input/output
Output
Input/output
Input
Input/output
Input/output
Input
Input/output
Output
Input/output
Input
Input/output
Input/output
Input
Input/output
Output
Input/output
Input
Port D4: Input/output port
Sending serial data 4: Open drain output pin depending on the program used
Port D5: Input/output port
Receiving serial data 4
1
Input/output
Input/output
Input
1
Input/output
Input
Port D6: Input/output port
Serial clock input/output 4
Ready to send serial data 4 (Clear To Send): Open drain output pin depending on the program
used
Port D7: Input/output port
Interrupt request pin 9: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
1
TMP19A64(rev1.1)2-5
TMP19A64F20AXBG
Table 2.2.1 Pin Names and Functions (4 of 6)
Pin name
Number
of pins
Input or
output
Function
PE0
TXD5
1
Input/output
Output
Port E0: Input/output port
Sending serial data 5: Open drain output pin depending on the program used
PE1
RXD5
PE2
SCLK5
CTS5
1
Input/output
Input
Input/output
Input/output
Input
Port E1: Input/output port
Receiving serial data 5
Port E2: Input/output port
Serial clock input/output 5
Ready to send serial data 5 (Clear To Send): Open drain output pin depending on the program
used
PE3-PE5
PE6
INTA
3
1
Input/output
Input/output
Input
PE7
INTB
1
Input/output
Input
PF0
SO
SDA
1
Input/output
Output
Input/output
Ports E3 to E5: Input/output ports that allow input/output to be set in units of bits
Port E6: Input/output port
Interrupt request pin A: Selectable between "H" level, "L" level, rising edge, and falling edge
Input pin with Schmitt trigger
Port E7: Input/output port
Interrupt request pin B: Selectable between "H" level, "L" level, rising edge, and falling edge
Input pin with Schmitt trigger
Port F0: Input/output port
Pin for sending data if the serial bus interface operates in the SIO mode
Pin for sending and receiving data if the serial bus interface operates in the I2C mode
Open drain output pin depending on the program used.
Input with Schmitt trigger
PF1
SI
SCL
1
Input/output
Input
Input/output
PF2
SCK
PF3
DREQ2
1
Input/output
Input/output
Input/output
Input
PF4
DACK2
1
Input/output
Output
PF5
DREQ3
1
Input/output
Input
PF6
DACK3
1
Input/output
Output
Port F6: Input/output port
DMA acknowledge signal 3: Signal showing that DREQ3 has acknowledged a DMA transfer
request
PF7
TBTIN
PG0-PG3
TC0IN-TC3IN
PG4-PG7
TCOU0-TCOUT3
PH0-PH5
TCOU4-TCOUT9
PH6-PH7
PI0
INT0
1
Input/output
Input
Input/output
Input
Input/output
Output
Input/output
Output
Input/output
Input/output
Input
PI1
INT1
1
Input/output
Input
PI2
INT2
1
Input/output
Input
Port F7: Input/output port
32-bit time base timer input: For inputting the count for 32-bit time base timer
Ports G0 to G3: Input/output ports that allow input/output to be set in units of bits
For inputting the capture trigger for 32-bit timer
Ports G4 to G7: Input/output ports that allow input/output to be set in units of bits
Outputting 32-bit timer if the result of a comparison is a match
Ports H0 to H5: Input/output ports that allow input/output to be set in units of bits
Outputting 32-bit timber if the result of a comparison is a match
Ports H6 to H7: Input/output ports that allow input/output to be set in units of bits
Port I0: Input/output port
Interrupt request pin 0: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port I1: Input/output port
Interrupt request pin 1: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port I2: Input/output port
Interrupt request pin 2: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
1
1
4
4
6
2
1
Port F1: Input/output port
Pin for receiving data if the serial bus interface operates in the SIO mode
Pin for inputting and outputting a clock if the serial bus interface operates in the I2C mode
Open drain output pin depending on the program used
Input with Schmitt trigger
Port F2: Input/output port
Pin for inputting and outputting a clock if the serial bus interface operates in the SIO mode
Port F3: Input/output port
DMA request signal 2: For inputting the request to transfer data by DMA from an external I/O
device to DMAC2
Port F4: Input/output port
DMA acknowledge signal 2: Signal showing that DREQ2 has acknowledged a DMA transfer
request
Port F5: Input/output port
DMA request signal 3: For inputting the request to transfer data by DMA from an external I/O
device to DMAC3
TMP19A64(rev1.1)2-6
TMP19A64F20AXBG
Table 2.2.1 Pin Names and Functions (5 of 6)
Pin name
Number
of pins
Input or output
Function
PI3
INT3
1
Input/output
Input
Port I3: Input/output port
Interrupt request pin 3: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
PI4
INT4
1
Input/output
Input
PJ0
DREQ2
1
Input/output
Input
PJ1
DACK2
1
Input/output
Output
PJ2
DREQ3
1
Input/output
Input
Port I4: Input/output port
Interrupt request pin 4: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port J0: Input/output port
DMA request signal 2: For inputting the request to transfer data by DMA from an external I/O
device to DMAC2
Port J1: Input/output port
DMA acknowledge signal 2: Signal showing that DREQ2 has acknowledged a DMA transfer
request
Port J2: Input/output port
DMA request signal 3: For inputting the request to transfer data by DMA from an external I/O
device to DMAC3
PJ3
DACK3
1
Input/output
Output
Port J3: Input/output port
DMA acknowledge signal 3: Signal showing that DREQ3 has acknowledged a DMA transfer
request
PK0-PK7
KEY0-KEY7
8
Input/output
Input
PL0-PL7
PM0-PM7
8
8
Input/output
Input/output
Port K: Input/output port that allows input/output to be set in units of bits
KEY on wake up input 0 to 7 (with pull-up)
With Schmitt trigger
Port L: Input/output port that allows input/output to be set in units of bits
Port M: Input/output port that allows input/output to be set in units of bits
PN0-PN7
PO0
INT0
8
1
Input/output
Input/output
Input
PO1
INT1
1
Input/output
Input
PO2
INT2
1
Input/output
Input
PO3
INT3
1
Input/output
Input
PO4
INT4
1
Input/output
Input
PO5
TXD6
PO6
RXD6
1
Input/output
Output
Input/output
Input
PO7
SCLK6
CTS6
1
Input/output
Input/output
Input
PP0-PP7
TPD0-TPD7
PQ0-PQ7
TPC0-TPC7
TPD0-TPD7
8
Input/output
Output
Input/output
Output
Output
1
8
Port N: Input/output port that allows input/output to be set in units of bits
Port O0: Input/output port
Interrupt request pin 0: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port O1: Input/output port
Interrupt request pin 1: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port O2: Input/output port
Interrupt request pin 2: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port O3: Input/output port
Interrupt request pin 3: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port O4: Input/output port
Interrupt request pin 4: Selectable between "H" level, "L" level, rising edge and falling edge
Input pin with Schmitt trigger
Port O5: Input/output port
Sending serial data 6: Open drain output pin depending on the program used
Port O6: Input/output port
Receiving serial data 6
Port O7: Input/output port
Serial clock input/output 6
Ready to send serial data 6 (Clear To Send): Open drain output pin depending on the program
used
Port P: Input/output port that allows input/output to be set in units of bits
Outputting trace data from the data access address: Signal for DSU-ICE
Port P: Input/output port that allows input/output to be set in units of bits
Outputting trace data from the program counter: Signal for DSU-ICE
Outputting trace data from the data access address: Signal for DSU-ICE
TMP19A64(rev1.1)2-7
TMP19A64F20AXBG
Table 2.2.1 Pin Names and Functions (6 of 6)
Pin name
Number
of pins
Input or output
Function
DCLK
EJE
1
1
Output
Input
Debug clock: Signal for DSU-ICE
EJTAG enable: Signal for DSU-ICE (input with Schmitt trigger and built-in noise filter)
PCST4-0
DINT
5
1
Output
Input
PC trace status: Signal for DSU-ICE
Debug interrupt: Signal for DSU-ICE
(input with Schmitt trigger, pull-up and built-in noise filter)
TOVR/TSTA
TCK
TMS
TDI
TDO
TRST
NMI
1
1
1
1
1
1
1
Output
Input
Input
Input
Output
Input
Input
PLLOFF
RESET
1
1
Input
Input
X1/X2
XT1/XT2
2
2
Input/output
Input/output
Outputting the status of PD data overflow status: Signal for DSU-ICE
Test clock input: Signal for testing JTAG (input with Schmitt trigger and pull-up)
Test mode select input: Signal for testing JTAG (input with Schmitt trigger and pull-up)
Test data input: Signal for testing JTAG (input with Schmitt trigger and pull-up)
Test data output: Signal for testing JTAG
Test reset input: Signal for testing JTAG (input with Schmitt trigger and pull-down)
Nonmaskable interrupt request pin: Pin for requesting an interrupt at the falling edge
Input with Schmitt trigger and built-in noise filter
Fix this pin to the "H (DVCC15) level."(Input with Schmitt trigger)
Reset: Initializing LSI (with pull-up)
Input with Schmitt trigger and built-in noise filter
Pin for connecting to a high-speed oscillator
Pin for connecting to a low-speed oscillator
BUPMD
BRESET
1
1
Input
Input
Backup mode trigger pin: This pin must be set to "L level" in backup mode.
Backup module reset: Initializing the backup module (with pull-up)
Input with Schmitt trigger
BUSMD
1
Input
Pin for setting an external bus mode: This pin functions as a multiplexed bus by sampling the
"H (DVCC15) level" upon the rising of a reset signal. It also functions as a separate bus by
sampling "L" upon the rising of a reset signal. When performing a reset operation, pull it up or
down according to a bus mode to be used.
ENDIAN
1
Input
Pin for setting endian: This pin is used to set a mode. It performs a big-endian operation by
sampling the "H (DVCC15) level" upon the rising of a reset signal, and performs a littleendian operation by sampling "L" upon the rising of a reset signal. When performing a reset
operation, pull it up or down according to the type of endian to be used.
BOOT
1
Input
Pin for setting a single boot mode: This pin goes into single boot mode by sampling "L" upon
the rising of a reset signal. It is used to overwrite internal flash memory. By sampling "H
(DVCC15) level" upon the rising of a reset signal, it performs a normal operation. This pin
should be pulled up under normal operating conditions. Pull it up when resetting.
BW0-1
2
Input
VREFH
1
Input
Fix these pins to BW0="H (DVCC15)" and BW1="H (DVCC15)," respectively.
(Input with Schmitt trigger)
Pin (H) for supplying the A/D converter with a reference power supply
Connect this pin to AVCC31 if the A/D converter is not used.
VREFL
1
Input
AVCC31-32
2
−
AVSS
3
−
A/D converter GND pin (0 V). Connect this pin to GND even if the A/D converter is not used.
TEST1-3
CVCC15
3
1
−
TEST pin: To be fixed to GND.
Pin for supplying oscillators with power: 1.5 V power supply
Input
Pin (L) for supplying the A/D converter with a reference power supply
Connect this pin to AVSS if the A/D converter is not used.
Pin for supplying the A/D converter with a power supply. Connect it to a power supply even if
the A/D converter is not used.
CVSS/BVSS
1
−
GND pin (0 V) for oscillators and backup modules
DVCC15
4
−
Power supply pin: 1.5 V power supply
BVCC
1
−
Pin exclusively for supplying backup modules with power: 3 V power supply
DVCC30-34
8
−
Power supply pin: 3 V power supply
DVSS
11
−
GND pin (0 V)
FVCC15
4
−
Power supply pin: 1.5 V power supply
FVCC3
2
−
Power supply pin: 3 V power supply
TMP19A64(rev1.1)2-8
TMP19A64F20AXBG
Note 1: For BUSMD, ENDIAN and BOOT pins, the state designated for each pin ("H" or "L"
level) must be maintained during one system clock before and after the rising of a
reset signal. The reset pin must always be in a stable state at both "L" and "H" levels.
Note 2: For DREQ2, DACK2, DREQ3 and DACK3, it is necessary to go to the port function
register and to select one port from two groups of ports, PF3 to PF6 and PJ0 to PJ3.
Two ports cannot be operated simultaneously to use the same function.
Likewise, for pins INT0 through INT4, one port must be selected from ports PI0 to PI4
and ports PO0 to PO4.
Table 2.2.2 shows the pin names and power supply pins.
Table 2.2.2 Pin names and power supply pins
Pin name
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
PA
PB
PC
PD
PE
PF
PG
PH
PI
PJ
PK
PL
PM
PN
PO
PP
PQ
Power
supply pin
DVCC33
DVCC33
DVCC33
DVCC33
DVCC33
DVCC33
DVCC33
AVCC32
AVCC32
AVCC31
DVCC32
DVCC32
DVCC32
DVCC32
DVCC32
DVCC32
DVCC32
DVCC32
DVCC30
DVCC33
DVCC34
DVCC34
DVCC34
DVCC34
DVCC34
DVCC31
DVCC31
Pin name
PCST4 to 0
DCLK
EJE
TRST
TDI
TDO
TMS
TCK
DINT
TOV
BUSMD
BOOT
ENDIAN
NMI
BRESET
BUPMD
X1, X2
XT1, XT2
BW0 and 1
PLLOFF
RESET
z 2.7 V ≤ AVCC32 ≤ AVCC31
TMP19A64(rev1.1)2-9
Power
supply pin
DVCC31
DVCC31
DVCC31
DVCC31
DVCC31
DVCC31
DVCC31
DVCC31
DVCC31
DVCC31
DVCC15
DVCC15
DVCC15
DVCC15
BVCC
BVCC
CVCC15
BVCC
DVCC15
DVCC15
DVCC15
TMP19A64F20AXBG
Table 2.2.3 shows the pin numbers and power supply pins.
Table 2.2.3 Pin numbers and power supply pins
Power
supply pin
DVCC15
CVCC15
DVCC30
DVCC31
DVCC32
DVCC33
DVCC34
AVCC31
AVCC32
FVCC15
FVCC3
BVCC
Pin number
D4, D8, E18, N9
C17
K17
H2
M6, U8
F17, U14
D15, F10
B1
F9
G3, G18, J6, L15
L1, U18
E15
Voltage range
1.35 V to 1.65 V
1.35 V to 1.65 V
1.65 V to 3.3 V
1.65 V to 3.3 V
1.65 V to 3.3 V
1.65 V to 3.3 V
1.65 V to 3.3 V
2.7 V to 3.3 V
2.7 V to 3.3 V
1.35 V to 1.65 V
2.7 V to 3.3 V
2.3 V to 3.3 V
(under normal operating conditions)
1.8 V to 3.3 V (in BACKUP mode)
TMP19A64(rev1.1)2-10
TMP19A64F20AXBG
3.
Flash Memory Operation
This section describes the hardware configuration and operation of the flash memory. The feature of this device
is that the internal ROM of TMP19A64C1DXBG is replaced by an internal flash memory. Other configurations
and functions of the device remain the same as with TMP19A64C1DXBG. Please refer to the
TMP19A64C1DXBG data sheet for functions not described in this section.
3.1
Flash Memory
3.1.1
Features
1)
Memory capacity
The TMP19A64F20AXBG device contains two 8M bits (1MB) of flash memory capacity. The
memory area consists of 4 independent memory blocks (128 kB × 16) to enable independent write
access to each block. When the CPU is to access the internal flash memory, 32-bit data bus width
is used.
2)
Write/erase
Write unit:
Erase unit:
Protection unit:
Protection erasure unit:
3)
1 page (128 words) × 4k
Selectable from 128 KB, 512 KB, and 1 MB
Selectable in 512 KB blocks
Selectable in 1 MB blocks
Write/erase time
Write time: 8 sec/2 chip (Typ)
Erase time: 1.6 sec /2 chip (Typ)
Protection bit erase time:
(Note)
4)
2 msec/128 word (Typ.)
100 msec/128 Kbyte (Typ.)
100 msec/2 bit (Typ)
The above values are theoretical values not including data transfer time.
The write time per chip depends on the write method to be used by the user.
Programming method
Two modes are available, i.e., the onboard programming mode to allow programming on the
user's board and the writer mode to program the device using an EPROM writer.
• Onboard programming mode
1) User boot mode
The user's original rewriting method can be supported.
2) Single boot mode
The rewriting method to use serial data transfer
(Toshiba's unique method) can be supported.
• Writer mode
Use of a general purpose EPROM writer is supported.
5)
Rewriting method
The flash memory included in this device is generally compliant with the applicable JEDEC
standards except for some specific functions. Therefore, if the user is currently using an external
flash memory device, it is easy to implement the functions into this device. Furthermore, the user
is not required to build his/her own programs to realize complicated write and erase functions
because such functions are automatically performed using the circuits already built-in the flash
memory chip.
This device is also implemented with a read-security function to inhibit reading flash memory
data from any external writer device. On the other hand, rewrite protection is available only
through command-based software programming; any hardware setting method to apply +12VDC
is not supported. The above described security function is automatically enabled when all the four
area are configured for protection. When the user removes protection, the internal data is
automatically erased before the protection is actually removed.
TMP19A64(rev1.1)-3-1
TMP19A64F20AXBG
JEDEC compliant functions
• Automatic programming
• Automatic chip erase
• Automatic block erase
• Data polling/toggle bit
<Modified> Block protect (only software protection is supported)
<Deleted> Erase resume - suspend function
Automatic multiple block erase (supported to the chip
level)
Block Diagram
Internal address bus
Internal data bus
Internal control bus
ROM controller
Control
Address
Data
Flash Memory
Command
register
Address latch
Data latch
Column decoder/sense amplifier
Flash memory cell
1MB
1MB
Erase block decoder
Fig. 3.1.2.1 Block Diagram of the Flash Memory Section
TMP19A64(rev1.1)-3-2
Row decoder
Control
circuit
(includes
automatic
sequence
control)
Row decoder
3.1.2
Modified, added, or deleted functions
TMP19A64F20AXBG
3.2
Operation Mode
This device has four operation modes including the mode not to use the internal flash memory.
Table 3.2.1.1 Operation Modes
Operation mode
Single chip mode
Operation details
After reset is cleared, it starts up from the internal flash memory.
Normal mode
In this operation mode, two different modes, i.e., the mode to execute user application programs
and the mode to rewrite the flash memory onboard the user’s card, are defined. The former is
referred to as "normal mode" and the latter "user boot mode."
User boot mode
The user can uniquely configure the system to switch between these two modes.
For example, the user can freely design the system such that the normal mode is selected when the
port "00" is set to "1" and the user boot mode is selected when it is set to "0."
The user should prepare a routine as part of the application program to make the decision on the
selection of the modes.
After reset is cleared, it starts up from the internal Boot ROM (Mask ROM). In the Boot ROM, an
algorithm to enable flash memory rewriting on the user’s set through the serial port of this device
is programmed. By connecting to an external host computer through the serial port, the internal
flash memory can be programmed by transferring data in accordance with predefined protocols.
This mode allows use of a general purpose EPROM writer to rewrite the internal flash memory.
Please use a special program adaptor and an EPROM writer that are recommended for use.
Single boot mode
Writer mode
Among the flash memory operation modes listed in the above table, the user boot mode, single boot mode, and
writer mode are programmable modes. These two modes, the User Boot mode and the Single Boot mode, are
referred to as "Onboard Programming" modes where onboard rewriting of internal flash memory can be made
on the user's card.
TMP19A64(rev1.1)-3-3
TMP19A64F20AXBG
Either the single chip, single boot, or writer operation mode can be selected by externally setting the levels of
the BW0, BW1, and BOOT input pins while the device is in the reset state.
Except for the case of the writer mode, the CPU starts operation in the selected operation mode when the reset
condition is removed after the pin levels are set. The writer mode is used with RESET set to "0". Be sure not to
change the levels during operation once the mode is selected. The mode setting method and the mode transition
diagram are shown below:
Table 3.2.1.2 Operation Mode Setting
Input pin
Operation mode
RESET
BW0
BW1
BOOT
Single chip mode
0→1
1
1
1
(2)
Single boot mode
1
0
Writer mode
0→1
*1
1
(3)
*1
*1
*1
(1)
*1: Don't care (No explanation is given in this section regarding condition settings.)
(3)
Reset mode
Writer mode
(1)
(2)
/ RESET = 0
/ RESET = 0
Single chip mode
User
Boot mode
Normal mode
User to set the
switch method
Single
Boot mode
Onboard
Programming mode
The number in the parentheses indicate the mode number in the above table to
show the input pin setting to be made for the corresponding state transition.
Fig. 3.2.1.3 Mode Transition Diagram
3.2.1
Reset Operation
To reset the device, ensure that the power supply voltage is within the operating voltage range, that the
internal oscillator has been stabilized, and that the RESET input is held at "0" for a minimum duration of
12 system clocks (1.8 μs with 54 MHz operation; the "1/8" clock gear mode is applied after reset).
(Note 1) Regarding power-on reset of devices with internal flash memory;
For devices with internal flash memory, it is necessary to apply "0" to the RESET inputs
upon power on for a minimum duration of 60 microseconds regardless of the operating
frequency.
During this period, each protection bit, to be described later, is locked in the state it is
written regardless of the state it ought to be. The original values of protection bits can be
checked by reading the register FLCS <BLPRO 3:0> after the power on reset operation is
normally terminated.
(Note 2) While flash programming is in progress, at least 0.5 microseconds of reset period is
required regardless of the system clock frequency.
TMP19A64(rev1.1)-3-4
TMP19A64F20AXBG
3.2.2
DSU (EJTAG) - PROBE Interface
This interface is used when the DSU probe is used in debugging. This is the dedicated interface for
connection to the DSU probe. Please refer to the operation manual for the DSU probe you are going to use
for details of debugging procedures to use the DSU probe. Here, the function to enable/disable the DSU
probe in the DSU (EJTAG) mode is described.
1)
Security function
This device allows use of an on-board DSU probe for debugging. To facilitate this, the device is
implemented with a security measure to prevent easy reading of the internal flash memory by a third
party other than the authorized user. By enabling the security function, it becomes impossible to read
the internal flash memory from a DSU probe. Use this function together with the security function of
the internal flash memory itself as described later.
2)
DSU probe enable/disable function
This device allows use of on-board DSU probes for debugging operations. To facilitate this, the device
is implemented with the "DSU probe inhibit" function (hereafter referred to as the "DSU inhibit"
function) to prevent easy reading of the internal flash memory by a third party other than the
authorized user. By enabling the DSU inhibit function, use of any DSU probe becomes impossible.
3)
DSU enable (Enables use of DSU probes for debugging)
In order to prevent the DSU inhibit function from being accidentally removed by system runaway, etc.,
the method to cancel the inhibit function requires a double action operation so it is necessary to set
DSU security mode register DSUSEC1<DSUOFF> to "0" and also write the security code
"0x0000_00C5" to the DSU security control register DSUSEC2 to cancel the function. Then,
debugging to use a DSU probe is allowed. While power to the device is still applied, setting
DSUSEC1<DSUOFF> to "1" and writing "0x0000_00C5" to the DSUSEC2 register will enable the
security function again.
Table 3.2.2.1 DSU Security Mode Register
7
DSUSEC1
(0xFFFF_E510)
6
5
Bit Symbol
Read/Write
After power
on reset
Function
4
3
14
13
12
1: DSU disable
0: DSU available
11
10
9
8
18
17
16
26
25
24
R
0
Always reads "0."
23
22
21
20
Bit Symbol
Read/Write
After power
on reset
Function
19
R
0
31
(Note)
0
DSUOFF
R/W
1
Always reads "0."
15
(Note)
1
R
0
Bit Symbol
Read/Write
After power
on reset
Function
Bit Symbol
Read/Write
After power
on reset
Function
2
30
29
28
27
R
0
Always reads "0."
This register can be initialized only by a power on reset. Normal reset inputs cannot reset
the register.
This register must be 32-bit accessed.
TMP19A64(rev1.1)-3-5
TMP19A64F20AXBG
Table 3.2.2.2 DSU Security Control Register
7
DSUSEC2
(0xFFFF_E514)
6
4
3
2
0
Bit Symbol
Read/Write
After reset
Function
DSECODE15 DSECODE14 DSECODE13 DSECODE12 DSECODE11 DSECODE10 DSECODE09 DSECODE08
Bit Symbol
Read/Write
After reset
Function
DSECODE23 DSECODE22 DSECODE21 DSECODE20 DSECODE19 DSECODE18 DSECODE17 DSECODE16
Bit Symbol
Read/Write
After reset
Function
DSECODE31 DSECODE30 DSECODE29 DSECODE28 DSECODE27 DSECODE26 DSECODE25 DSECODE24
W
0
Write "0x0000_00C5."
14
13
12
11
10
9
8
W
0
Write "0x0000_00C5."
23
22
21
20
19
18
17
16
W
0
Write "0x0000_00C5."
31
30
29
28
27
26
W
0
Write "0x0000_00C5."
This register must be 32-bit accessed.
4)
1
DSECODE07 DSECODE06 DSECODE05 DSECODE04 DSECODE03 DSECODE02 DSECODE01 DSECODE00
15
(Note)
5
Bit Symbol
Read/Write
After reset
Function
Example use by the user
An example to use a DSU probe together with this function is shown as follows:
Power ON
Protection bit
set to 1111
N
[DSU-Probe available]
Y
DSU availability decision program
(to be prepared by the user)
External ports
Data, etc.
N
DSU inhibit cleared?
Y
Clear ROM security
(only for internal ROM/flash)
[DSU-Probe disabled]
DSU remains unavailable
Clear DSU inhibit function by writing
to DSUSEC1 and DSUSEC2
[DSU-Probe available]
DSU can be used until power
is turned off.
Fig. 3.2.2.3 Example Use of DSU Inhibit Function
TMP19A64(rev1.1)-3-6
25
24
TMP19A64F20AXBG
3.3
On-board Programming of Flash Memory (Rewrite/Erase)
In on-board programming, the CPU is to execute software commands for rewriting or erasing the flash memory.
The rewrite/erase control program should be prepared by the user beforehand. Because the flash memory
content cannot be read while it is being written or erased, it is necessary to run the rewrite/erase program from
the internal RAM or from an external memory device after shifting to the user boot mode. In this section, flash
memory addresses are represented in virtual addresses unless otherwise noted.
3.4
Flash Memory
Except for some functions, writing and erasing flash memory data are in accordance with the standard JEDEC
commands. In writing or erasing, use the SW command of the CPU to enter commands to the flash memory.
Once the command is entered, the actual write or erase operation is automatically performed internally.
Table 3.4.1.1 Flash Memory Functions
Major functions
Automatic page program
Automatic chip erase
Automatic block erase
Write protect
Security function
Description
Writes data automatically (in 128 word blocks).
Automatically erases the flash memory area one chip at a time (1 MB at a time).
Erases a selected block automatically (128 kB at a time).
The write or erase function can be individually inhibited for each area (of 512 kB). When all
areas are set for protection, the security function is automatically enabled.
A security function is implemented to inhibit reading from the flash memory when the
device is in the writer mode. By setting protection to all the four areas, the security function
is enabled. In order to disable the security function, it is necessary to cancel write protection
when the entire flash memory is automatically erased.
Note that addressing of operation commands is different from the case of standard commands due to the specific
interface arrangements with the CPU as detailed operation of the user boot mode and RAM transfer mode is
described later. Also note that the flash memory is written in 32-bit blocks. So, 32-bit (word) data transfer
commands must be used in writing the flash memory.
TMP19A64(rev1.1)-3-7
TMP19A64F20AXBG
(1) Block configuration
0xBFDF_FFFF
Protection area 3
Chip 1
Protection area 2
Block 7
128 kB
128 words
|
x 256
Block 6
128 kB
128 words
Block 5
128 kB
Block 4
128 kB
Block 3
128 kB
Block 2
128 kB
Block 1
128 kB
0xBFD0_0000
Block 0
128 kB
0xBFCF_FFFF
Block 7
128 kB
Block 6
128 kB
Block 5
128 kB
Block 4
128 kB
Block 3
128 kB
Block 2
128 kB
Block 1
128 kB
Block 0
128 kB
Protection area 1
Chip 0
Protection area 0
0xBFC0_0000
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
128 words
|
x 256
128 words
Fig. 3.4.1.2 Block Configuration of Flash Memory
TMP19A64(rev1.1)-3-8
TMP19A64F20AXBG
(2) Basic operation
Generally speaking, this flash memory device has the following two operation modes:
•
The mode to read memory data (Read mode)
•
The mode to automatically erase or rewrite memory data (Automatic operation)
Transition to the automatic mode is made by executing a command sequence while it is in the memory
read mode. In the automatic operation mode, flash memory data cannot be read and any commands
stored in the flash memory cannot be executed. During automatic operation, be sure not to cause any
exceptions other than debug exceptions and reset while a DSU probe is connected. Any interrupt or
exception generation cannot set the device to the read mode except when a hardware reset is generated.
1)
Read
When data is to be read, the flash memory must be set to the read mode. The flash memory will
be set to the read mode immediately after power is applied, when CPU reset is removed, or when
an automatic operation is normally terminated. In order to return to the read mode from other
modes or after an automatic operation has been abnormally terminated, either the Read/reset
command (a software command to be described later) or a hardware reset is used. The device
must also be in the read mode when any command written on the flash memory is to be executed.
•
Read/reset command and Read command (software reset)
When an automatic operation is abnormally terminated, the flash memory cannot return to the
read mode by itself (When FLCS<RDY/BSY> = 0, data read from the flash memory is
undefined.) In this case, the Read/reset command can be used to return the flash memory to
the read mode. Also, when a command that has not been completely written has to be
canceled, the Read/reset command must be used to return to the read mode. The Read
command is used to return to the read mode after executing the SW command to write the
data "0x0000_00F0" to two arbitrary addresses 0x001x_xxxx and 0x000x_xxxx of the flash
memory.
•
2)
With the Read/reset command, the device is returned to the read mode after completing the
third bus write cycle.
Command write
This flash memory uses the command control method. Commands are executed by executing a
command sequence to the flash memory. The flash memory executes automatic operation
commands according to the address and data combinations applied (refer to Command Sequence).
If it is desired to cancel a command write operation already in progress or when any incorrect
command sequence has been entered, the Read/reset command is to be executed. Then, the flash
memory will terminate the command execution and return to the read mode.
Also, when issuing a command, the address [20:19] must be fixed to either "1" or "0" in order to
enable a decision to select either chip 0 or 1.
While commands are generally comprised of several bus cycles, the operation to apply the SW
command to the flash memory is called "bus write cycle." The bus write cycles are to be in a
specific sequential order and the flash memory will perform an automatic operation when the
sequence of the bus write cycle data and address of a command write operation is in accordance
with a predefined specific sequence. If any bus write cycle does not follow a predefined
command write sequence, the flash memory will terminate the command execution and return to
the read mode. The address [31:21] in each bus write cycle should be the virtual address [31:21]
of command execution. It will be explained later for the address bits [20:8].
TMP19A64(rev1.1)-3-9
TMP19A64F20AXBG
(Note 1) Command sequences are executed from outside the flash memory area.
(Note 2) The interval between bus write cycles for this device must be 15 system clock cycles or
longer. The command sequencer in the flash memory device requires a certain time period to
recognize a bus write cycle. If more than one bus write cycles are executed within this time
period, normal operation cannot be expected. For adjusting the applicable bus write cycle
interval using a software timer to be operated at the operating frequency, use the section 10)
"ID-Read" to check for the appropriateness.
(Note 3) Between the bus write cycles, never use any load command (such as LW, LH, or LB) to the
flash memory or perform a DMA transmission by specifying the flash area as the source
address. Also, don't execute a Jump command to the flash memory. While a command
sequence is being executed, don't generate any interrupt such as maskable interrupts (except
debug exceptions when a DSU probe is connected).
If such an operation is made, it can result in an unexpected read access to the flash memory
and the command sequencer may not be able to correctly recognize the command. While it
could cause an abnormal termination of the command sequence, it is also possible that the
written command is incorrectly recognized.
(Note 4) The SYNC command must be executed immediately after the SW command for each bus
write cycle.
(Note 5) For the command sequencer to recognize a command, the device must be in the read mode
prior to executing the command. Be sure to check before the first bus write cycle that the
FLCS[0] RDY/BSY bit is set to "1." It is recommended to subsequently execute a Read
command.
(Note 6) Upon issuing a command, if any address or data is incorrectly written, be sure to perform a
system reset operation or issue a reset command (for Chip 0 and Chip 1) to return to the read
mode again.
3)
Reset
Hardware reset
The flash memory has a reset input as the memory block and it is connected to the CPU reset
signal. Therefore, when the RESET input pin of this device is set to VIL or when the CPU is reset
due to any overflow of the watch dog timer, the flash memory will return to the read mode
terminating any automatic operation that may be in progress. The CPU reset is also used in
returning to the read mode when an automatic operation is abnormally terminated or when any
mode set by a command is to be canceled. It should also be noted that applying a hardware reset
during an automatic operation can result in incorrect rewriting of data. In such a case, be sure to
perform the rewriting again.
Refer to Section 3.1 "Reset Operation" for CPU reset operations. After a given reset input, the
CPU will read the reset vector data from the flash memory and starts operation after the reset is
removed.
4)
Automatic Page Programming
Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell
cannot be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is necessary to
perform an erase operation.
The automatic page programming function of this device writes data in 128 word blocks. A 128
word block is defined by a same [31:9] address and it starts from the address [8:0] = 0 and ends at
the address [8:0] = 0x1FF. This programming unit is hereafter referred to as a "page."
TMP19A64(rev1.1)-3-10
TMP19A64F20AXBG
Writing to data cells is automatically performed by an internal sequencer and no external control
by the CPU is required. The state of automatic page programming (whether it is in writing
operation or not) can be checked by the FLCS <RDY/BSY> register.
Also, any new command sequence is not accepted while it is in the automatic page programming
mode. If it is desired to interrupt the automatic page programming, use the hardware reset
function. If the operation is stopped by a hardware reset operation, it is necessary to once erase
the page and then perform the automatic page programming again because writing to the page has
not been normally terminated.
The automatic page programming operation is allowed only once for a page already erased. No
programming can be performed twice or more times irrespective of the data cell value whether it
is "1" or "0." Note that rewriting to a page that has been once written requires execution of the
automatic block erase or automatic chip erase command before executing the automatic page
programming command again. Note that an attempt to rewrite a page two or more times without
erasing the content can cause damages to the device.
No automatic verify operation is performed internally to the device. So, be sure to read the data
programmed to confirm that it has been correctly written.
The automatic page programming operation starts when the fourth bus write cycle of the
command cycle is completed. On and after the fifth bus write cycle, data will be written
sequentially starting from the next address of the address specified in the fourth bus write cycle
(in the fourth bus write cycle, the page top address will be command written) (32 bits of data is
input at a time). Be sure to use the SW command in writing commands on and after the fourth bus
cycle. In this, any SW command shall not be placed across word boundary. On and after the fifth
bus write cycle, data is command written to the same page area. Even if it is desired to write the
page only partially, it is required to perform the automatic page programming for the entire page.
In this case, the address input for the fourth bus write cycle shall be set to the top address of the
page. Be sure to perform command write operation with the input data set to "1" for the data cells
not to be set to "0." For example, if the top address of a page is not to be written, set the input data
of the fourth bus write cycle to 0xFFFFFFFF to command write the data.
Once the fourth bus cycle is executed, it is in the automatic programming operation. This
condition can be checked by monitoring the register bit FLCS <RDY/BSY>. Any new command
sequence is not accepted while it is in automatic page programming mode. If it is desired to stop
operation, use the hardware reset function. Be careful in doing so because data cannot be written
normally if the operation is interrupted. When a single page has been command written normally
terminating the automatic page writing process, the FLCS <RDY/BSY> bit is set to "1" and it
returns to the read mode.
When multiple pages are to be written, it is necessary to execute the page programming
command for each page because the number of pages to be written by a single execution of the
automatic page program command is limited to only one page. It is not allowed for automatic
page programming to process input data across pages.
Data cannot be written to a protected block. When automatic programming is finished, it
automatically returns to the read mode. This condition can be checked by monitoring FLCS
<RDY/BSY>. If automatic programming has failed, the flash memory is locked in the mode and
will not return to the read mode. For returning to the read mode, it is necessary to use the reset
command or hardware reset to reset the flash memory or the device. In this case, while writing to
the address has failed, it is recommended not to use the device or not to use the block that
includes the failed address.
Note:
Software reset becomes ineffective in bus write cycles on and after the
fourth bus write cycle of the automatic page programming command.
TMP19A64(rev1.1)-3-11
TMP19A64F20AXBG
5)
Automatic chip erase (1MB at a time)
The automatic chip erase operation starts when the sixth bus write cycle of the command cycle is
completed.
This condition can be checked by monitoring FLCS <RDY/BSY>. While no automatic verify
operation is performed internally to the device, be sure to read the data to confirm that data has
been correctly erased. Any new command sequence is not accepted while it is in an automatic
chip erase operation. If it is desired to stop operation, use the hardware reset function. If the
operation is forced to stop, it is necessary to perform the automatic chip erase operation again
because the data erasing operation has not been normally terminated.
Also, any protected blocks cannot be erased. If all the blocks are protected, the automatic chip
erase operation will not be performed and it returns to the read mode after completing the sixth
bus read cycle of the command sequence. When an automatic chip erase operation is normally
terminated, it automatically returns to the read mode. If an automatic chip erase operation has
failed, the flash memory is locked in the mode and will not return to the read mode.
For returning to the read mode, it is necessary to use the reset command or hardware reset to reset
the flash memory or the device. In this case, the failed block cannot be detected. It is
recommended not to use the device anymore or to identify the failed block by using the block
erase function for not to use the identified block anymore.
6)
Automatic block erase (128 kB at a time)
The automatic block erase operation starts when the sixth bus write cycle of the command cycle
is completed.
This status of the automatic block erase operation can be checked by monitoring FLCS
<RDY/BSY>. While no automatic verify operation is performed internally to the device, be sure
to read the data to confirm that data has been correctly erased. Any new command sequence is not
accepted while it is in an automatic block erase operation. If it is desired to stop operation, use the
hardware reset function. In this case, it is necessary to perform the automatic block erase
operation again because the data erasing operation has not been normally terminated.
Note that any block in the protected area is not erased. It returns to the read mode upon
completing the last bus cycle of the command sequence. If an automatic block erase operation has
failed, the flash memory is locked in the mode and will not return to the read mode. In this case,
use the reset command or hardware reset to reset the flash memory or the device.
Note:
7)
Commands can be accepted only by Chip 0. Even if automatic protection bit
programming or erasure is commanded to Chip 1, it will not result in any
setting or clearing of the protection.
Automatic programming of protection bits (for each 512 kB block)
This device is implemented with four protection bits. The protection bits can be individually set in
the automatic programming. The applicable protection bit is specified in the seventh bus write
cycle. By automatically programming the protection bits, write and/or erase functions can be
inhibited individually for each protection area. The protection status of each area can be checked
by FLCS <PROTECT3:0> to be described later. Any new command sequence is not accepted
while automatic programming is in progress to program the protection bits. If it is desired to stop
the programming operation, use the hardware reset function. In this case, it is necessary to
perform the programming operation again because the protection bits may not have been correctly
programmed. If all the protection bits have been programmed, the flash memory cannot be read
TMP19A64(rev1.1)-3-12
TMP19A64F20AXBG
from any area outside the flash memory such as the internal RAM. In this condition, the FLCS
<PROTECT3:0> register is set to "0xF" (secure state). After this, no command writing can be
performed.
Note:
Commands can be accepted only by Chip 0. Even if automatic protection bit
programming or erasure is commanded to Chip 1, it will not result in any
setting or clearing of the protection.
Note:
Software reset is ineffective in the seventh bus write cycle of the automatic
protection bit programming command. The FLCS <RDY/BSY> bit turns to "0"
after entering the seventh bus write cycle.
8)
Automatic erasing of protection bits
Different results will be obtained when the automatic protection bit erase command is executed
depending on the status of the protection bits. It depends on the status of FLCS<PROTECT3:0>
before the command execution whether it is set to "0 x F" or to any other values. Be sure to check
the value of FLCS<PROTECT3:0> before executing the automatic protection bit erase command.
• When FLCS<PROTECT3:0> is set to "0 x F" (all the protection bits are programmed):
When the automatic protection bit erase command is command written, the flash memory is
automatically initialized within the device. When the seventh bus write cycle is completed, the
entire area of the flash memory data cells is erased and then all the protection bits are erased. This
operation can be checked by monitoring FLCS <RDY/BSY>. If the automatic operation to erase
protection bits is normally terminated, FLCS<PROTECT3:0> will be set to "0x0." While no
automatic verify operation is performed internally to the device, be sure to read the data to
confirm that it has been correctly erased. For returning to the read mode while the automatic
operation after the seventh bus cycle is in progress, it is necessary to use the hardware reset to
reset the flash memory or the device. If this is done, it is necessary to check the status of
protection bits by FLCS<PROTECT3:0> after retuning to the read mode and perform either the
automatic protection bit erase, automatic chip erase, or automatic block erase operation, as
appropriate.
• When FLCS<PROTECT3:0>is other than "0 x F" (not all the protection bits are programmed):
The protection condition can be canceled by the automatic protection bit erase operation. With
this device, protection bits can be erased handling two bits at a time. The target bits are specified
in the seventh bus write cycle and when the command is completed, the device is in a condition
the two bits are erased. The protection status of each block can be checked by
FLCS<PROTECT3:0> to be described later. This status of the programming operation for
automatic protection bits can be checked by monitoring FLCS <RDY/BSY>. When the automatic
operation to erase protection bits is normally terminated, the two protection bits of
FLCS<PROTECT3:0> selected for erasure are set to "0."
In any case, any new command sequence is not accepted while it is in an automatic operation to
erase option bits. If it is desired to stop the operation, use the hardware reset function. When the
automatic operation to erase option bits is normally terminated, it returns to the read mode.
TMP19A64(rev1.1)-3-13
TMP19A64F20AXBG
9)
Flash control/ status register
This resister is used to monitor the status of the flash memory and to indicate the block protection
status.
Table 3.4.1.3 Flash Control Register
7
FLCS
Bit Symbol
(0xFFFF_E520) Read/Write
After power
on reset
Function
Bit Symbol
Read/Write
After power
on reset
Function
Bit Symbol
Read/Write
After power
on reset
Function
Bit Symbol
Read/Write
After power
on reset
Function
6
5
4
PROTECT3 PROTECT2 PROTECT1 PROTECT0
R
0
0
0
0
3
2
1
0
R
0
ROMTYPE
R
0
PRGB
R/W
0
RDY/BSY
R
1
ROM ID bit Programming Ready/Busy
Protection area setting (for each 512 kB)
0000: No blocks are protected
xxx1: Block 0 is protected
xx1x: Block 1 is protected
x1xx: Block 2 is protected
1xxx: Block 3 is protected
bit
0:Flash
1:MROM
15
14
13
12
0
0
0
23
22
0
0: Already
issued
1: Issue
0: In
operation
1: Operation
terminated
11
10
9
8
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
R
R
R
Bit 0: Ready/Busy flag bit
The RDY/BSY output is provided as a means to monitor the status of automatic operation. This bit is a
function bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs
"0" to indicate that it is busy. When the automatic operation is terminated, it returns to the ready state and
outputs "1" to accept the next command. If the automatic operation has failed, this bit maintains the "0"
output. Returns to "1" upon power on.
(Note)
Be sure to confirm the ready status whenever a command is to be issued.
Issuing a command while the device is busy may result in a situation where further command inputs
are rejected in addition to the fact that the command cannot be transferred correctly. In such a case,
restore the system by using system reset or a reset command.
Bit 1: Programming bit
This bit notifies the flash interface that a command is to be issued to the flash memory.
Be sure to set this bit to "1" whenever a command is to be issued to the internal flash memory. Also, when all
commands have been issued, set this bit to "0" after confirming that the <RDY/BSY> bit is set to "1."
Bit 2: ROM type identification bit
This bit is read after reset to identify whether the ROM is a flash ROM or a mask ROM.
Flash ROM: "0"
Mask ROM: "1"
Bits [7:4]: Protection bits (x: can be set to any combination of areas)
Each of the protection bits (4 bits) represents the protection status of the corresponding area. When a bit is
set to "1," it indicates that the area corresponding to the bit is protected. When the area is protected, data
cannot be written into it.
TMP19A64(rev1.1)-3-14
TMP19A64F20AXBG
10) ID-Read
Using the ID-Read command, you can obtain the type and other information on the flash memory
contained in the device. The data to be loaded will be different depending on the write address to
the flash [15:14] of the fourth and subsequent bus write cycles (any input data other than 0xF0
can be used). On and after the fourth bus write cycle, when an LW command (to read an arbitrary
flash memory area) is executed after an SW command, the ID value will be loaded (execute a
SYNC command immediately after the LW command). Once the fourth bus write cycle of an IDRead command has passed, the device will not automatically return to the read mode. In this
condition, the set of the fourth bus write cycle and LW/SYNC commands can be repetitively
executed. For returning to the read mode, reset the system or use the Read or Read/reset
command.
The ID-Read command can be used when it is necessary for an application to identify whether the
device in the product has an internal flash memory or an internal ROM. This is effective because
a mask ROM doesn't have a command sequencer so it interprets any ID-Read command written
as simply a pair of SW and LW commands applied to the mask ROM. If an ID-Read command is
to be executed on a device with an internal mask ROM, it is necessary to select an address at
which the return value to a normal LW command is different from the ID-Read execution result
(ID) from a device with an internal flash memory, also taking into account any applicable security
conditions.
Note:
Setting is required when a command is to be issued to Chip 0 or Chip 1.
Refer to (4) List of Command Sequences.
TMP19A64(rev1.1)-3-15
TMP19A64F20AXBG
(4) List of Command Sequences
This product is implemented with two 1 MB flash ROM chips (1 MB x 2). It is necessary to identify
the target chip (0 or 1) before executing a command. This identification is made by the address bit [20].
Table 3.4.1.2 Flash Memory Access from the Internal CPU
Flash Chip 0 Command Sequence: Addr. [20] = 0
Command
sequence
Read
First bus
cycle
Second bus
cycle
Addr.
Data
0xXX
0xF0
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
Read/reset
ID-Read
Automatic page
programming (note)
Automatic chip
erase
Auto
Block erase (note)
Protection bit
programming
Protection bit
erase
Addr.
Third bus
cycle
Addr.
Fourth bus
cycle
Addr.
Fifth bus
cycle
Addr.
Sixth bus
cycle
Addr.
Seventh bus
cycle
Addr.
Data
Data
Data
Data
Data
Data
RA
RD
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0x55XX
0xF0
0x55XX
0x90
0x55XX
0xA0
0x55XX
0x80
0x55XX
0x80
0x55XX
0x9A
0x55XX
0x6A
RA
RD
IA
0x00
PA
PD0
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0xXX
ID
PA
PD1
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
PA
PD2
0x55XX
0x10
BA
0x30
0x55XX
0x9A
0x55XX
0x6A
PA
PD3
−
−
−
−
PBA
0x9A
PBA
0x6A
−
−
Flash Chip 1 Command Sequence: Addr. [20] = 1
Command
sequence
Read
Read/reset
ID-Read
Automatic page
programming (note)
Automatic chip
erase
Auto
Block erase (note)
First bus
cycle
Second bus
cycle
Third bus
cycle
Fourth bus
cycle
Fifth bus
cycle
Sixth bus
cycle
Seventh bus
cycle
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Data
0xXX
0xF0
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
0x55XX
0xAA
Data
Data
Data
Data
Data
Data
RA
RD
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0xAAXX
0x55
0x55XX
0xF0
0x55XX
0x90
0x55XX
0xA0
0x55XX
0x80
0x55XX
0x80
RA
RD
IA
0x00
PA
PD0
0x55XX
0xAA
0x55XX
0xAA
•
RA:
Read address
RD: Read data
•
IA:
ID address
ID: ID data
•
PA:
PD:
Program page address (specified in Addr.[20:9])
Program data (32-bit data)
0xXX
ID
PA
PD1
0xAAXX
0x55
0xAAXX
0x55
−
−
PA
PD2
0x55XX
0x10
BA
0x30
After the fourth bus cycle, enter data in the order of the address for a page.
•
BA:
Block address
PBA: Protection bit address
TMP19A64(rev1.1)-3-16
PA
PD3
−
−
−
−
TMP19A64F20AXBG
(Note)
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 5)
To select the target memory access area (block), set either "0" or "1" to the address bits [20:19] in the first bus
cycle.
Always set "0" to the address bits [1:0] in the entire bus cycle. (Setting values to bits [7:2] are undefined.)
Bus cycles are "bus write cycles" except for the second bus cycle of the Read command, the fourth bus cycle of
the Read/reset command, and the fifth bus cycle of the ID-Read command. Bus write cycles are executed by SW
commands. Use "Data" in the table for the rt register [7:0] of SW commands. The address [31:16] in each bus write
cycle should be the target flash memory address [31:16] of the command sequence. Use "Addr." in the table for the
address [15:0].
In executing the bus write cycles, the interval between each bus write cycle shall be 15 system clocks or more.
The "Sync command" must be executed immediately after completing each bus write cycle.
Execute the "Sync command" immediately following the "LW command" after the fourth bus write cycle of the IDRead command.
(5) Address bit configuration for bus write cycles
Table 3.4.1.3 Address Bit Configuration for Bus Write Cycles
Address
Normal
commands
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
[31:21]
[20]
[19]
[18:17]
[16]
[15]
[14]
[13]
[12:9]
[8]
[7:0]
Chip
selection
Area
selection
Normal bus write cycle address configuration
Flash area
Block erase Flash area
"0" is recommended
Addr [1:0]=0 (fixed),
Others: 0
(recommended)
Command
BA: Block address (Set the sixth bus write cycle address for block erase operation)
Chip
selection
Auto page
programming
Flash area
Chip
selection
ID-READ
Flash area
Chip
selection
Area
selection
Block
selection
Addr[1:0]=0 (fixed), Others: 0 (recommended)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
Area
selection
Block
selection
Page selection
Addr[1:0]=0 (fixed), Others: 0
(recommended)
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
"0" is recommended
ID address
Addr[1:0]=0 (fixed), Others: 0 (recommended)
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming)
Protection
bit
programming
Flash area
Fixed to
"0"
"0" is recommended
Protection bit write
00: Area 0
01: Area 1
10: Areak 2
11: Area 3
Addr[1:0]=0 (fixed), Others: 0 (recommended)
PBA: Protection bit address (Set the seventh bus write cycle address for protection bit erasure)
Protection
bit erase
Flash area
Fixed to
"0"
"0" is recommended
Erase protection
for
0: Area 0, 1
1: Area 2, 3
Addr[1:0]=0 (fixed), Others: 0 (recommended)
(Note)
Table 3.4.1.2 "Flash Memory Access from the Internal CPU" can also be used.
(Note)
Address setting can be performed according to the "Normal bus write cycle address
configuration" from the first bus cycle.
(Note)
""0" is recommended" can be changed as necessary.
TMP19A64(rev1.1)-3-17
TMP19A64F20AXBG
Table 3.4.1.4 Block Erase Address Table
Select Area
Chip
Area
Area 3
Chip 1
Area 2
Area 1
Chip 0
Area 0
Set Address[20:17]
Address Area
BA
[20]
[19]
[18]
[17]
Flash Memory Address
When applied to the
projected area
Size
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0xBFDE_0000-0xBFDF_FFFF
0xBFDC_0000-0xBFDD_FFFF
0xBFDA_0000-0xBFDB_FFFF
0xBFD8_0000-0xBFD9_FFFF
0xBFD6_0000-0xBFD7_FFFF
0xBFD4_0000-0xBFD5_FFFF
0xBFD2_0000-0xBFD3_FFFF
0xBFD0_0000-0xBFD1_FFFF
0xBFCE_0000-0xBFCF_FFFF
0xBFCC_0000-0xBFCD_FFFF
0xBFCA_0000-0xBFCB_FFFF
0xBFC8_0000-0xBFC9_FFFF
0xBFC6_0000-0xBFC7_FFFF
0xBFC4_0000-0xBFC5_FFFF
0xBFC2_0000-0xBFC3_FFFF
0xBFC0_0000-0xBFC1_FFFF
0x001E_0000-0x001F_FFFF
0x001C_0000-0x001D_FFFF
0x001A_0000-0x001B_FFFF
0x0018_0000-0x0019_FFFF
0x0016_0000-0x0017_FFFF
0x0014_0000-0x0015_FFFF
0x0012_0000-0x0013_FFFF
0x0010_0000-0x0011_FFFF
0x000E_0000-0x000F_FFFF
0x000C_0000-0x000D_FFFF
0x000A_0000-0x000B_FFFF
0x0008_0000-0x0009_FFFF
0x0006_0000-0x0007_FFFF
0x0004_0000-0x0005_FFFF
0x0002_0000-0x0003_FFFF
0x0000_0000-0x0001_FFFF
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
128 KB
Table 3.4.1.5 Protection Bit Programming Address Table
PBA
The seventh bus write cycle address [15:14]
Address [15]
Address [14]
Area 0
Area 1
Area 2
Area 3
0
0
1
1
0
1
0
1
Table 3.4.1.6 Protection Bit Erase Address Table
PBA
The seventh bus write cycle address [15:14]
Address [15]
Address [14]
Area 0
Area 1
Area 2
Area 3
0
0
1
1
X
X
X
X
The protection bit erase command will erase bits 0 and 1 together.
The bits 2 and 3 are also erased together.
Table 3.4.1.7 The ID-Read command's fourth bus write cycle ID address (IA) and
the data to be read by the following LW command (ID)
IA [15:14]
ID [7: 0]
Code
00b
01b
11b
10b
0x98
0x5A
0x06
Reserved
Manufacturer code
Device code
Macro code
---
TMP19A64(rev1.1)-3-18
TMP19A64F20AXBG
4.
Electrical Characteristics
The letter x in equations presented in this chapter represents the cycle period of the fsys clock
selected through the programming of the SYSCR1.SYSCK bit. The fsys clock may be derived from
either the high-speed or low-speed crystal oscillator. The programming of the clock gear function
also affects the fsys frequency. All relevant values in this chapter are calculated with the high-speed
(fc) system clock (SYSCR1.SYSCK = 0) and a clock gear factor of 1/fc (SYSCR1.GEAR[2:0] =
000).
4.1
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
Vcc2 (Core)
− 0.3 to 3.0
Vcc3(I/O)
− 0.3 to 3.9
AVCC(A/D)
− 0.3 to 3.9
BVCC
− 0.3 to 3.9
VIN
Supply voltage
Rating
− 0.3 to VCC+0.3
Unit
V
V
Low-level
Per pin
output
Total
current
High-level
Per pin
output
Total
current
Power dissipation (Ta = 85°C)
IOL
5
ΣIOL
IOH
50
-5
ΣIOH
50
PD
600
mW
Soldering temperature (10 s)
TSOLDER
260
℃
Storage temperature
TSTG
−40 to 125
℃
-20 to 85
℃
Operating
temperature
Except during flash
W/E
TOPR
During flash W/E
Write/erase cycles
NEW
0 to 70
100
mA
cycle
VCC15=DVCC15=CVCC15=FVCC15、VCC3=DVCC3n(n=0 to 4)、AVCC=AVCC3m
(m=1 to 2)
Note:
VSS=DVSS*=AVSS*=CVSS=FVSS
The Absolute Maximum Rating is a rating that must never be exceeded, even for an instant. Not a
single Absolute Maximum Rating value can be exceeded. If any Absolute Maximum Rating value
is exceeded, the product may be damaged or weakened, or damage or combustion may cause
personal injury. Always be sure to design your application devices so the Absolute Maximum
Rating is never exceeded.
TMP19A64(rev1.1)4-1
TMP19A64F20AXBG
4.2
DC Electrical Characteristics (1/3)
Ta=-20 to 85℃
Parameter
Supply voltage
CVCC15=DVCC15
CVSS=DVSS=0V
Symbol
DVCC15
BVCC
DVCC3n
(n=0 to 4)
P7 to P9
(Used as a port)
VIL1
Normal port
VIL2
Conditions
Min
1.35
1.65
fsys = 16kHz to 54MHz
1.8
3.3
1.65
3.3
fsys = 4 to 54MHz
0.3AVCC31
0.3AVCC32
2.7V≦AVCC32≦AVCC31≦3.3V
Low-level input voltage
1.65V≦DVCC3n≦3.3V(n=0 to 4)
1.8V≦BVCC≦3.3V
0.3DVCC3n
0.3BVCC
−0.3
0.2DVCC3n
0.2BVCC
VIL3
1.35V≦DVCC15≦1.65V
0.1DVCC15
X1
VIL4
1.35V≦CVCC15≦1.65V
0.1CVCC
XT1
VIL5
1.8V≦BVCC≦3.3V
0.1CVCC
BVCC :Normal mode 2.3V to 3.3V,BACKUP mode 1.8V to 3.3V
TMP19A64(rev1.1)4-2
Unit
V
1.8V≦BVCC≦3.3V
Note1:
Max
fosc = 8 to 13.5MHz
fs = 30kHz to 34kHz
fsys = 30kHz to 54MHz
PLLOFF="1"
1.65V≦DVCC3n≦3.3V (n=0 to 4)
Schmitt-Triggered port
Typ
(Note 1)
V
TMP19A64F20AXBG
Ta=-20 to 85℃
Parameter
Symbol
Conditions
Min.
Typ
Max.
Unit
DVCC3n+0.
3
BVCC+0.3
DVCC15+0.
2
CVCC+0.2
V
(Note 1)
High-level input voltage
P7 to P9
(Used as a port)
Normal port
VIH1
VIH2
2.7V≦AVCC32≦AVCC31≦3.3V
1.65V≦DVCC3n≦3.3V(n=0 to 4)
1.8V≦BVCC≦3.3V
Schmitt-Triggered
port
VIH3
0.7AVCC31
0.7AVCC32
0.7DVCC3n
0.7BVCC
1.65V≦DVCC3n≦3.3V(n=0 to 4)
1.8V≦BVCC≦3.3V
0.8DVCC3n
0.8BVCC
1.35V≦DVCC15≦1.65V
0.9DVCC15
X1
VIH4
1.35V≦CVCC≦1.65V
0.9CVCC
XT2
VIH4
1.8V≦BVCC≦3.3V
0.9BVCC
IOL = 2mA
Low-level output voltage
VOL
IOL = 500μA
IOH = −2mA
High-level output voltage
Note 1:
VOH
IOH = −500μA
0.4
0.2DVCC3n
≦0.4
DVCC3n≧2.7V
DVCC3n
<
2.7V
DVCC3n
≧
2.7V
DVCC3n
<
2.7V
2.4
0.8DVCC3n
Ta = 25°C, DVCC15=1.5V,DVCC3n =3.0V, BVCC=3.0V, AVCC3m=3.3V, unless otherwise noted
TMP19A64(rev1.1)4-3
V
TMP19A64F20AXBG
4.3
DC Electrical Characteristics (2/3)
Ta=-20 to 85℃
Parameter
Symbol
Conditions
Min.
Typ
Max.
Unit
(Note 1)
0.0 ≦ VIN ≦ DVCC15
0.0 ≦ VIN ≦ BVCC
Input leakage current
ILI
0.0 ≦ VIN ≦ DVCC3n(n=0 to 4)
0.0 ≦ VIN ≦ AVCC31
0.02
±5
0.0 ≦ VIN ≦ AVCC32
0.2 ≦ VIN ≦ DVCC15−0.2
Output leakage current
ILO
μA
0.2 ≦ VIN ≦ BVCC−0.2
0.2 ≦ VIN ≦ DVCC3n−0.2(n=0 to 4)
0.05
±10
0.2 ≦ VIN ≦ AVCC31−0.2
0.2 ≦ VIN ≦ AVCC32−0.2
VSTOP
(DVCC15)
VSTOP1
Power-down voltage
(STOP mode RAM backup)
(BVCC)
VSTOP2
VIL1 = 0.3AVCC31,32
(AVCC3)
VIH1 = 0.7AVCC31,32
VSTOP3
VIL2 = 0.3DVCC3n, VIL3 = 0.1DVCC3n
VIH2 = 0.7DVCC3n, VIH3 = 0.9DVCC3n
(DVCC3)
RRST
DVCC15 = 1.5V ± 0.15V
Schmitt-Triggered port
VTH
1.65V≦DVCC3n≦3.3V(n=0 to 4)
1.8V≦BVCC≦3.3V
1.35V≦DVCC15≦1.65V
PKH
DVCC3n = 1.65V to 3.3V(n=0 to 4)
DVCC15 = 1.35V to 1.65V
BVCC = 1.8V to 3.3V
CIO
Fc = 1MHz
Pin capacitance
(Except power supply pins)
Note 1:
1.65
1.8
3.3
2.7
3.6
1.65
3.3
V
(n=0 to 4)
Pull-up resister at Reset
Programmable pull-up/
pull-down resistor
1.35
20
50
0.3
0.6
20
50
150
V
150
kΩ
10
pF
Ta = 25°C, DVCC15=1.5V,DVCC3n =3.0V, BVCC=3.0V, AVCC3m=3.3V, unless otherwise noted
TMP19A64(rev1.1)4-4
kΩ
TMP19A64F20AXBG
4.4
DC Electrical Characteristics (3/3)
DVCC15=CVCC15=FVCC15=1.35V to 1.65V, DVCC3n=FVCC3=2.7V to 3.3V,
AVCC3m=2.7V to 3.3V, BVCC=1.8V to 3.3V
Ta=-20 to 85℃
(n=0 to 4、m=1,2)
Parameter
Symbol
Max.
Unit
50
18
14
60
28
23
mA
Fsys = 32.768kHz
(fs = 32.768kHz)
300
970
μA
Fsys = 32.768kHz
(fs = 32.768kHz)
100
950
μA
90
900
μA
3
5
μA
Conditions
Min.
Typ.
(Note 1)
NORMAL(Note 2): Gear = 1/1
Fsys = 54 MHz
(fosc = 13.5 MHz, PLLOFF="DVCC15")
IDLE(Doze)
IDLE(Halt)
SLOW
SLEEP
STOP
BACKUP
Note 1:
ICC
DVCC15 = CVCC15 =1.35 to 1.65V
BVCC = 1.8 to 3.3V
DVCC3n = 1.65 to 3.3V
AVCC3m = 2.7 to 3.3V
BVCC = 1.8 to 3.3V
Ta = 25°C, DVCC15=1.5V,DVCC3n =3.0V, BVCC=3.0V, AVCC3m=3.3V, unless otherwise noted
Note 2: Measured with the CPU dhrystone operating, all I/O peripherals channel on, and 16-bit
external bus operated with 4 system clocks.
Note 3: The supply current flowing through the DVCC15、BVCC、DVCC3n、CVCC15 and AVCC3m
pins is included in the digital supply current parameter (ICC).
TMP19A64(rev1.1)4-5
TMP19A64F20AXBG
4.5
10-bit ADC Electrical Characteristics
DVCC15=CVCC15=1.35V to 1.65V, AVCC3m=2.7V to 3.3V,
AVSS=DVSS, Ta=-20 to 85℃
Parameter
Symbol
Analog reference voltage (+)
VREFH
Analog reference voltage (−)
VREFL
VAIN
Analog input voltage
A/D conversion
Analog supply
current
IREF
Non-A/D
conversion
Analog input capacitance
Analog input impedance
INL error
Conditions
Typ
Max
2.7
AVCC3m−0.3
AVSS
VREFL
AVCC
AVSS
3.3
AVCC3m+0.3
AVSS+0.2
VREFH
Unit
V
V
V
AVCC3m
= VREFH = 3.0V ± 0.3V
DVSS = AVSS = VREFL
1.15
1.8
mA
AVCC3m
= VREFH = 2.7 to 3.3V
DVSS = AVSS = VREFL
0.1
10.0
μA
1.0
2.0
2.0
3.5
pF
kΩ
±2
3
LSB
±1
3
LSB
±2
3
LSB
±2
4
LSB
⎯
⎯
⎯
Min
AVCC3m
= VREFH = 3.0 V ±0.3 V
DVSS = AVSS = VREFL
DNL error
⎯
AIN resistance < 1.3kΩ
AIN load capacitance < 20 pF
AVCCm load capacitance
Offset error
⎯
≥ 10 μF
VREFH load capacitance
≥ 10 μF
Gain error
⎯
Conversion time ≥ 7.85 μs
Note 1: 1LSB = (VREFH − VREFL)/1024[V]
Note 2: The supply current flowing through the AVCC3m pin is included in the digital supply current
parameter (ICC).
TMP19A64(rev1.1)4-6
TMP19A64F20AXBG
4.6
AC Electrical Characteristics
[1]Separate Bus mode
(1)DVCC15=CVCC15=FVCC15=1.35V to 1.65V, DVCC3n=FVCC3=2.3V to 3.3V
SYSCR3<ALESEL> = “0”, 2 programmed wait state
Equation
No.
Parameter
Symbol
Min
1
54 MHz (fsys)
System clock period (x)
tSYS
18.5
Max
Min
Unit
Max
ns
2
A0-A23 valid to RD , WR or HWR
asserted
tAC
(1+ALE)x-20
17
ns
3
A0-A23 hold after RD , WR or HWR
negated
tCAR
x-14
4.5
ns
4
A0-A23 valid to D0-D15 Data in
tAD
x(2+TW+ALE)-42
50.5
ns
5
RD asserted to D0-D15 data in
tRD
x(1+TW)-28
27.5
ns
6
RD
7
8
9
10
11
12
13
14
tRR
x(1+TW)-10
45.5
ns
D0-D15 hold after RD negated
tHR
0
0
ns
RD negated to next A0-A23 output
tRAE
x-15
x(1+TW)-10
3.5
45.5
ns
width low
WR /HWR
width low
tWW
WR or HWR asserted to D0-D15
tDO
valid
D0-D15 hold after
HWR negated
WR
or
D0-D15 hold after WR or HWR
negated
A0-A23 valid to
WAIT
input
WAIT hold after RD , WR or HWR
asserted
12.3
ns
12.3
ns
tDW
x(1+TW)-18
37.5
ns
tWD
x−15
3.5
ns
tAW
tCW
x(TW-3)+7
x+(ALE)x+(TW-1
)x -30
x(TW-1)-17
25.5
25.5
ns
38.5
ns
Note 1: No. 1 to 13:
Internal 2 wait insertion ,ALE “1” Clock,@54MHz
TW = (Auto wait insertion + 2N)
No. 14 :
Conditions (Auto wait insertion + 2N)
TW = 2 + 2*1 = 4
AC measurement conditions:
Output levels:
High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF
Input levels:
High = 0.7DVCC33 V/Low 0.3DVCC33 V
TMP19A64(rev1.1)4-7
TMP19A64F20AXBG
(2) DVCC15=CVCC15=FVCC15=1.35V to 1.65V, DVCC3n=FVCC3=1.65V to 1.95V
SYSCR3<ALESEL> = “0”, 2programmed wait state
No.
Parameter
1
System clock period (x)
Equation
Symbol
Min
54 MHz (fsys) Unit
Max
Min
Max
tSYS
18.5
2 A0-A23 valid to RD , WR or HWR
asserted
3 A0-A23 hold after RD , WR or HWR
negated
tAC
(1+ALE)x-20
17
ns
tCAR
x-7
11.5
ns
4
A0-A23 valid to D0-D15 Data in
tAD
x(2+TW+ALE)-42
50.5
ns
5
RD asserted to D0-D15 data in
tRD
x(1+TW)-28
27.5
ns
6
RD
7
width low
ns
tRR
x(1+TW)-10
45.5
ns
D0-D15 hold after RD negated
tHR
0
0
ns
8 RD negated to next A0-A23 output
tRAE
x-15
3.5
ns
9
tWW
x(1+TW)-10
45.5
ns
WR /HWR
width low
10 WR or HWR asserted to D0-D15 valid
11
12
13
14
D0-D15 hold after
negated
D0-D15 hold
negated
after
A0-A23 valid to
WR
or
WR
or
WAIT
HWR
HWR
12.3
tDO
WAIT hold after RD , WR or HWR
asserted
ns
tDW
x(1+TW)-18
37.5
ns
tWD
x−15
3.5
ns
tAW
input
12.3
tCW
x(TW-3)+7
x+(ALE)x+(TW-1
)x -30
x(TW-1)-17
25.5
Note 1: No. 1 to 13:
Internal 2 wait insertion ,ALE “1” Clock,@54MHz
TW = (Auto wait + 2N)
No. 14 :
Conditions (Auto wait insertion + 2N)
TW = 2 + 2*1 = 4
AC measurement conditions:
Output levels:
High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF
Input levels:
High = 0.7DVCC33 V/Low 0.3DVCC33 V
TMP19A64(rev1.1)4-8
25.5
ns
38.5
ns
TMP19A64F20AXBG
(1)
Read cycle timing (SYSCR3<ALESEL> = 0, 1 programmed wait state)
4CLK/1BUS Cycle
Internal
CLK
S1
Sw
S2
S0
S1
CS0~3
tAD
A0~23
tAC
tHR
D0~15
D0∼15
tRR
RD
tRD
R/W
TMP19A64(rev1.1)4-9
tCAR
tRAE
TMP19A64F20AXBG
(2) Read cycle timing (SYSCR3<ALESEL> = 1, 1 programmed wait state)
5CLK/1BUS Cycle
InternalCLK
S1i
S1
Sw
S2
S0
S1i
CS0~3
tAD
A16~23
tAC
tHR
tAD
D0~15
D0∼15
tRR
RD
tRD
R/W
TMP19A64(rev1.1)4-10
tCAR
tRAE
TMP19A64F20AXBG
(2)Read cycle timing SYSCR3<ALESEL> = 1, 4 externally generated wait states with N = 1)
8CLK/1BUS Cycle
Internal
CLK
S1
Sw
Sw
SwE
Sw
S0
S2
CS0~3
A0~23
D0~15
D0∼15
RD
tCW
R/W
tAW
WAIT
TMP19A64(rev1.1)4-11
S1i
TMP19A64F20AXBG
(4) Write cycle timing (SYSCR3<ALESEL> = 1, zero wait sate)
4CLK/1BUS Cycle
Internal
CLK
CS0~3
A0~23
tAC
tDW
D0~15
tWD
D0∼15
tDO
tWW
WR, HWR
R/W
TMP19A64(rev1.1)4-12
tCAR
TMP19A64F20AXBG
[2]Multiplex Bus mode
(1) DVCC15=CVCC15=FVCC15=1.35V to 1.65V, DVCC3n=FVCC3=2.3V to 3.3V
1.
ALE width = 1 clock cycle, 2 programmed wait state
No.
Equation
Symbo
l
Parameter
Min
1
2
3
4
5
System clock period (x)
A0-A15 valid to ALE low
A0-A15 hold after ALE low
ALE pulse width high
ALE low to
asserted
RD
,
WR
or
HWR
54 MHz
(fsys)
Max
Min
Unit
Max
tSYS
18.5
tAL
(ALE)x-12
6.5
ns
ns
tLA
x-8
10.5
ns
tLL
(ALE)x-6
12.5
ns
tLC
x-8
10.5
ns
6
RD , WR or HWR negated to ALE high
tCL
x-15
3.5
ns
7
A0-A15 valid to RD , WR or HWR
asserted
tACL
2x-20
17.0
ns
8
A16-A23 valid to RD , WR or HWR
asserted
tACH
2x-20
17.0
ns
9
A16-A23 hold after RD , WR or HWR
negated
tCAR
x-14
4.5
ns
10
A0-A15 valid to D0-D15 Data in
tADL
x(2+TW+ALE)-42
50.5
ns
tADH
x(2+TW+ALE)-42
50.5
ns
tRD
x(1+TW)-28
27.5
ns
11
12
A16-A23 valid to D0-D15 Data in
RD asserted to D0-D15 data in
13
RD
tRR
x(1+TW)-10
45.5
ns
14
D0-D15 hold after RD negated
tHR
0
0
ns
15
RD negated to next A0-A15 output
tRAE
x-15
3.5
ns
16
WR / HWR
width low
tWW
x(1+TW)-10
45.5
ns
D0-D15 valid to WR or HWR
negated
D0-D15 hold after WR or HWR
negated
tDW
x(1+TW)-18
37.5
ns
tWD
x-15
3.5
ns
17
18
19
20
21
width low
A16-A23 valid to WAIT input
tAWH
x+(ALE)x+(TW-1)x-3
0
25.5
ns
A0-A15 valid to WAIT input
tAWL
x+(ALE)x+(TW-1)x-3
0
25.5
ns
WAIT hold after RD , WR or HWR
asserted
tCW
38.5
ns
x(TW-3)+7
x(TW-1)-17
25.5
Note 1: No. 1 to 20:
Internal 2 wait insertion ,ALE “1” Clock,@54MHz
TW = (Auto wait insertion + 2N)
No. 21 :
Conditions (Auto wait + 2N)
TW = 2 + 2*1 = 4
AC measurement conditions:
Output levels:
High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF
TMP19A64(rev1.1)4-13
TMP19A64F20AXBG
Input levels:
High = 0.7DVCC33 V/Low 0.3DVCC33 V
(2) DVCC15=CVCC15=FVCC15=1.35V to 1.65V, DVCC3n=FVCC3=1.65V to 1.95V
ALE width = 1 clock cycles, 2 programmed wait state
No.
1
2
3
4
5
6
Symbo
l
Parameter
System clock period (x)
A0-A15 valid to ALE low
A0-A15 hold after ALE low
ALE pulse width high
ALE low to
asserted
RD
,
WR
or
HWR
RD , WR or HWR negated to ALE
Equation
Min
54 MHz (fsys) Unit
Max
Min
Max
tSYS
18.5
tAL
(ALE)x-12
6.5
ns
ns
tLA
x-8
10.5
ns
tLL
(ALE)x-6
12.5
ns
tLC
x-8
10.5
ns
tCL
x-15
3.5
ns
high
7
A0-A15 valid to RD , WR or HWR
asserted
tACL
2x-20
17.0
ns
8
A16-A23 valid to RD , WR or HWR
asserted
tACH
2x-20
17.0
ns
9
A16-A23 hold after RD , WR or HWR
negated
tCAR
x-7
11.5
ns
10
11
A0-A15 valid to D0-D15 Data
in
12
A16-A23 valid to D0-D15 Data in
RD asserted to D0-D15 data in
13
RD
14
D0-D15 hold after RD negated
width low
tADL
x(2+TW+ALE)-42
50.5
ns
tADH
x(2+TW+ALE)-42
50.5
ns
tRD
x(1+TW)-28
27.5
ns
tRR
x(1+TW)-10
45.5
ns
tHR
0
0
ns
15
RD negated to next A0-A15 output
tRAE
x-15
3.5
ns
16
WR / HWR
width low
tWW
x(1+TW)-10
45.5
ns
D0-D15 valid to WR or HWR
negated
D0-D15 hold after WR or HWR
negated
tDW
x(1+TW)-18
37.5
ns
tWD
x-15
3.5
ns
17
18
19
20
21
A16-A23 valid to WAIT input
tAWH
x+(ALE)x+(TW-1)x-3
0
25.5
ns
A0-A15 valid to WAIT input
tAWL
x+(ALE)x+(TW-1)x-3
0
25.5
ns
WAIT hold after RD , WR or HWR
asserted
tCW
38.5
ns
x(TW-3)+7
x(TW-1)-17
25.5
Note 1: No. 1 to 20:
Internal 2 wait insertion ,ALE “1” Clock,@54MHz
TW = (Auto insert wait + 2N)
No. 21 :
Conditions (Auto 2 waits insertion + 2N)
TW = 2 + 2*1 = 4
AC measurement conditions:
Output levels:
High = 0.8DVCC33 V/Low 0.2DVCC33 V, CL = 30 pF
TMP19A64(rev1.1)4-14
TMP19A64F20AXBG
Input levels:
High = 0.7DVCC33 V/Low 0.3DVCC33 V
(1) Read cycle timing, ALE width = 1 clock cycle, 1 programmed wait state
5CLK/1BUS Cycle
Internal
CLK
S1i
W1
S1
Sw
S2
S3
S2
S1
S0
S1i
tLL
ALE
tCL
tAL
tLA
AD0~15
D0∼15
A0∼15
tADL
tADH
A16~23
tHR
tACH
tACL
tLC
tRR
tCAR
tRAE
RD
tRD
CS0~3
R/W
TMP19A64(rev1.1)4-15
TMP19A64F20AXBG
(2) Read cycle timing, ALE width = 1 clock cycle, 2 programmed wait state
6CLK/1BUS Cycle
Internal
CLK
tLL
ALE
tCL
tAL
tLA
AD0~15
D0∼15
A0∼15
tADL
tADH
A16~23
tHR
tACH
tACL
tLC
tRR
tCAR
tRAE
tRD
RD
CS0~3
R/W
TMP19A64(rev1.1)4-16
TMP19A64F20AXBG
(3) Read cycle timing, ALE width = 1 clock cycle, 4 programmed wait state
8CLK/1BUS Cycle
Internal
CLK
ALE
AD0~15
A0∼15
D0∼15
AD16~23
RD
tCW
CS0~3
R/W
tAWL/H
WAIT
TMP19A64(rev1.1)4-17
TMP19A64F20AXBG
(4) Read cycle timing, ALE width = 2 clock cycle, 1 programmed wait state
6CLK/1BUS Cycle
Internal
CLK
S1i
S1x
S1
Sw
S2
S0
S1i
tLL
ALE
tAL
tCL
tLA
AD0~15
A0∼15
D0∼15
tADL
tHR
tADH
A16~23
tACH
tACL
tLC
tRR
tRAE
tRD
RD
CS0~3
R/W
TMP19A64(rev1.1)4-18
TMP19A64F20AXBG
(5) Read cycle timing, ALE width = 2 clock cycle, 4 programmed wait state
9CLK/1BUS Cycle
Internal
CLK
S1x
S1
Sw
Sw
SwEx
Sw
S2
S0
ALE
AD0~15
A0∼15
D0∼15
AD16~23
RD
tCW
CS0~3
R/W
tAWL/H
WAIT
TMP19A64(rev1.1)4-19
S1x
TMP19A64F20AXBG
(6) Write cycle timing, ALE width = 2 clock cycles, zero wait state
5CLK/1BUS Cycle
Internal
CLK
tLL
ALE
tAL
tCL
tLA
AD0~15
D0∼15
A0∼15
tDW
AD16~23
tWD
tACH
tACL
tLC
WR, HWR
CS0~3
R/W
TMP19A64(rev1.1)4-20
tWW
tCAR
TMP19A64F20AXBG
(7) Write cycle timing, ALE width = 1 clock cycles, 2 wait state
6CLK/1BUS Cycle
Internal
CLK
tLL
ALE
tAL
tCL
tLA
AD0~15
D0∼15
A0∼15
tDW
AD16~23
tWD
tACH
tACL
tLC
tWW
WR, HWR
CS0~3
R/W
TMP19A64(rev1.1)4-21
tCAR
TMP19A64F20AXBG
(8) Write cycle timing, ALE width = 2 clock cycles, 4 wait state
9CLK/1BUS Cycle
Internal
CLK
tLL
ALE
tAL
tCL
tLA
AD0~15
AD16~23
D0∼15
A0∼15
tDW
tWD
tWW
tCAR
tACH
tACL
tLC
WR, HWR
tCW
CS0~3
R/W
tAWL/H
WAIT
TMP19A64(rev1.1)4-22
TMP19A64F20AXBG
4.7
Transfer with DMA Request
The following shows an example of a transfer between the on-chip RAM and an external
device in multiplex bus mode.
•
16-bit data bus width, non-recovery time
•
Level data transfer mode
•
Transfer size of 16 bits, device port size (DPS) of 16 bits
•
Source/destination: on-chip RAM/external device
The following shows transfer operation timing of the on-chip RAM to an external bus during write
operation (memory-to-memory transfer).
GCLKIN
Internal
Clock
①tDREQ_w
②tDREQ_w
DREQn
②tDREQ_r
①tDREQ_r
AD[15:0]
Add
Data
(N-1)transfer
Add
Data
N transfer
Add
(N+1)transfe
ALE
HWR
LWR
CS
R/W
GBSTART
内部的には
GACK
2Clk
2Clk
(1) Indicates the condition under which Nth transfer is performed successfully.
(2) Indicates the condition under which (N + 1)th transfer is not performed.
TMP19A64(rev1.1)4-23
Data
TMP19A64F20AXBG
(1) DVCC15=CVCC15=FVCC15= 1.35V to 1.65V, AVCC3m=FVCC3=2.7V to 3.3V
DVCC33=2.3V to 3.3V, DVCC30/31/32/34=1.65V to 3.3V, Ta= -20 to 85°C (m=1 to 2)
Equation
No.
Parameter
54 MHz (fsys)
Symbol
(1)Min
(2)Max
Min
Max
Unit
2
RD asserted to DREQn negated
(external device to on-chip RAM
transfer)
tDREQ_r
(W+1)x
(2W+ALE+8)x
-51
37
152.5
ns
3
WR / HWR rising to DREQn negated
tDREQ_w
-(W+2)x
(5+WAIT)x-51.8
-55.5
59.2
ns
(on-chip RAM to external device
transfer)
(2) DVCC15=CVCC15=FVCC15=1.35V to 1.65V, AVCC3m =FVCC3=2.7V to 3.3V
DVCC33=1.65V to 1.95V, DVCC30/31/32/34=1.65V to 3.3V, Ta=-20 to 85°C (m=1 to 2)
Equation
No.
2
Parameter
Symbol
RD asserted to DREQn negated
WR / HWR rising to DREQn negated
Unit
(1)Min
(2)Max
Min
Max
tDREQ_r
(W+1)x
(2W+ALE+8)
x-56
37
147.5
ns
tDREQ_w
-(W+2)x
(5+WAIT)x-56.8
-55.5
54.2
ns
(external device to on-chip RAM
transfer)
3
54 MHz (fsys)
(on-chip RAM to external device
transfer)
Number of wait-state cycles inserted. In the case of (2 + N) externally generated wait states with
N = 1, W becomes 4
ALE: Apply ALE = ALE 1 clock, ALE = 1 for ALE 2 clock. The values in the above table are obtained
with W = 1, ALE = 1.
W:
TMP19A64(rev1.1)4-24
TMP19A64F20AXBG
4.8
Serial Channel Timing
(1)
I/O Interface mode (DVCC3n = 1.65V to 3.3V)
In the table below, the letter x represents the fsys cycle period, which varies depending on
the programming of the clock gear function.
(1) SCLK input mode (SIO0 to SIO6)
Parameter
Symbol
Equation
Min
54 MHz
Max
Min
Max
Unit
tSCY
12x
222
ns
SCLK Clock High width(input)
TscH
6x
111
ns
SCLK Clock Low width (input)
TscL
6x
111
ns
tOSS
2x-30
6
ns
8x-15
129
ns
SCLK period
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall*
tOHS
RxD data valid to SCLK rise or fall*
tSRD
30
30
ns
tHSR
2x+30
66
ns
RxD data hold after SCLK rise or fall*
* SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
2.
SCLK output mode (SIO0 to SIO6)
Parameter
Symbol
Equation
Min
54 MHz
Max
Min
Max
Unit
tSCY
8x
222
ns
TxD data to SCLK rise or fall*
tOSS
4x-10
62
ns
TxD data hold after SCLK rise or fall*
tOHS
4x-10
62
ns
RxD data valid to SCLK rise or fall*
tSRD
45
45
ns
tHSR
0
0
ns
SCLK period
RxD data hold after SCLK rise or fall*
tSCY
SCLK
SCK Output Mode/
Active-High
SCL Input Mod
SCLK
Active-Low SCK
Input Mode
OUTPUT DATA
TxD
tOSS
0
tOHS
1
2
tSRD
INPUT DATA
RxD
3
tHSR
0
1
2
3
VALID
VALID
VALID
VALID
TMP19A64(rev1.1)4-25
TMP19A64F20AXBG
4.9
SBI Timing
(1) I2C mode
In the table below, the letters x represent the fsys periods, respectively.
n denotes the value of n programmed into the SCK (SCL output frequency select) field in
the SBI0CR1.
Parameter
Equation
Symbol
Min
Max
0
Standard mode
Fast mode
Min
Max
Min
Max
0
100
0
400
Unit
kHz
SCL clock frequency
tSCL
Hold time for START condition
tHD:STA
4.0
0.6
μs
SCL clock low width (Input) (Note 1)
tLOW
4.7
1.3
μs
4.0
0.6
μs
4.7
0.6
μs
SCL clock high width (Output) (Note 2) tHIGH
Setup time for a repeated START
condition
tSU;STA
Data hold time (Input) (Note 3, 4)
tHD;DAT
0.0
0.0
μs
Data setup time
tSU;DAT
250
100
ns
Setup time for STOP condition
tSU;STO
4.0
0.6
μs
Bus free time between STOP and
START conditions
tBUF
4.7
1.3
μs
(Note 5)
(Note 5)
Note 1:
SCL clock low width (output) is calculated with: (2n-1 +58)/(fsys/2)
Note 2:
SCL clock high width (output) is calculated with (2n-1 +12)/(fsys/2)
Notice: On I2C-bus specification, Maximum Speed of Standard mode is 100KHz ,Fast mode is
400Khz. Internal SCL clock Frequency setting should be shown above Note1 & Note2.
Note 3:
The output data hold time is equal to 12x
Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at
least 300 ns for the SDA signal to bridge the undefined region of the fall edge of SCL.
However, the 19A64 SBI does not satisfy this requirement. Also, the output buffer for SCL
does not incorporate slope control of the falling edges; therefore, the equipment manufacturer
should design so that the input data hold time shown in the table is satisfied, including tr/tf of
the SCL and SDA lines.
Note 5:
Software-dependent
tSCL
tf
tLOW
tr
tHIGH
SCL
tHD;STA
tSU;DAT
tHD;DAT
tSU;STA
tSU;STO
SDA
S
Sr
S: START condition
Sr: Repeated START condition
P: STOP condition
TMP19A64(rev1.1)4-26
P
tBUF
TMP19A64F20AXBG
(2) Clock-Synchronous 8-Bit SIO mode
In the tables below, the letters x represent the fsys cycle periods, respectively. The letter
n denotes the value of n programmed into the SCK (SCL output frequency select) field in
the SBI0CR1.
The electrical specifications below are for an SCK signal with a 50% duty cycle.
③ SCK Input mode
Parameter
Equation
Symbol
Min
54 MHz
Max
Min
Max
Unit
SCK period
tSCY
16x
296
ns
SO data to SCK rise
tOSS
(tSCY/2) − (6x + 30)
7
ns
SO data hold after SCK rise
tOHS
(tSCY/2) + 4x
222
ns
SI data valid to SCK rise
tSRD
0
0
ns
SI data hold after SCK rise
tHSR
4x + 10
84
ns
④ SCK Output mode
Parameter
Equation
Symbol
Min
tSCY
SCK period (programmable)
54 MHz
Max
Min
Max
Unit
16x
296
ns
ns
SO data to SCK rise
tOSS
(tSCY/2) − 20
128
SO data hold after SCK rise
tOHS
(tSCY/2) − 20
128
ns
SI data valid to SCK rise
tSRD
2x + 30
67
ns
SI data hold after SCK rise
tHSR
0
0
ns
tSCY
SCLK
tOSS
OUTPUT DATA
TxD
0
tOHS
1
2
tSRD
INPUT DATA
TxD
3
tHSR
0
1
2
3
VALID
VALID
VALID
VALID
TMP19A64(rev1.1)4-27
TMP19A64F20AXBG
4.10
Event Counter
In the table below, the letter x represents the fsys cycle period.
Parameter
Symbol
Equation
Min
54 MHz
Max
Min
Max
Unit
Clock low pulse width
tVCKL
2X + 100
137
ns
Clock high pulse width
tVCKH
2X + 100
137
ns
4.11
Timer Capture
In the table below, the letter x represents the fsys cycle period.
Parameter
Symbol
Equation
Min
54 MHz
Max
Min
Max
Unit
Low pulse width
tCPL
2X + 100
137
ns
High pulse width
tCPH
2X + 100
137
ns
4.12
General Interrupts
In the table below, the letter x represents the fsys cycle period.
Parameter
Symbol
Equation
Min
54 MHz
Max
Min
Max
Unit
Low pulse width for INT0-INTA
tINTAL
X + 100
118.5
ns
High pulse width for INT0-INTA
tINTAH
X + 100
118.5
ns
4.13
NMI and STOP /SLEEP Wake-up Interrupts
Parameter
Symbol
Equation
Min
54 MHz
Max
Min
Max
Unit
Low pulse width for NMI and
INT0-INT4
tINTBL
100
100
ns
High pulse width for INT0-INT4
tINTBH
100
100
ns
4.14
SCOUT Pin
Parameter
Symbol
Equation
Min
54 MHz
Max
Min
Max
Unit
Clock high pulse width
tSCH
0.5T − 5
4.25
ns
Clock low pulse width
tSCL
0.5T −
4.25
ns
5
Note: In the above table, the letter T represents the cycle period of the SCOUT output clock.
tSCH
SCOUT
tSCL
TMP19A64(rev1.1)4-28
TMP19A64F20AXBG
4.15
Bus Request and Bus Acknowledge Signals
BUSRQ
(Note1)
BUSAK
tBAA
tABA
(Note2)
AD0~AD15
(Note2)
A0~A23,
RD , WR
CS0 ~ CS3 ,
R / W , HWR
ALE
Parameter
Symbol
Equation
54 MHz
Min
Max
Min
Max
Unit
Bus float to BUSAK asserted
tABA
0
80
0
80
ns
Bus float after BUSAK negated
tBAA
0
80
0
80
ns
Note 1: If the current bus cycle has not terminated due to wait-state insertion, the
TMP19A64F20BXBG does not respond to BUSRQ until the wait state ends.
Note 2: This broken line indicates that output buffers are disabled, not that the
signals are at indeterminate states. The pin holds the last logic value present
at that pin before the bus is relinquished. This is dynamically accomplished
through external load capacitances. The equipment manufacturer may
maintain the bus at a predefined state by means of off-chip restores, but he
or she should design, considering the time (determined by the CR constant)
it takes for a signal to reach a desired state. The on-chip, integrated
programmable pullup/pulldown resistors remain active, depending on
internal signal states.
TMP19A64(rev1.1)4-29
TMP19A64F20AXBG
4.16
KWUP Input
Pull-up Register Active
Parameter
Equation
Symbol
Min
54 MHz
Max
Min
Max
Unit
Low pulse width for KEY0-D
tkyTBL
X+100
118
ns
High pulse width for KEY0-D
tkyTBH
X+100
118
ns
4.17
Dual Pulse Input
Parameter
Equation
Symbol
Min
54 MHz
Max
Min
Max
Unit
Dual input pulse period
Tdcyc
8Y
296
ns
Dual input pulse setup
Tabs
Y+20
57
ns
Dual input pulse hold
Tabh
Y+20
57
ns
Y:
Sampling clock (fsys/2)
A
Tabs
B
Tabh
Tdcyc
TMP19A64(rev1.1)4-30