Application Note Transceiver TH7122x Narrow Band TH7122 and TH71221 Used In Narrow Band FSK Applications 1 Narrow band considerations The most common application for low power transceivers is in applications where the channel bandwidth and spacing are relatively wide. In these cases, the peak FSK deviation is usually around 25 to 50kHz, and the channel spacing is usually 200kHz or more. In the case of the TH7122x, the intermediate frequency (IF) filter is usually a low cost FM receiver filter with a bandwidth from 150 to 250kHz. For these applications the VCO noise is usually not a big consideration because the frequency deviation causes a voltage swing at the demodulator output which is much greater than the noise. Also, the loop bandwidth is usually wide because the reference frequency is high. This allows for modulation of the reference frequency by simple switching of the load capacitance on a crystal. The TH7122x is designed to work in these applications and gives very good results. However, if it is used in narrow band applications with small channel spacing such as 12.5 or 25kHz, the loop bandwidth must be small to allow for stable PLL operation and to suppress the reference spurs sufficiently. The reference frequency for the integer N synthesizer is equal to the channel spacing. For these designs, the VCO noise becomes very important and some changes need to be made to the usual application circuit to improve the performance. A second consideration in narrow band applications is that the transmitter which uses the same PLL as the receiver must be capable of FSK generation. Since the PLL bandwidth must be narrow, it is necessary to generate FSK by modulating the VCO outside the loop bandwidth. If FSK modulation down to DC is required, it is also necessary to modulate the reference crystal oscillator at the low frequencies and the VCO at high frequencies. This is often referred to as two point modulation. The difficult part is to make a smooth transition from modulation of the VCO to modulation of the reference. In this application, we will assume DC modulation is not needed and so the low loop frequency can be set to accommodate the widest data pulses. 2 VCO design In order to reduce the phase noise of the VCO in the TH7122x, the impedance of the tuned circuit must be reduced. The negative resistance oscillator goes into saturation with high impedance load and reduces the Q of the resonator. The resonator Q is reduced further by the relatively low Q of the internal varactor diode. In the usual application, the inductance of the tuned circuit is determined by the capacitance of the internal varactor and any fixed capacitance across the VCO tank coil. The capacitance in parallel with the coil can be increased, but this limits the tuning range which must be large enough to tune the offset between the transmit frequency and VCO frequency for receive. Note the offset frequency corresponds to the IF because the TH7122x constitutes a super-heterodyne receiver. Usually, the IF is 10.7MHz. The solution is to use a small inductance together with an external varactor but not to make the tuned circuit impedance smaller. Fig. 3 shows the circuit of an evaluation board with a small tuning inductor and an external varactor to increase the tuning capacitance. In this case a BB639 diode was used because it was available and is a low cost diode usually used for TV tuners. Almost any tuning diode with enough capacitance could be used by simply adjusting C0. Care must be taken not to make L0 so small that the oscillator does not oscillate. Since the oscillator current is programmable, the oscillator can be checked for operation it at the lowest current setting and then operated at the highest current for lowest noise. 3 PLL setup In order to design the PLL loop filter, it is first necessary to know the phase detector constant and VCO tuning sensitivity KVCO around the desired frequency. There are two ways to determine KVCO: 1. Tune the VCO with a variable voltage from a potentiometer (e.g. 1kΩ) or power supply and measure the output frequency with a counter or spectrum analyzer. This can be done by simply connecting the variable voltage via a 100kΩ resistor to pin 23 of the TH7122x. Using the software for programming the TH7122x with a personal computer, set it to transmit mode, VCOCUR to ‘11’ high current2, and PACTRL to ‘1’ so the PA is always on. Adjust the tuning voltage and measure the output frequency. 390110712203 Rev. 002 Page 1 of 8 AN7122x-NB Aug./04 Application Note Transceiver TH7122x Narrow Band 2. Set-up the TH7122x to operate at the desired frequency in transmit mode using the loop filter on the evaluation board. Connect a high-impedance digital voltmeter to pin 23, the charge pump output. Using the TH7122x software, set the transmitter to frequencies around the operating frequency, and measure the tuning voltage at each frequency. Be careful to keep capacitive and resistive loading at pin 23 should be as low as possible to avoid influencing the over-all stability of the PLL. A tuning curve taken on an evaluation board is shown in Fig. 1. In this example it can be seen that the slope of the tuning voltage around 434MHz is typically about 14MHz/Volt. Expressed in an angular relation the KVCO yields in K VCO = 2π ⋅ 13 MHz rad 1 = 81.7 ⋅ 10 6 . V s V A second design parameter is the gain of the phase detector KPD. This parameter is proportional to the charge pump current ICP which is 260µA by default. The phase detector constant is expressed as K PD = I CP µA = 41.4 . 2π rad Loop filter Voltage / V (pin 23) As we will see below the 2π term cancels out since KPD and KVCO are always multiplied together. 3.0 2.0 1.0 0.0 430 420 440 450 VCO frequency / MHz Fig. 1: TH7122x VCO tuning curve for 434MHz center frequency The recommended loop filter topology is a 2nd order as depicted in Fig. 2. From the filter transfer function F(s) we can obtain a zero and a non-DC pole frequency1: ωz = 1 R F ⋅ C F1 ωP = C F1 + C F2 C F1 ⋅ C F2 ⋅ R F 1 Investigation of the details of the PLL behaviour would require more space than this application note allows. A more detailed analysis of the PLL behaviour can be found in references [1] – [3]. 390110712203 Rev. 002 Page 2 of 8 AN7122x-NB Aug./04 Application Note Transceiver TH7122x Narrow Band The 3dB bandwidth of the PLL in a closed loop configuration is approximately the transit frequency ωT of the loop filter. Since CF2 is much smaller than CF1 in most of the cases, ωT can be approximated as described in [4]: ωT ≈ K PD ⋅ K VCO ⋅ R F C F1 ⋅ N C F1 + C F2 K PD ⋅ K VCO ⋅ R F N ≈ In these equations N represents the value of the feedback divider. For a stable loop the available phase margin is of importance. It should be in between 30 and 70 degrees. To ensure enough phase margin at the transit frequency ωT, the zero frequency should be located M times below and the pole frequency M times above ωT. As mentioned in [4] a factor M of four gives a phase margin of approximately 60 degrees. With M = 2.5 the phase margin will be approximately 45 degrees. Fig. 2: K PD K VCO s nd + 2 order Loop filter LF F(s) CF1 CF2 RF By using these equations the loop-filter elements can be easily obtained: RF = K PD N ⋅ ωT ⋅ K VCO C F1 = M R F ⋅ ωT C F2 = 1 M ⋅ R F ⋅ ωT This approximation is quite accurate for calculating the loop filter elements. Normally the step size between the available component values is larger than the error using this calculation method, so that there is no need to use the more complex exact formulas. Nevertheless the exact calculation can be found in [1-3]. Example: If a channel step size of 12.5kHz is used, a feedback divider of N = 34720 is necessary to achieve a desired operating frequency of 434MHz. Assume a narrow loop frequency, ωT of about 2π · 50 Hz because of the external VCO modulation. In case of direct modulation of the VCO as a rule of thumb the lowest data signal frequency should be 10 times higher than the loop frequency. To insure loop stability we want a phase margin of about 45 degrees, so the factor M is 2.5. With the equations above and the calculated gains KPD and KVCO the loop filter elements result in: C F1 = 2.2 µF C F2 = 470 nF R F = 3.3 kΩ The complete narrow band transceiver application schematic is show in Fig. 3 390110712203 Rev. 002 Page 3 of 8 AN7122x-NB Aug./04 Application Note GND SDTA SDEN SCLK IN_DTA GND OUT_DTA GND RSSI GND OUT_DEM GND 4 3 2 1 4 3 2 1 4 3 2 1 RM3 12 3 ASK/FSK CX1 RSSI 7 OUT_DEM 6 CTX4 CB2 LTX0 CRX0 C2 LRX2 CTX2 50 LTX1 C1 TX_OUT RX_IN L1 C4 C3 RP CB5 1 IN_IFA CERDIS RL0 CB4 CERFIL LIF1 VCC CTX1 CTX0 28 OUT_LNA 24 RPS 32 OUT_MIX 2 31 VEE_IF VCC_IF 30 IN_MIX 23 LF 29 GAIN_LNA 3 27 VEE_LNA 4 IN_DEM 26 IN_LNA INT2/PDO 22 VEE_PLL OUT_PA CF2 INT1 5 C5 RB1 CB1 CIF1 CIF2 VCC RO 10 IN_DTA 12 FSK_SW 11 ASK/FSK 13 8 TH7122 21 TNK_LO C0 25 RF 19 FS1/LD 20 VCC_PLL L0 RF1 CF1 OUT_DTA 18 VEE_DIG VD1 RM1 CM1 VCC_DIG 14 FS0/SDEN 17 RE/SCLK 15 16 CB6 RB0 9 XTAL CB7 VEE_RO RE/SCLK TE/SDTA 12 3 FS0/SDEN 12 3 RS2 RS3 RS1 12 3 CB0 RM2 FS1/LD 2 1 12 3 CM2 VCC GND Transceiver TH7122x Narrow Band Fig. 3: TH7122x circuit schematic for narrow band applications 390110712203 Rev. 002 Page 4 of 8 AN7122x-NB Aug./04 Application Note Transceiver TH7122x Narrow Band 4 Transmitter Set-Up Continuing our example from the previous section, assume we want a peak FSK deviation of 2.5kHz with a 3.0V logic signal. Since the slope of the VCO control voltage is 13MHz/V, this would require a level of 192uV. If we make RM1 = 1MΩ, then the input to it would be 58mV. For the FSK modulation to have flat frequency response, the time constant of RM1 · CM1 should match the time constant of CF2 · RF, so CM1 = 1.5nF. Additional attenuation is needed so done by adding RM2 and RM3 to the data input connector. The modulation bandwidth of the VCO is very wide when the loop is modulated, so it may be desirable to shape the data signal in order to limit the occupied bandwidth of the RF signal. This has been done by adding CM2 across the input attenuator. Fig. 4 and Fig. 5 show the RF output signal in CW mode and with modulation applied to the IN_DTA pin, respectively. 22.Jan 04 11:37 Ref 10 dBm * Att 40 dB RBW 3 kHz *VBW 1 kHz SWT 85 ms 10 0 -10 -20 -30 -40 -50 -60 -70 -80 Center 433.9285 MHz 12.5 kHz/ Span 125 kHz Fig. 4: CW output spectrum of the TH7122x in transmit mode 390110712203 Rev. 002 Page 5 of 8 AN7122x-NB Aug./04 Application Note Transceiver TH7122x Narrow Band 22.Jan 04 11:36 Ref 10 dBm * Att 40 dB RBW 3 kHz *VBW 1 kHz SWT 85 ms 10 0 -10 -20 -30 -40 -50 -60 -70 -80 Center 433.9285 MHz 12.5 kHz/ Span 125 kHz Fig. 5: FSK modulation spectrum of the TH7122x in transmit mode 5 Receiver 390110712203 Rev. 002 Page 6 of 8 IN_DEM 3 VCC_IF 2 32 OUT_MIX 31 VEE_IF In systems with 12.5kHz channel spacing, the required channel selectivity is higher. This can be achieved by connecting two filters in cascade as shown in Fig. 6. In this case, a 4-pole 10.7MHz crystal filter is shown. This is usually made up of a cascade of two 2-pole filters (FIL1 and FIL2). The series inductor between the mixer output and FIL1 as well as capacitor in parallel to the filter input match the mixer output impedance to the 1.8kΩ impedance required by the filter. The input resistance of the IF amplifier is approximately 2kΩ, so this is close enough to the required filter load. The maximum stop-band attenuation of this filter is about 40dB which is about the maximum which can be obtained because of leakage between pins 1 and 32 of the TH7122x. If more selectivity is desired, a dual conversion arrangement with an external mixer should be considered. However, the maximum selectivity will be limited by the VCO noise in the adjacent channel. The maximum signal-to-noise ratio is also determined by the VCO noise. In this receiver, with a peak FM deviation of 2.5kHz, it is about 36dB. This was measured over the frequency range from 20Hz to 20kHz. 30 IN_MIX The receiver part of the TH7122x application circuit as shown in Fig. 3 contains a ceramic filter with a 20kHz bandwidth. LIF1, CIF1 and CIF2 are used to match the 330Ω output impedance to the required 600Ω of the ceramic filter. Additionally this circuitry reduces out-of-band spurious responses. RL0 in parallel to the input impedance of the IF amplifier is used to load the filter as specified. The 20dB bandwidth of this filter is approx. 95kHz. CB5 1 IN_IFA VCC FIL2 3.9pF FIL1 10 µH Fig. 6 22pF Cascaded filter configuration AN7122x-NB Aug./04 Application Note Transceiver TH7122x Narrow Band 5.1 Component Values for Fig. 3 Part Size Value @ Tolerance Description 434 MHz C0 0603 8.2 pF ±5% VCO tank capacitor C1 0603 4.7 pF ±5% LNA output tank capacitor C2 0603 1.5 pF ±5% MIX input matching capacitor C3 0805 10 nF ±10% data slicer capacitor C4 0805 1 nF ±10% demodulator output low-pass capacitor C5 0805 1.5 nF ±10% RSSI output low-pass capacitor CB0 1210 ±10% CB1 0603 10 µF 330 pF de-coupling capacitor ±10% de-coupling capacitor CB2 0805 330 pF ±10% de-coupling capacitor CB4 0603 10 nF ±10% de-coupling capacitor CB5 0603 100 nF ±10% de-coupling capacitor CB6 0603 100 pF ±10% de-coupling capacitor CB7 0603 100 nF ±10% de-coupling capacitor CF1 0603 ±5% loop filter capacitor CF2 0805 1.0 µF 100 nF ±10% loop filter capacitor CIF1 0603 180 pF ±5% filter matching capacitor CIF2 0603 220 pF ±5% filter matchingcapacitor CM1 0603 560 pF ±5% modulation capacitor CM2 0603 10 nF ±10% modulation capacitor CX1 0805 47 pF ±5% RO capacitor CRX0 0603 100 pF ±5% RX coupling capacitor CTX0 0603 100 pF ±5% TX coupling capacitor CTX1 0805 5.6 pF ±5% TX impedance matching capacitor CTX2 0805 4.7 pF ±5% TX impedance matching capacitor CTX4 0603 4.7 pF ±5% TX impedance matching capacitor RB0, RB1 0603 100 Ω ±5% protection resistor RF 0603 5.6 kΩ ±5% loop filter resistor RF1 0603 10 kΩ ±5% varactor bias resistor RL0 0603 ±5% RM1 0603 820 Ω 1 MΩ CERFIL loading, optionally ±5% modulation resistor RM2 0603 390 Ω ±5% modulation resistor RM3 0603 10 kΩ ±5% modulation resistor RP 0603 4.7 kΩ ±5% CERRES loading resistor RPS 0603 33 kΩ ±5% power-select resistor RS1 to RS3 0603 ±5% protection resistor LIF1 0603 10 kΩ 2.2 µH ±5% crystal filter matching ind., not needed if FIL1 is ceramic type L0 0603 10 nH ±5% VCO tank inductor L1 0603 15 nH ±5% LNA output tank inductor LRX2 0603 56 nH ±5% RX impedance matching inductor LTX0 0603 15 nH ±5% TX impedance matching inductor LTX1 0603 27 nH ±5% VD1 XTAL SOD-323 HC49 SMD CERFIL FIL1 FIL2 CERDIS leaded BB639 8.0000 MHz ±10ppm calibr. ±20ppm temp. SFKLA10M7NL00 @ BIF2 = 30 kHz HC-49/U ECS-10.7-7.5B @ BIF2 = 7 kHz SMD CDSCB10M7GA136 390110712203 Rev. 002 TX impedance matching inductor VCO tank varactor diode fundamental-mode crystal, Cload = 10 pF to 15pF, C0, max = 7 pF, Rm, max = 70 Ω ceramic filter from Murata, or equivalent part one half (2 poles) of 4-pole crystal filter from ECS, or equivalent part; only required for the Fig. 6 schematic ceramic discriminator from Murata, or equivalent part Page 7 of 8 AN7122x-NB Aug./04 Application Note Transceiver TH7122x Narrow Band References [1] [2] [3] [4] Ulrich L. Rohde: “Microwave and Wireless Synthesizers”, John Wiley & Sons, New York, 1997 Floyd. M. Gardner: “Phaselock Techniques”, John Wiley & Sons, New York, 1979 Behzad Razavi: “Monolithic Phase-Locked Loops and Clock Recovery Circuits - Theory and Design”, IEEE Press, 1996 J. Craninckx and M. Steyaert: “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer”, IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998 Your Notes For the latest version of this document. Go to our website at www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: All other locations: Phone: +32 1367 0495 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] ISO/TS16949 and ISO14001 Certified 390110712203 Rev. 002 Page 8 of 8 AN7122x-NB Aug./04