EFM8UB2 Data Sheet

EFM8 Universal Bee Family
EFM8UB2 Data Sheet
The EFM8UB2, part of the Universal Bee family of MCUs, is a
multi-purpose line of 8-bit microcontrollers with USB feature set.
These devices offer high value by integrating a USB peripheral interface with a high precision oscillator, clock recovery circuit, and integrated transceiver, making them ideal for
any full speed USB applications with no external components required. With an efficient
8051 core and precision analog, the EFM8UB2 family is also optimal for embedded applications.
• Pipelined 8-bit 8051 MCU Core with 48
MHz maximum operating frequency
• Up to 40 multifunction I/O pins
• Crystal-less full speed/low speed USB 2.0
compliant controller with 1 KB buffer
memory
• One differential 10-bit ADC and two analog
comparators
EFM8UB2 applications include the following:
• Consumer electronics
• Medical equipment
• USB I/O controls, dongles
• High-speed communication bridge
KEY FEATURES
• Internal 48 MHz oscillator with ±0.25%
accuracy with USB clock recovery supports
crystal-free USB and UART operation
• 2 UARTs, SPI, 2 SMBus/I2C serial
communications
Core / Memory
Clock Management
CIP-51 8051 Core
(48 MHz)
Flash Program
Memory
RAM Memory
(up to 4352 bytes)
(up to 64 KB)
External
Oscillator
Debug Interface
with C2
Energy Management
High Frequency
48 MHz RC
Oscillator
Low Frequency
RC Oscillator
Internal LDO
Regulator
Power-On Reset
Brown-Out
Detector
5 V-to 3.3 V LDO
Regulator
8-bit SFR bus
Serial Interfaces
2 x UART
SPI
2 x I2C /
SMBus
USB
I/O Ports
External
Interrupts
Pin Reset
General Purpose I/O
Timers and Triggers
6 x Timers
PCA/PWM
Watchdog Timer
Analog Interfaces
ADC
Comparator 0
Comparator 1
Internal
Voltage
Reference
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
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EFM8UB2 Data Sheet
Feature List
1. Feature List
The EFM8UB2 highlighted features are listed below.
• Core:
• Pipelined CIP-51 Core
• Fully compatible with standard 8051 instruction set
• 70% of instructions execute in 1-2 clock cycles
• 48 MHz maximum operating frequency
• Memory:
• Up to 64 KB flash memory, in-system re-programmable
from firmware.
• Up to 4352 bytes RAM (including 256 bytes standard 8051
RAM and 4096 bytes on-chip XRAM)
• Power:
• Internal LDO regulator for CPU core voltage
• Internal 5-to-3.3 V LDO allows direct connection to USB
supply net
• Power-on reset circuit and brownout detectors
• I/O: Up to 40 total multifunction I/O pins:
• Flexible peripheral crossbar for peripheral routing
• 10 mA source, 25 mA sink allows direct drive of LEDs
• Clock Sources:
• Internal 48 MHz precision oscillator ( ±1.5% accuracy
without USB clock recovery, ±0.25% accuracy with USB
clock recovery)
• Internal 80 kHz low-frequency oscillator
• External crystal, RC, C, and CMOS clock options
• Timers/Counters and PWM:
• 5-channel Programmable Counter Array (PCA) supporting
PWM, capture/compare, and frequency output modes with
watchdog timer function
• 6 x 16-bit general-purpose timers
• Communications and Digital Peripherals:
• Universal Serial Bus (USB) Function Controller with eight
flexible endpoint pipes, integrated transceiver, and 1 KB
FIFO RAM
• 2 x UART
• SPI™ Master / Slave
• 2 x SMBus™/I2C™ Master / Slave
• External Memory Interface (EMIF)
• Analog:
• 10-Bit Analog-to-Digital Converter (ADC0)
• 2 x Low-current analog comparators
• On-Chip, Non-Intrusive Debugging
• Full memory and register inspection
• Four hardware breakpoints, single-stepping
• Pre-loaded USB bootloader
• Temperature range -40 to 85 ºC
• Single power supply 2.65 to 3.6 V
• QFP48, QFP32, and QFN32 packages
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8UB2 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field upgrades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. Each device is specified for 2.65 to 3.6 V operation and is available in 32-pin QFN, 32-pin QFP, or 48-pin QFP packages. All package options are lead-free and RoHS compliant.
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EFM8UB2 Data Sheet
Ordering Information
2. Ordering Information
EFM8 UB2 0 F 64 G – A – QFP48 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85)
Flash Memory Size – 64 KB
Memory Type (Flash)
Family Feature Set
Universal Bee 2 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8UB2 Part Numbering
All EFM8UB2 family members have the following features:
• CIP-51 Core running up to 48 MHz
• Two Internal Oscillators (48 MHz and 80 kHz)
• USB Full/Low speed Function Controller
• 5 V-In, 3.3 V-Out Regulator
• 2 SMBus/I2C Interfaces
• SPI
• 2 UARTs
• 5-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
• 6 16-bit Timers
• 2 Analog Comparators
• 10-bit Differential Analog-to-Digital Converter with integrated multiplexer and temperature sensor
• Pre-loaded USB bootloader
In addition to these features, each part number in the EFM8UB2 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
Comparator 1 Inputs
Crystal Oscillator
External Memory
Temperature Range
Package
5
5
Yes
Yes
Yes
-40 to +85 °C
QFP48
EFM8UB20F64G-A-QFP32
64
4352
25
20
5
4
—
—
Yes
-40 to +85 °C
QFP32
EFM8UB20F64G-A-QFN32
64
4352
25
20
5
4
—
—
Yes
-40 to +85 °C
QFN32
EFM8UB20F32G-A-QFP48
32
2304
40
32
5
5
Yes
Yes
Yes
-40 to +85 °C
QFP48
EFM8UB20F32G-A-QFP32
32
2304
25
20
5
4
—
—
Yes
-40 to +85 °C
QFP32
EFM8UB20F32G-A-QFN32
32
2304
25
20
5
4
—
—
Yes
-40 to +85 °C
QFN32
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Comparator 0 Inputs
32
Pb-free
ADC0 Channels
40
Inferface
Digital Port
4352
I/Os (Total)
RAM (Bytes)
64
Number
EFM8UB20F64G-A-QFP48
Ordering Part
Flash Memory (kB)
Table 2.1. Product Selection Guide
Rev. 1.2 | 2
EFM8UB2 Data Sheet
System Overview
3. System Overview
3.1 Introduction
C2D
Port I/O Configuration
Debug / Programming
Hardware
C2CK/RSTb
Digital Peripherals
Reset
Power-On
Reset
Supply
Monitor
VDD
VREGIN
Power
Net
Voltage
Regulators
UART0
CIP-51 8051 Controller
Core
Timers 0, 1,
2, 3, 4, 5
Priority
Crossbar
Decoder
PCA/WDT
SMBus 0
256 Byte RAM
SMBus 1
Crossbar Control
SFR
Bus
External Memory
Interface
External Oscillator
P1
Control
Low Freq.
Oscillator
VBUS
Full / Low
Speed
Transceiver
P2.n
Port 3
Drivers
P3.n
Port 4
Drivers
P4.n
Analog Peripherals
VREF
VDD
VREF
+
-+
Comparators
Controller
1 KB RAM
10-bit
500ksps
ADC
AMUX
D+
D-
Port 2
Drivers
P4
Data
USB Peripheral
P1.n
P2 / P3
Address
Internal Oscillator
Clock
Recovery
Port 1
Drivers
SPI
4/2 KB XRAM
GND
XTAL1
XTAL2
P0.n
UART1
64/32 KB ISP Flash
Program Memory
System Clock Setup
Port 0
Drivers
VDD
Temp
Sensor
Figure 3.1. Detailed EFM8UB2 Block Diagram
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EFM8UB2 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devices without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Details
Mode Entry
Wake-Up Sources
Normal
Core and all peripherals clocked and fully operational
—
—
Set IDLE bit in PCON0
Any interrupt
Idle
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Suspend
• Core and peripheral clocks halted
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0
2. Set SUSPEND bit in
HFO0CN
Shutdown
•
•
•
•
1. Set STOPCF bit in
REG01CN
2. Set STOP bit in
PCON0
All internal power nets shut down
5V regulator remains active (if enabled)
Pins retain state
Exit on pin or power-on reset
USB0 Bus Activity
• RSTb pin reset
• Power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P3.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P4.0-P4.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0 on
some packages.
• Up to 40 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1) available on P0 pins.
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 48 MHz oscillator divided by 4, then divided by 8 (1.5 MHz).
• Provides clock to core and peripherals.
• 48 MHz internal oscillator (HFOSC0), accurate to ±1.5% over supply and temperature corners: accurate to +/- 0.25% when using
USB clock recovery.
• 80 kHz low-frequency oscillator (LFOSC0).
• External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK) for QFP48 packages.
• External CMOS clock option (EXTCLK) for QFP32 and QFN32 packages.
• Internal oscillator has clock divider with eight settings for flexible clock scaling: 1, 2, 4, or 8.
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EFM8UB2 Data Sheet
System Overview
3.5 Counters/Timers and PWM
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
•
•
•
•
•
•
•
•
•
16-bit time base.
Programmable clock divisor and clock source selection.
Up to five independently-configurable channels
8- or 16-bit PWM modes (edge-aligned operation).
Frequency output mode.
Capture on rising, falling or any edge.
Compare function for arbitrary waveform generation.
Software timer (internal compare) mode.
Integrated watchdog timer.
Timers (Timer 0, Timer 1, Timer 2, Timer 3, Timer 4, and Timer 5)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2, Timer 3, Timer 4, and Timer 5 are 16-bit timers including the following features:
• Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• USB start-of-frame or falling edge of LFOSC0 capture (Timer 2 and Timer 3)
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software. The state of the RSTb pin is unaffected by this reset.
The Watchdog Timer integrated in the PCA0 peripheral has the following features:
• Programmable timeout interval
• Runs from the selected PCA clock source
• Automatically enabled after any system reset
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EFM8UB2 Data Sheet
System Overview
3.6 Communications and Other Digital Peripherals
Universal Serial Bus (USB0)
The USB0 module provides Full/Low Speed function for USB peripheral implementations. The USB function controller (USB0) consists
of a Serial Interface Engine (SIE), USB transceiver (including matching resistors and configurable pull-up resistors), 1 KB FIFO block,
and clock recovery mechanism for crystal-less operation. No external components are required. The USB0 module is Universal Serial
Bus Specification 2.0 compliant.
The USB0 module includes the following features:
• Full and Low Speed functionality.
• Implements 4 bidirectional endpoints.
• USB 2.0 compliant USB peripheral support (no host capability).
• Direct module access to 1 KB of RAM for FIFO memory.
• Clock recovery to meet USB clocking requirements with no external components.
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
• Asynchronous transmissions and receptions
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 8- or 9-bit data
• Automatic start and stop generation
Universal Asynchronous Receiver/Transmitter (UART1)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a
16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1
to receive multiple bytes before data is lost and an overflow occurs.
UART1 provides the following features:
• Asynchronous transmissions and receptions.
• Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 5, 6, 7, 8, or 9 bit data.
• Automatic start and stop generation.
• Automatic parity generation and checking.
• Three byte FIFO on receive.
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
The SPI module includes the following features:
• Supports 3- or 4-wire operation in master or slave modes.
• Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode.
• Support for four clock phase and polarity options.
• 8-bit dedicated clock clock rate generator.
• Support for multiple masters on the same data lines.
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EFM8UB2 Data Sheet
System Overview
System Management Bus / I2C (SMB0 and SMB1)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus.
The SMBus modules include the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
• Support for master, slave, and multi-master modes.
• Hardware synchronization and arbitration for multi-master mode.
• Clock low extending (clock stretching) to interface with faster masters.
• Hardware support for 7-bit slave and general call address recognition.
• Firmware support for 10-bit slave address decoding.
• Ability to inhibit all slave states.
• Programmable data setup/hold times.
External Memory Interface (EMIF0)
The External Memory Interface (EMIF) enables access of off-chip memories and memory-mapped devices connected to the GPIO
ports. The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in
either 8-bit or 16-bit formats.
• Supports multiplexed and non-multiplexed memory access.
• Four external memory modes:
• Internal only.
• Split mode without bank select.
• Split mode with bank select.
• External only
• Configurable ALE (address latch enable) timing.
• Configurable address setup and hold times.
• Configurable write and read pulse widths.
3.7 Analog
10-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 10-bit mode, integrated track-and hold and a programmable window
detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure different
signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external reference sources.
The ADC module is a Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The key features of this ADC module are:
• Up to 32 external inputs.
• Differential or Single-ended 10-bit operation.
• Supports an output update rate of 500 ksps samples per second.
• Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.
• Output data window comparator allows automatic range checking.
• Two tracking mode options with programmable tracking time.
• Conversion complete and window compare interrupts supported.
• Flexible output data formatting.
• Voltage reference selectable from external reference pin, on-chip precision reference (driven externally on reference pin), or VDD
supply.
• Integrated temperature sensor.
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EFM8UB2 Data Sheet
System Overview
Low Current Comparators (CMP0, CMP1)
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator module includes the following features:
• Up to 5 external positive inputs.
• Up to 5 external negative inputs.
• Synchronous and asynchronous outputs can be routed to pins via crossbar.
• Programmable hysteresis between 0 and +/-20 mV.
• Programmable response time.
• Interrupts generated on rising, falling, or both edges.
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• USB reset
3.9 Debugging
The EFM8UB2 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
3.10 Bootloader
All devices come pre-programmed with a USB bootloader. This bootloader resides in flash and can be erased if it is not needed.
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EFM8UB2 Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 4.1 Recommended Operating Conditions on page
9, unless stated otherwise.
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Operating Supply Voltage on VDD
VDD
Test Condition
Min
Typ
Max
Unit
2.72
3.3
3.6
V
2.7
—
5.25
V
0
—
48
MHz
-40
—
85
°C
Min
Typ
Max
Unit
FSYSCLK = 48 MHz2
—
12
14
mA
FSYSCLK = 24 MHz2
—
7
8
mA
FSYSCLK = 80 kHz3
—
280
—
μA
FSYSCLK = 48 MHz2
—
6.5
8
mA
FSYSCLK = 24 MHz2
—
3.5
5
mA
FSYSCLK = 80 kHz3
—
220
—
μA
LFO Running
—
105
—
μA
LFO Stopped
—
100
—
μA
Operating Supply Voltage on VRE- VREGIN
GIN
System Clock Frequency
fSYSCLK
Operating Ambient Temperature
TA
Note:
1. All voltages with respect to GND
2. The USB specification requires 3.0 V minimum supply voltage.
Table 4.2. Power Consumption
Parameter
Symbol
Test Condition
Digital Core Supply Current
Normal Mode-Full speed with code IDD
executing from flash
Idle Mode—Core halted with peripherals running
IDD
Suspend Mode-Core halted and
high frequency clocks stopped,
Supply monitor off. Regulators in
low-power mode.
IDD
Stop Mode—Core halted and all
clocks stopped, Regulators in lowpower mode, Supply monitor off.
IDD
—
100
—
μA
Shutdown Mode—Core halted and
all clocks stopped,Regulators Off,
Supply monitor off.
IDD
—
0.25
—
μA
—
900
—
μA
—
5
—
μA
Analog Peripheral Supply Currents
High-Frequency Oscillator 0
IHFOSC0
Operating at 48 MHz,
TA = 25 °C
Low-Frequency Oscillator
ILFOSC
Operating at 80 kHz,
TA = 25 °C
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EFM8UB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
ADC0 Supply Current
IADC
Operating at 500 ksps
Min
Typ
Max
Unit
—
750
1000
μA
VDD = 3.0 V
On-chip Precision Reference
IVREFP
—
75
—
µA
Temperature Sensor
ITSENSE
—
35
—
μA
Comparator 0 (CMP0, CMP1)
ICMP
CPMD = 11
—
1
—
μA
CPMD = 10
—
4
—
μA
CPMD = 01
—
10
—
μA
CPMD = 00
—
20
—
μA
—
15
50
μA
Both Regulators in Normal Mode
—
200
—
μA
Both Regulators in Low Power
Mode
—
100
—
μA
5 V Regulator Off, Internal LDO in
Low Power Mode
—
150
—
μA
Active
—
8
—
mA
Voltage Supply Monitor (VMON0)
IVMON
Regulator Bias Currents
IVREG
USB (USB0) Full-Speed
IUSB
Note:
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increases supply current by the specified amount.
2. Includes supply current from regulators, supply monitor, and High Frequency Oscillator.
3. Includes supply current from regulators, supply monitor, and Low Frequency Oscillator.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
VDD Supply Monitor Threshold
VVDDM
VDD Ramp Time
tRMP
Reset Delay from non-POR source tRST
RST Low Time to Generate Reset
tRSTL
Missing Clock Detector Response
Time (final rising edge to reset)
tMCD
Test Condition
Min
Typ
Max
Unit
2.60
2.65
2.70
V
Time to VDD > 2.7 V
—
—
1
ms
Time between release of reset
source and code execution
—
—
250
μs
15
—
—
μs
80
580
800
μs
—
—
100
μs
Min
Typ
Max
Units
FSYSCLK >1 MHz
VDD Supply Monitor Turn-On Time tMON
Table 4.4. Flash Memory
Parameter
Symbol
Test Condition
Write Time1
tWRITE
One Byte
10
15
20
μs
Erase Time1
tERASE
One Page
10
15
22.5
ms
VDD Voltage During Programming2 VPROG
2.7
—
3.6
V
Endurance (Write/Erase Cycles)
10k
100k
—
Cycles
NWE
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EFM8UB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Note:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM).
3. Data Retention Information is published in the Quarterly Quality and Reliability Report.
Table 4.5. Internal Oscillators
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
47.3
48
48.7
MHz
—
110
—
ppm/V
TSHFOSC0 VDD = 3.0 V
—
25
—
ppm/°C
Oscillator Frequency
fLFOSC
75
80
85
kHz
Power Supply Sensitivity
PSSLFOSC TA = 25 °C
—
0.05
—
%/V
Temperature Sensitivity
TSLFOSC
—
65
—
ppm/°C
Min
Typ
Max
Unit
0.02
—
30
MHz
Min
Typ
Max
Unit
0
—
48
MHz
Min
Typ
Max
Unit
High Frequency Oscillator 0 (48 MHz)
Oscillator Frequency
fHFOSC0
Full Temperature and Supply
Range
Power Supply Sensitivity
PSSHFOS
TA = 25 °C
C0
Temperature Sensitivity
Low Frequency Oscillator (80 kHz)
Full Temperature and Supply
Range
VDD = 3.0 V
Table 4.6. Crystal Oscillator
Parameter
Symbol
Crystal Frequency
fXTAL
Test Condition
Table 4.7. External Clock Input
Parameter
Symbol
External Input CMOS Clock
fCMOS
Test Condition
Frequency (at EXTCLK pin)
Table 4.8. ADC
Parameter
Symbol
Resolution
Nbits
Throughput Rate
fS
Tracking Time
Test Condition
10
Bits
—
—
500
ksps
tTRK
300
—
—
ns
SAR Clock Frequency
fSAR
—
—
8.33
MHz
Conversion Time
tCNV
13
—
—
Clocks
Sample/Hold Capacitor
CSAR
—
30
—
pF
Input Mux Impedance
RMUX
—
5
—
kΩ
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EFM8UB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Voltage Reference Range
VREF
Input Voltage Range1
VIN
Test Condition
Min
Typ
Max
Unit
1
—
VDD
V
0
—
VREF
V
-VREF
—
VREF
V
PSRRADC
—
70
—
dB
Integral Nonlinearity
INL
—
±0.5
±1
LSB
Differential Nonlinearity (Guaranteed Monotonic)
DNL
—
±0.5
±1
LSB
Offset Error
EOFF
-2
0
2
LSB
Offset Temperature Coefficient
TCOFF
—
0.005
—
LSB/°C
Slope Error
EM
—
-0.2
±0.5
%
Single-Ended (AIN+ - GND)
Differential (AIN+ - AIN-)
Power Supply Rejection Ratio
DC Performance, VREF = 2.4 V
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, VREF = 2.4 V
Signal-to-Noise
SNR
55
58
—
dB
Signal-to-Noise Plus Distortion
SNDR
55
58
—
dB
Total Harmonic Distortion (Up to
5th Harmonic)
THD
—
-73
—
dB
Spurious-Free Dynamic Range
SFDR
—
78
—
dB
Note:
1. Absolute input pin voltage is limited by the VDD and GND supply pins.
Table 4.9. Voltage Reference
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Voltage
VREFP
T = 25 °C
2.38
2.42
2.46
V
Turn-on Time, settling to 0.5 LSB
tVREFP
4.7 µF tantalum + 0.1 µF ceramic
bypass on VREF pin
—
3
—
ms
0.1 µF ceramic bypass on VREF
pin
—
100
—
µs
Load = 0 to 200 µA to GND
—
360
—
µV / µA
On-chip Precision Reference
Load Regulation
LRVREFP
Short-circuit current
ISCVREFP
—
—
8
mA
Power Supply Rejection
PSRRVRE
—
140
—
ppm/V
—
9
—
μA
FP
External Reference
Input Current
IEXTREF
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EFM8UB2 Data Sheet
Electrical Specifications
Table 4.10. Temperature Sensor
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Offset
VOFF
TA = 0 °C
—
764
—
mV
Offset Error1
EOFF
TA = 0 °C
—
15
—
mV
Slope
M
—
2.87
—
mV/°C
Slope Error1
EM
—
120
—
μV/°C
Linearity
—
0.5
—
°C
Turn-on Time
—
1.8
—
μs
Min
Typ
Max
Unit
2.7
—
5.25
V
3.0
3.3
3.6
V
—
—
100
mA
Note:
1. Represents one standard deviation from the mean.
Table 4.11. 5V Voltage Regulator
Parameter
Symbol
Input Voltage Range1
VREGIN
Output Voltage on VDD2
VREGOUT
Output Current2
IREGOUT
Test Condition
Output Current = 1 to 100 mA
Note:
1. Input range specified for regulation. When an external regulator is used, VREGIN should be tied to VDD.
2. Output current is total regulator output, including any current required by the device.
Table 4.12. Comparators
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Response Time, CPMD = 00
(Highest Speed)
tRESP0
+100 mV Differential
—
100
—
ns
-100 mV Differential
—
250
—
ns
Response Time, CPMD = 11 (Low- tRESP3
est Power)
+100 mV Differential
—
1.05
—
μs
-100 mV Differential
—
5.2
—
μs
Positive Hysteresis
CPHYP = 00
—
0.4
—
mV
CPHYP = 01
—
8
—
mV
CPHYP = 10
—
16
—
mV
CPHYP = 11
—
32
—
mV
CPHYN = 00
—
-0.4
—
mV
CPHYN = 01
—
-8
—
mV
CPHYN = 10
—
-16
—
mV
CPHYN = 11
—
-32
—
mV
HYSCP+
Mode 0 (CPMD = 00)
Negative Hysteresis
HYSCP-
Mode 0 (CPMD = 00)
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EFM8UB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Positive Hysteresis
HYSCP+
Mode 1 (CPMD = 01)
Negative Hysteresis
HYSCP-
Mode 1 (CPMD = 01)
Positive Hysteresis
HYSCP+
Mode 2 (CPMD = 10)
Negative Hysteresis
HYSCP-
Mode 2 (CPMD = 10)
Positive Hysteresis
HYSCP+
Mode 3 (CPMD = 11)
Negative Hysteresis
HYSCP-
Mode 3 (CPMD = 11)
Min
Typ
Max
Unit
CPHYP = 00
—
0.5
—
mV
CPHYP = 01
—
6
—
mV
CPHYP = 10
—
12
—
mV
CPHYP = 11
—
24
—
mV
CPHYN = 00
—
-0.5
—
mV
CPHYN = 01
—
-6
—
mV
CPHYN = 10
—
-12
—
mV
CPHYN = 11
—
-24
—
mV
CPHYP = 00
—
0.7
—
mV
CPHYP = 01
—
4.5
—
mV
CPHYP = 10
—
9
—
mV
CPHYP = 11
—
18
—
mV
CPHYN = 00
—
-0.6
—
mV
CPHYN = 01
—
-4.5
—
mV
CPHYN = 10
—
-9
—
mV
CPHYN = 11
—
-18
—
mV
CPHYP = 00
—
1.5
—
mV
CPHYP = 01
—
4
—
mV
CPHYP = 10
—
8
—
mV
CPHYP = 11
—
16
—
mV
CPHYN = 00
—
-1.5
—
mV
CPHYN = 01
—
-4
—
mV
CPHYN = 10
—
-8
—
mV
CPHYN = 11
—
-16
—
mV
Input Range (CP+ or CP-)
VIN
-0.25
—
VDD+0.25
V
Input Pin Capacitance
CCP
—
7.5
—
pF
Common-Mode Rejection Ratio
CMRRCP
—
60
—
dB
Power Supply Rejection Ratio
PSRRCP
—
60
—
dB
Input Offset Voltage
VOFF
-10
0
10
mV
Min
Typ
Max
Unit
TA = 25 °C
Table 4.13. Port I/O
Parameter
Symbol
Test Condition
Output High Voltage
VOH
IOH = -3 mA
VDD - 0.7
—
—
V
IOH = -10 μA
VDD - 0.1
—
—
V
IOL = 8.5 mA
—
—
0.6
V
IOL = 10 μA
—
—
0.1
V
2.0
—
—
V
Output Low Voltage
Input High Voltage
VOL
VIH
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EFM8UB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Input Low Voltage
Test Condition
Min
Typ
Max
Unit
VIL
—
—
0.8
V
Pin Capacitance
CIO
—
7
—
pF
Weak Pull-Up Current
IPU
VDD = 3.6
-50
-15
—
μA
Input Leakage (Pullups off or Analog)
ILK
GND < VIN < VDD
-1
—
1
μA
Input Leakage Current with VIN
above VDD
ILK
VDD < VIN < VDD+2.0 V
0
5
150
μA
(VIN = 0 V)
Table 4.14. USB Transceiver
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output High Voltage
VOH
VDD ≥3.0V
2.8
—
—
V
Output Low Voltage
VOL
VDD ≥3.0V
—
—
0.8
V
Output Crossover Point
VCRS
1.3
—
2.0
V
Output Impedance
ZDRV
Driving High
—
38
—
Ω
Driving Low
—
38
—
1.425
1.5
1.575
kΩ
Low Speed
75
—
300
ns
Full Speed
4
—
20
ns
Low Speed
75
—
300
ns
Full Speed
4
—
20
ns
Transmitter
Pull-up Resistance
RPU
Full Speed (D+ Pull-up)
Low Speed (D- Pull-up)
Output Rise Time
Output Fall Time
TR
TF
Receiver
Differential Input
V
VDI
| (D+) - (D-) |
0.2
—
—
V
0.8
—
2.5
V
—
<1.0
—
μA
Sensitivity
Differential Input Common Mode
Range
VCM
Input Leakage Current
IL
Pullups Disabled
Refer to the USB Specification for timing diagrams and symbol definitions.
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EFM8UB2 Data Sheet
Electrical Specifications
4.2 Thermal Conditions
Table 4.15. Thermal Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Thermal Resistance
θJA
QFP48 Packages
─
60
─
°C/W
QFP32 Packages
─
80
─
°C/W
QFN32 Packages
─
28
─
°C/W
Note:
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
4.3 Absolute Maximum Ratings
Stresses above those listed in Table 4.16 Absolute Maximum Ratings on page 16 may cause permanent damage to the device. This
is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For
more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/
support/quality/pages/default.aspx.
Table 4.16. Absolute Maximum Ratings
Parameter
Symbol
Ambient Temperature Under Bias
Test Condition
Min
Max
Unit
TBIAS
-55
125
°C
Storage Temperature
TSTG
-65
150
°C
Voltage on VDD
VDD
GND-0.3
4.2
V
Voltage on VREGIN
VREGIN
GND-0.3
5.8
V
Voltage on I/O, RSTb, or VBUS pins
VIN
VDD > 2.2 V
GND-0.3
5.8
V
VDD < 2.2 V
GND-0.3
VDD+3.6
V
Total Current Sunk into Supply Pin
IVDD
─
500
mA
Total Current Sourced out of Ground
Pin
IGND
500
─
mA
Current Sourced or Sunk by any I/O
Pin or RSTb
IIO
-100
100
mA
Note:
1. Exposure to maximum rating conditions for extended periods may affect device reliability.
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EFM8UB2 Data Sheet
Electrical Specifications
4.4 Typical Performance Curves
Figure 4.1. Typical Operating Supply Current using HFOSC0
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EFM8UB2 Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Figure 5.1 Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered) on page 18 shows a typical connection diagram for the power pins of the EFM8UB2 devices when the internal regulator used and USB is connected (bus-powered).
The VBUS signal is used to detect when USB is connected to a host device.
EFM8UB2 Device
USB 5 V (in)
VBUS
1 µF and 0.1 µF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
3.3 V (out)
VREGIN
Voltage
Regulator
VDD
GND
Figure 5.1. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered)
Figure 5.2 Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered) on page 19 shows a typical connection diagram for the power pins of the EFM8UB2 devices when the internal regulator used and USB is connected (self-powered).
The VBUS signal is used to detect when USB is connected to a host device and is shown with a resistor divider. This resistor divider (or
functionally-equivalent circuit) on VBUS is required to meet the absolute maximum voltage on VBUS specification for self-powered systems where VDD and VIO may be unpowered when VBUS is connected to 5 V.
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EFM8UB2 Data Sheet
Typical Connection Diagrams
USB 5 V
(sense)
24 k
EFM8UB2 Device
47 k
3.6-5.25 V (in)
VBUS
3.3 V (out)
1 µF and 0.1 µF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
VREGIN
Voltage
Regulator
VDD
GND
Figure 5.2. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered)
5.2 USB
Figure 5.3 Connection Diagram for USB Pins on page 19 shows a typical connection diagram for the USB pins of the EFM8UB2 devices including ESD protection diodes on the USB pins.
EFM8UB2 Device
VBUS
USB
Connector
VBUS
D+
D+
D-
USB
D-
Signal GND
SP0503BAHT or
equivalent USB ESD
protection diodes
GND
Figure 5.3. Connection Diagram for USB Pins
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EFM8UB2 Data Sheet
Typical Connection Diagrams
5.3 Voltage Reference (VREF)
Figure 5.4 Connection Diagram for Internal Voltage Reference on page 20 shows a typical connection diagram for the voltage reference (VREF) pin of the EFM8UB2 devices when using the internal voltage reference. When using an external voltage reference, consult the external reference data sheet for connection recommendations.
EFM8UB2 Device
2.42 V (out)
0.1 µF capacitor required,
additional 4.7 µF capacitor
optional for internal
voltage reference
VREF
Voltage
Reference
GND
Figure 5.4. Connection Diagram for Internal Voltage Reference
5.4 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN203: "8-bit MCU Printed
Circuit Board Design Notes" contains detailed information on these connections. Application Notes can be accessed on the Silicon
Labs website (www.silabs.com/8bit-appnotes).
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EFM8UB2 Data Sheet
Pin Definitions
6. Pin Definitions
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
48
47
46
45
44
43
42
41
40
39
38
37
6.1 EFM8UB2x-QFP48 Pin Definitions
P0.5
1
36
P2.2
P0.4
2
35
P2.3
P0.3
3
34
P2.4
P0.2
4
33
P2.5
P0.1
5
32
P2.6
P0.0
6
31
P2.7
GND
7
30
P3.0
D+
8
29
P3.1
D-
9
28
P3.2
VDD
10
27
P3.3
VREGIN
11
26
P3.4
VBUS
12
25
P3.5
13
14
15
16
17
18
19
20
21
22
23
24
RSTb / C2CK
C2D
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
P3.7
P3.6
48 Pin QFP
Figure 6.1. EFM8UB2x-QFP48 Pinout
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EFM8UB2 Data Sheet
Pin Definitions
Table 6.1. Pin Definitions for EFM8UB2x-QFP48
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
P0.5
Multifunction I/O
Yes
UART0_RX
Number
1
Analog Functions
INT0.5
INT1.5
2
3
P0.4
P0.3
Multifunction I/O
Multifunction I/O
Yes
Yes
UART0_TX
ADC0P.18
INT0.4
ADC0N.18
INT1.4
CMP0N.4
INT0.3
ADC0P.17
INT1.3
ADC0N.17
CMP0P.4
4
P0.2
Multifunction I/O
Yes
INT0.2
INT1.2
5
P0.1
Multifunction I/O
Yes
INT0.1
INT1.1
6
P0.0
Multifunction I/O
Yes
INT0.0
INT1.0
7
GND
Ground
8
D+
USB Data Positive
9
D-
USB Data Negative
10
VDD
Supply Power Input /
5V Regulator Output
11
VREGIN
5V Regulator Input
12
VBUS
USB VBUS Sense Input
13
RST /
Active-low Reset /
C2CK
C2 Debug Clock
14
C2D
C2 Debug Data
15
P4.7
Multifunction I/O
16
P4.6
Multifunction I/O
VBUS
EMIF_D7
ADC0P.34
EMIF_AD7m
ADC0N.34
EMIF_D6
ADC0P.15
EMIF_AD6m
ADC0N.15
CMP1N.3
17
P4.5
Multifunction I/O
EMIF_D5
ADC0P.14
EMIF_AD5m
ADC0N.14
CMP1P.3
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
P4.4
Multifunction I/O
Crossbar Capability
Number
18
Additional Digital
Functions
Analog Functions
EMIF_D4
ADC0P.13
EMIF_AD4m
ADC0N.13
CMP0N.3
19
P4.3
Multifunction I/O
EMIF_D3
ADC0P.12
EMIF_AD3m
ADC0N.12
CMP0P.3
20
21
22
P4.2
P4.1
P4.0
Multifunction I/O
Multifunction I/O
Multifunction I/O
EMIF_D2
ADC0P.33
EMIF_AD2m
ADC0N.33
EMIF_D1
ADC0P.32
EMIF_AD1m
ADC0N.32
EMIF_D0
ADC0P.11
EMIF_AD0m
ADC0N.11
CMP1N.2
23
P3.7
Multifunction I/O
Yes
EMIF_A7
ADC0P.10
EMIF_A15m
ADC0N.10
CMP1P.2
24
25
P3.6
P3.5
Multifunction I/O
Multifunction I/O
Yes
Yes
EMIF_A6
ADC0P.29
EMIF_A14m
ADC0N.29
EMIF_A5
ADC0P.9
EMIF_A13m
ADC0N.9
CMP0N.2
26
P3.4
Multifunction I/O
Yes
EMIF_A4
ADC0P.8
EMIF_A12m
ADC0N.8
CMP0P.2
27
28
29
P3.3
P3.2
P3.1
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
EMIF_A3
ADC0P.28
EMIF_A11m
ADC0N.28
EMIF_A2
ADC0P.27
EMIF_A10m
ADC0N.27
EMIF_A1
ADC0P.7
EMIF_A9m
ADC0N.7
CMP1N.1
30
P3.0
Multifunction I/O
Yes
EMIF_A0
ADC0P.6
EMIF_A8m
ADC0N.6
CMP1P.1
31
P2.7
Multifunction I/O
Yes
EMIF_A15
ADC0P.26
ADC0N.26
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P2.6
Multifunction I/O
Yes
EMIF_A14
ADC0P.5
Number
32
ADC0N.5
CMP0N.1
33
P2.5
Multifunction I/O
Yes
EMIF_A13
ADC0P.4
ADC0N.4
CMP0P.1
34
P2.4
Multifunction I/O
Yes
EMIF_A12
ADC0P.25
ADC0N.25
35
P2.3
Multifunction I/O
Yes
EMIF_A11
ADC0P.3
ADC0N.3
CMP1N.0
36
P2.2
Multifunction I/O
Yes
EMIF_A10
ADC0P.2
ADC0N.2
CMP1P.0
37
P2.1
Multifunction I/O
Yes
EMIF_A9
ADC0P.1
ADC0N.1
CMP0N.0
38
P2.0
Multifunction I/O
Yes
EMIF_A8
ADC0P.0
ADC0N.0
CMP0P.0
39
P1.7
Multifunction I/O
Yes
EMIF_WRb
ADC0P.24
ADC0N.24
40
P1.6
Multifunction I/O
Yes
EMIF_RDb
ADC0P.23
ADC0N.23
41
P1.5
Multifunction I/O
Yes
VREF
42
P1.4
Multifunction I/O
Yes
CNVSTR
43
P1.3
Multifunction I/O
Yes
EMIF_ALEm
ADC0P.22
ADC0N.22
44
P1.2
Multifunction I/O
Yes
ADC0P.20
ADC0N.20
CMP1N.4
45
P1.1
Multifunction I/O
Yes
ADC0P.19
ADC0N.19
CMP1P.4
46
P1.0
Multifunction I/O
Yes
ADC0P.21
ADC0N.21
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
P0.7
Multifunction I/O
Yes
XTAL2
Number
47
Analog Functions
EXTCLK
INT0.7
INT1.7
48
P0.6
Multifunction I/O
Yes
XTAL1
INT0.6
INT1.6
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EFM8UB2 Data Sheet
Pin Definitions
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
30
29
28
27
26
25
31
P0.2
P0.3
32
6.2 EFM8UB2x-QFP32 Pin Definitions
P0.1
P0.0
1
24
2
23
P1.2
P1.3
GND
3
22
P1.4
D+
4
21
P1.5
D-
5
20
P1.6
VDD
6
19
P1.7
VREGIN
7
18
P2.0
VBUS
8
17
P2.1
11
12
13
14
15
16
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
10
RSTb / C2CK
P3.0 / C2D
9
32 Pin QFP
Figure 6.2. EFM8UB2x-QFP32 Pinout
Table 6.2. Pin Definitions for EFM8UB2x-QFP32
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.1
Multifunction I/O
Yes
INT0.1
ADC0P.18
INT1.1
ADC0N.18
Number
1
CMP0N.4
2
P0.0
Multifunction I/O
Yes
INT0.0
ADC0P.17
INT1.0
ADC0N.17
CMP0P.4
3
GND
Ground
4
D+
USB Data Positive
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
5
D-
USB Data Negative
6
VDD
Supply Power Input /
Crossbar Capability
Number
Additional Digital
Functions
Analog Functions
5V Regulator Output
7
VREGIN
5V Regulator Input
8
VBUS
USB VBUS Sense Input
9
RST /
Active-low Reset /
C2CK
C2 Debug Clock
P3.0 /
Multifunction I/O /
C2D
C2 Debug Data
P2.7
Multifunction I/O
10
11
VBUS
Yes
ADC0P.16
ADC0N.16
Yes
ADC0P.15
ADC0N.15
12
P2.6
Multifunction I/O
Yes
ADC0P.14
ADC0N.14
13
P2.5
Multifunction I/O
Yes
ADC0P.13
ADC0N.13
CMP0N.3
14
P2.4
Multifunction I/O
Yes
ADC0P.12
ADC0N.12
CMP0P.3
15
P2.3
Multifunction I/O
Yes
ADC0P.11
ADC0N.11
CMP1N.2
16
P2.2
Multifunction I/O
Yes
ADC0P.10
ADC0N.10
CMP1P.2
17
P2.1
Multifunction I/O
Yes
ADC0P.9
ADC0N.9
CMP0N.2
18
P2.0
Multifunction I/O
Yes
ADC0P.8
ADC0N.8
CMP0P.2
19
P1.7
Multifunction I/O
Yes
ADC0P.7
ADC0N.7
CMP1N.1
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
P1.6
Multifunction I/O
Yes
Number
20
Additional Digital
Functions
Analog Functions
ADC0P.6
ADC0N.6
CMP1P.1
21
P1.5
Multifunction I/O
Yes
ADC0P.5
ADC0N.5
CMP0N.1
22
P1.4
Multifunction I/O
Yes
ADC0P.4
ADC0N.4
CMP0P.1
23
P1.3
Multifunction I/O
Yes
ADC0P.3
ADC0N.3
CMP1N.0
24
P1.2
Multifunction I/O
Yes
ADC0P.2
ADC0N.2
CMP1P.0
25
P1.1
Multifunction I/O
Yes
ADC0P.1
ADC0N.1
CMP0N.0
26
P1.0
Multifunction I/O
Yes
ADC0P.0
ADC0N.0
CMP0P.0
27
P0.7
Multifunction I/O
Yes
INT0.7
VREF
INT1.7
28
P0.6
Multifunction I/O
Yes
CNVSTR
INT0.6
INT1.6
29
30
31
P0.5
P0.4
P0.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
INT0.5
ADC0P.20
INT1.5
ADC0N.20
UART0_RX
CMP1N.4
INT0.4
ADC0P.19
INT1.4
ADC0N.19
UART0_TX
CMP1P.4
EXTCLK
INT0.3
INT1.3
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
P0.2
Multifunction I/O
Yes
INT0.2
Number
32
Analog Functions
INT1.2
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Rev. 1.2 | 29
EFM8UB2 Data Sheet
Pin Definitions
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
32
31
30
29
28
27
26
25
6.3 EFM8UB2x-QFN32 Pin Definitions
P0.1
1
24
P1.2
P0.0
2
23
P1.3
GND
3
22
P1.4
D+
4
21
P1.5
D-
5
20
P1.6
VDD
6
19
P1.7
VREGIN
7
18
P2.0
17
P2.1
32 pin QFN
(Top View)
GND
15
16
P2.2
14
P2.4
P2.3
13
P2.5
11
P2.7
12
10
P3.0 / C2D
P2.6
9
8
RSTb / C2CK
VBUS
Figure 6.3. EFM8UB2x-QFN32 Pinout
Table 6.3. Pin Definitions for EFM8UB2x-QFN32
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.1
Multifunction I/O
Yes
INT0.1
ADC0P.18
INT1.1
ADC0N.18
Number
1
CMP0N.4
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.0
Multifunction I/O
Yes
INT0.0
ADC0P.17
INT1.0
ADC0N.17
Number
2
CMP0P.4
3
GND
Ground
4
D+
USB Data Positive
5
D-
USB Data Negative
6
VDD
Supply Power Input /
5V Regulator Output
7
VREGIN
5V Regulator Input
8
VBUS
USB VBUS Sense Input
9
RST /
Active-low Reset /
C2CK
C2 Debug Clock
P3.0 /
Multifunction I/O /
C2D
C2 Debug Data
P2.7
Multifunction I/O
10
11
VBUS
Yes
ADC0P.16
ADC0N.16
Yes
ADC0P.15
ADC0N.15
12
P2.6
Multifunction I/O
Yes
ADC0P.14
ADC0N.14
13
P2.5
Multifunction I/O
Yes
ADC0P.13
ADC0N.13
CMP0N.3
14
P2.4
Multifunction I/O
Yes
ADC0P.12
ADC0N.12
CMP0P.3
15
P2.3
Multifunction I/O
Yes
ADC0P.11
ADC0N.11
CMP1N.2
16
P2.2
Multifunction I/O
Yes
ADC0P.10
ADC0N.10
CMP1P.2
17
P2.1
Multifunction I/O
Yes
ADC0P.9
ADC0N.9
CMP0N.2
18
P2.0
Multifunction I/O
Yes
ADC0P.8
ADC0N.8
CMP0P.2
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EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
P1.7
Multifunction I/O
Yes
Number
19
Additional Digital
Functions
Analog Functions
ADC0P.7
ADC0N.7
CMP1N.1
20
P1.6
Multifunction I/O
Yes
ADC0P.6
ADC0N.6
CMP1P.1
21
P1.5
Multifunction I/O
Yes
ADC0P.5
ADC0N.5
CMP0N.1
22
P1.4
Multifunction I/O
Yes
ADC0P.4
ADC0N.4
CMP0P.1
23
P1.3
Multifunction I/O
Yes
ADC0P.3
ADC0N.3
CMP1N.0
24
P1.2
Multifunction I/O
Yes
ADC0P.2
ADC0N.2
CMP1P.0
25
P1.1
Multifunction I/O
Yes
ADC0P.1
ADC0N.1
CMP0N.0
26
P1.0
Multifunction I/O
Yes
ADC0P.0
ADC0N.0
CMP0P.0
27
P0.7
Multifunction I/O
Yes
INT0.7
VREF
INT1.7
28
P0.6
Multifunction I/O
Yes
CNVSTR
INT0.6
INT1.6
29
30
P0.5
P0.4
Multifunction I/O
Multifunction I/O
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Yes
Yes
INT0.5
ADC0P.20
INT1.5
ADC0N.20
UART0_RX
CMP1N.4
INT0.4
ADC0P.19
INT1.4
ADC0N.19
UART0_TX
CMP1P.4
Rev. 1.2 | 32
EFM8UB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
P0.3
Multifunction I/O
Yes
EXTCLK
Number
31
Analog Functions
INT0.3
INT1.3
32
P0.2
Multifunction I/O
Yes
INT0.2
INT1.2
Center
GND
Ground
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Rev. 1.2 | 33
EFM8UB2 Data Sheet
QFP48 Package Specifications
7. QFP48 Package Specifications
7.1 QFP48 Package Dimensions
Figure 7.1. QFP48 Package Drawing
Table 7.1. QFP48 Package Dimensions
Dimension
Min
Typ
Max
A
—
—
1.20
A1
0.05
—
0.15
A2
0.95
1.00
1.05
b
0.17
0.22
0.27
D
9.00 BSC
D1
7.00 BSC
e
0.50 BSC
E
9.00 BSC
E1
7.00 BSC
L
0.45
0.60
aaa
0.20
bbb
0.20
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0.75
Rev. 1.2 | 34
EFM8UB2 Data Sheet
QFP48 Package Specifications
Dimension
Min
Typ
ccc
0.08
ddd
0.08
theta
0°
Max
3.5°
7°
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation ABC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8UB2 Data Sheet
QFP48 Package Specifications
7.2 QFP48 PCB Land Pattern
Figure 7.2. QFP48 PCB Land Pattern Drawing
Table 7.2. QFP48 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
8.30
8.40
C2
8.30
8.40
E
0.50 BSC
X1
0.20
0.30
Y1
1.40
1.50
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EFM8UB2 Data Sheet
QFP48 Package Specifications
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
7.3 QFP48 Package Marking
EFM8
PPPPPPPP
TTTTTT
YYWW #
Figure 7.3. QFP48 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8UB2 Data Sheet
QFP32 Package Specifications
8. QFP32 Package Specifications
8.1 QFP32 Package Dimensions
Figure 8.1. QFP32 Package Drawing
Table 8.1. QFP32 Package Dimensions
Dimension
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
D
9.00 BSC
D1
7.00 BSC
e
0.80 BSC
E
9.00 BSC
E1
7.00 BSC
L
aaa
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0.45
0.60
0.75
0.20
Rev. 1.2 | 38
EFM8UB2 Data Sheet
QFP32 Package Specifications
Dimension
Min
Typ
bbb
0.20
ccc
0.10
ddd
0.20
theta
0°
Max
3.5°
7°
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.2 | 39
EFM8UB2 Data Sheet
QFP32 Package Specifications
8.2 QFP32 PCB Land Pattern
Figure 8.2. QFP32 PCB Land Pattern Drawing
Table 8.2. QFP32 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
8.40
8.50
C2
8.40
8.50
E
0.80 BSC
X1
0.40
0.50
Y1
1.25
1.35
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8UB2 Data Sheet
QFP32 Package Specifications
8.3 QFP32 Package Marking
EFM8
PPPPPPPP
TTTTTT
YYWW #
Figure 8.3. QFP32 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8UB2 Data Sheet
QFN32 Package Specifications
9. QFN32 Package Specifications
9.1 QFN32 Package Dimensions
Figure 9.1. QFN32 Package Drawing
Table 9.1. QFN32 Package Dimensions
Dimension
Min
Typ
Max
A
0.80
0.85
0.90
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
5.00 BSC
3.20
3.30
e
0.50 BSC
E
5.00 BSC
3.40
E2
3.20
3.30
3.40
L
0.35
0.40
0.45
aaa
—
—
0.10
bbb
—
—
0.10
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Rev. 1.2 | 42
EFM8UB2 Data Sheet
QFN32 Package Specifications
Dimension
Min
Typ
Max
ddd
—
—
0.05
eee
—
—
0.08
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which
are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.2 | 43
EFM8UB2 Data Sheet
QFN32 Package Specifications
9.2 QFN32 PCB Land Pattern
Figure 9.2. QFN32 PCB Land Pattern Drawing
Table 9.2. QFN32 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
4.80
4.90
C2
4.80
4.90
E
0.50 BSC
X1
0.20
0.30
X2
3.20
3.40
Y1
0.75
0.85
Y2
3.20
3.40
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 3 x 3 array of 1.0 mm x 1.0 mm openings on a 1.2 mm pitch should be used for the center pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8UB2 Data Sheet
QFN32 Package Specifications
9.3 QFN32 Package Marking
EFM8
PPPPPPPP
TTTTTT
YYWW #
Figure 9.3. QFN32 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.2 | 45
EFM8UB2 Data Sheet
Revision History
10. Revision History
10.1 Revision 1.2
Updated the VDD Ramp Time specification in Table 4.3 Reset and Supply Monitor on page 10 to a maximum of 1 ms.
10.2 Revision 1.1
Initial release.
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Rev. 1.2 | 46
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Introduction.
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. 3
3.2 Power
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3.3 I/O.
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3.4 Clocking .
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3.5 Counters/Timers and PWM .
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. 5
3.6 Communications and Other Digital Peripherals .
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. 6
3.7 Analog .
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. 8
3.9 Debugging .
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3.10 Bootloader
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. 8
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Electrical Characteristics .
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4.2 Thermal Conditions .
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.16
4.3 Absolute Maximum Ratings .
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.16
4.4 Typical Performance Curves .
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.17
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .
18
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5.2 USB .
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.19
5.3 Voltage Reference (VREF)
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.20
5.4 Other Connections .
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.20
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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.21
6.2 EFM8UB2x-QFP32 Pin Definitions .
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.26
6.3 EFM8UB2x-QFN32 Pin Definitions .
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.30
7. QFP48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
34
7.1 QFP48 Package Dimensions .
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.34
7.2 QFP48 PCB Land Pattern .
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7.3 QFP48 Package Marking .
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8. QFP32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
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8.1 QFP32 Package Dimensions .
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8.2 QFP32 PCB Land Pattern .
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8.3 QFP32 Package Marking .
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.41
Table of Contents
47
9. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
42
9.1 QFN32 Package Dimensions .
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9.2 QFN32 PCB Land Pattern .
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9.3 QFN32 Package Marking .
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.45
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
10.1 Revision 1.2 .
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10.2 Revision 1.1 .
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.46
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
Table of Contents
48
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