dm00151294

TN1200
Technical note
IPAD™, micro-bump Flip Chip:
package description and recommendations for use
Introduction
This document provides package and usage recommendation information for 200 µm (min.)
pitch Flip Chips. For information on 500 µm Flip Chips, see Application note AN1235. For
information on 400 µm Flip Chips, see Application note AN2348.
The competitive market of portable equipment, notably the mobile phone market, is driven
by a challenging development of highly integrated products. To allow manufacturers of
portable equipment to reduce the dimension of their products, STMicroelectronics has
developed packages with reduced size, thickness and weight in the form of the Flip Chip.
The electrical performance of such components in Flip Chips is improved thanks to shorter
connections than the ones in standard plastic packages (such as TSSOP, SSOP or BGA).
Figure 1. Micro-bumped flip-chip packages
3HULSKHUDO
0DWUL[
3HULSKHUDO
ZLWKRXWFRUQHU
The Flip-Chip package family has been designed to fulfill the same quality levels and the
same reliability performances as standard semiconductor plastic packages. This means
these new Flip-Chip packages should be considered as new surface mount devices which
will be assembled on a printed circuit board (PCB) without any special or additional process
steps required. In particular this package does not require any extra underfill to increase
reliability performances or to protect the device. This package is compatible with existing
pick and place equipment for board mounting. Only lead-free, RoHS compliant Flip Chips
are available in mass production.
This application note addresses the following topics:
• Product description
• Mechanical description
• Packing specifications and labeling description
• Recommended storage and shipping instructions
• Soldering assembly recommendations
• User responsibility and returns
• Changes
• Delivery quantity
• Quality
December 2014
DocID027277 Rev 1
1/16
www.st.com
16
Product description
1
TN1200
Product description
Flip Chips are manufactured with a wafer level process that STMicroelectronics has
developed by attaching solder bumps on I/O pads of the active wafer side, thus allowing
bumped dice to be produced. The I/O contact layout can be either matrix shape or set in
periphery. No redistribution layer is used. This allows parasitic inductances coming from the
redistribution metal tracks to be minimized.
Paste composition is 96.5% Sn, 3% Ag, 0.5% Cu, SAC305. This is fully compatible with
standard lead-free reflow processes. The bump dimension allows the pick and place
process to be compatible with existing equipment (in particular with equipment used for ball
grid array - BGA packages) and makes it also compatible with the PCB design rules used
for standard ICs.
These components are delivered in tape and reel packing with the bumps turned down
(placed on the bottom of the carrier tape cavity). The other face of the component is flat and
allows picking as in the standard SMD packages.
Devices are 100% electrically tested before packing. The product references are marked
on the flat side of the device.
2/16
DocID027277 Rev 1
TN1200
2
Mechanical description
Mechanical description
Mechanical dimensions of Flip Chips are provided through a product example in Figure 2.
Bumps are lead-free. Bump composition is 96.5% Sn, 3% Ag, 0.5% (SAC305) Cu alloy with
a near eutectic melting point of 218 to 227 °C. Die size and bump count are adapted to the
connection requirements.
Figure 2. Mechanical dimensions of a 4 x 2 bump matrix array (sample).
0DWUL[
PP
PP
PPPLQ
PPPLQ
PP
3HULSKHUDO
3HULSKHUDOZLWKRXWFRUQHU
PP
PPPLQ
PP
PPPLQ
PPPLQ
PPPLQ
PPPLQ
PP
7ROHUDQFHV
Note:
'LHVL]H“—P
7RWDOWKLFNQHVV“—P
%XPSVSLWFK“—P
%XPSGLDPHWHU“—P
%XPSKHLJKW“—P
The package height of 290 µm is valid for a die thickness of 200 µm.
The Flip Chip tolerance on bump diameter and bump height are very tight. This constant
bump shape insures a good coplanarity between bumps. Optical measurements performed
through vertical focuses show a bump plus die coplanarity below 50 µm.
The product marking for the flat side is shown on Figure 3 (product example). The Flip Chip
has a pin marker - A1 (see Figure 1) on both the flat side and the bump side so that the
orientation of the component can be easily determined before and after assembly. The dots
marked on the flat side and on the bump side have been designed so that they can be
detected by standard vision systems.
Marking dimensions are linked to the die size.
DocID027277 Rev 1
3/16
16
Packing specifications and labeling description
TN1200
Figure 3. Flip Chip marking example (only for Si and HRSi)
'RW
[[ PDUNLQJ
] PDQXIDFWXULQJ
ORFDWLRQ
\ZZ GDWHFRGH
\ \HDU
ZZ ZHHN
7KLFNQHVV—P
[ [ ]
\ ZZ
• “Dot” used for die thickness > 200 µm
• “LL” used for die thickness < 200 µm
3
Packing specifications and labeling description
Flip Chips are delivered in tape and reel to be fully compatible with standard high volume
SMD components. The features of tape and reel materials are in accordance with
EIA-481-D, IEC 60286-3 and EIA 763 (783) standards. All features not specified in this
section are in accordance with EIA-481-D, IEC 60286-3 and EIA 763 (783) standards.
3.1
Carrier tape
Flip Chips are placed in the carrier tape with their bump side facing the bottom of the cavity
so that the components can be picked-up by their flat side. No flipping of the package is
necessary for mounting on PCB. The products are positioned in the carrier tape with pin A1
on the sprocket hole side. Carrier tape mechanical dimensions are shown in the example in
Figure 4. Standard tape width is 8 mm for die sizes smaller than 3 mm (dimension B0).
Figure 4. Carrier tape example
Dot identifying Pin A1 location
A1 bump location may vary with product layout
2.0
Ø 1.55
4.0
8.0
3.5
Cavity
has center hole
at the bottom
1.27
1.75
0.2
x x z
y ww
x x z
y ww
x x z
y ww
0.67
x x z
y ww
x x z
y ww
x x z
y ww
2.0
0.46
All dimensions are typical values in mm
4/16
User direction of unreeling
DocID027277 Rev 1
x x z
y ww
TN1200
Packing specifications and labeling description
Table 1. Tape cavity sizing
Dimension
Die with both sides
smaller than or equal to 1.5 mm
Die with one side larger than 1.5 mm
A0 and B0
Die side size + 100 µm
Cavity dimensions established to ensure that
component rotation cannot exceed 10° max.
The cavities in the carrier tape have been designed to avoid any damage to the
components. Specific hole is present to improve device stability during sealing and pick up.
The embossed carrier tape is in a black conductive material (surface resistivity within 10E5
and 10E11 ohm/sq). Use of this material protects the component against damage from
electrostatic discharge and ensures the total discharge of the component prior to placement
on the PCB. Conductivity is guaranteed to be constant and not affected by shelf life or
humidity. The material will not break when bent and does not have any residue to rub off,
powder, or flake.
3.2
Cover tape
The carrier tape is sealed with a transparent, antistatic (surface resistivity within 10E5 and
10E11 ohm/sq) polyester film cover tape with a heat activated adhesive. The cover tape
tensile strength is higher than 10 N.
The peeling force of the cover tape is between 0.08 N and 0.5 N in accordance with the
testing method EIA-481-D and IEC 60286-3. Cover tape is peeled back in the direction
opposite to the carrier tape travel; the angle between the cover tape and the carrier tape is
between 165 and 180 degrees and the test is done at a speed of 120 ±10% mm/minute.
3.3
Reels
The sealed carrier tape with the Flip Chip is reeled on seven-inch reels (see Figure 5 for reel
mechanical dimensions). These reels are compliant with EIA-481-D standard. In particular,
they are made of an antistatic polystyrene material. Color of the reel may vary depending on
supplier.
Dice quantity per reel is 10000 (with typical package thickness equal to 380 µm). In
compliance with the IEC 60286-3, each reel contains a maximum of 0.1% empty cavities.
Two successive empty cavities are not allowed. Each reel may contain components coming
from 2 different wafer lots.
Each reel has a minimum leader of 400 mm and a minimum trailer of 160 mm (compliant
with EIA 481-D and IEC 60286-3 standards). The leader makes up a portion of carrier tape
with empty cavities and sealed by cover tape at the beginning of the reel (external side). The
leader is affixed to the last turn of the carrier tape by using adhesive tape. The trailer is at
the end of the reel and consists of empty, sealed cavities (see Figure 6).
DocID027277 Rev 1
5/16
16
Packing specifications and labeling description
TN1200
Figure 5. Seven-inch reel mechanical dimensions.
Material: ANTISTATIC POLYSTYRENE
A
B
C
D
E
W1 (Hub)
180 max
1.5 min
13 +0.5
-0.2
20.2 min
60 min
8.4 +1.5
-0
W2
14.4 max
W3
(external)
8.4 +2.5
-0.5
All dimensions in mm
Figure 6. Leader and trailer
Leader and trailer
Start
End
No components
Components
Top
cover
tape
Trailer
Leader
160mm min .
400mm min.
Sealed with cover tape
User direction of feed
6/16
No components
.
100mm min
DocID027277 Rev 1
TN1200
3.4
Packing specifications and labeling description
Final packing
Each reel is heat sealed under inert atmosphere in a transparent, recyclable and antistatic
polyethylene bag (minimum of 4 mils material thickness).
Reels are then packed in cardboard boxes.
The complete description for packing is shown on Figure 7.
Figure 7. Packing flow chart
dice into
the reel
Reel in a sealed
plastic bag within
inert atmosphere
The reel in its bag is packed in a
cardbox for storage & shipment
3.5
Labeling
To ensure component traceability, labels are stuck on the reels and the cardboard box. The
seven inch reels and the cardboard box are identified by labels including part number,
shipped quantity and traceability references (Figure 8).
The traceability is ensured for each production lot and each shipment lot through the
labeling.
The trace code number printed on the labels ensures backward traceability from the lot
received by the customer at each step of the process - in / out dates and quantity at
diffusion, assembly, test and final store. Likewise, forward traceability is able to trace a lot
history from the wafer fab to the customer’s location.
Figure 8. Example of a reel label
DocID027277 Rev 1
7/16
16
Packing specifications and labeling description
TN1200
Table 2. Parameter reel label
Field
Assembled in
nd
8/16
Field type
Mandatory-Country of origin
Pb-free 2 . Level interconnect
As per JEDEC Standard JESD97
MSL
Mandatory for concerned products as defined in MPI
Moisture Sensitivity Level as per JEDEC J-STD-020
Mandatory for SMD
Bag seal date
For MSL 2 and above, date of vacuum sealing of dry bag
For MSL=1, “Not Moisture Sensitive” must be printed instead
PBT
Peak Package Body Temperature as JEDEC J-STD-020
Mandatory for the SMD
Category
Pb-free category as pr JEDEC Standard JESD97
Mandatory for concerned products as defined in MPI
Eco level
Mandatory for ECOLEVEL devices only as defined in MPI
Type
Mandatory
First line: Not Required
Second line: Raw line product name
Total qty
Mandatory - bulk quantity
Trace code
MandatoryTraceability code with Wafer Fab Production Area Code
Bulk ID
Mandatory- Bulk ID Number, Start with A
Bar code
Mandatory-Bar code area
DocID027277 Rev 1
TN1200
4
Recommended storage, shipping instructions and descriptions
Recommended storage, shipping instructions and
descriptions
Flip-Chip reels are packed under inert N2 atmosphere in a sealed bag. For shipment and
handling, reels are packed in a cardboard box.
STMicroelectronics thus recommends the following shipping and storage conditions:
•
Relative humidity between 15% and 70%
•
Temperature range from -55 °C to +150 °C
Components in a non opened sealed bag can be stored 6 months after shipment.
Components in tape and reel must be protected from exposure to direct sunlight.
Moisture sensitivity level (MSL as per JEDEC J-STD-020C) is not applicable to Flip-Chip
devices since there is no plastic encapsulation and so no risk of moisture absorption and
related possible package cracks.
DocID027277 Rev 1
9/16
16
Soldering assembly recommendations
TN1200
5
Soldering assembly recommendations
5.1
PCB design recommendations for multi-pads Flip Chips
For optimum electrical performance and highly reliable solder joints, STMicroelectronics
recommends the PCB design guidelines for each bumps configuration.
Table 3. PCB design recommendations example.
Note:
PCB pad design
Non solder mask defined
PCB pad size
80 µm / 100 µm maximum
Solder mask
clearance
25 µm minimum
PCB pad finishing
Cu - Ni (2-6 µm) - Au (0.2 µm max) or Cu OSP (Organic Substrate Protection)
A too thick gold layer finishing on the PCB pad is not recommended (low joint reliability).
To optimize the natural self centering effect of Flip Chip on PCB, PCB pad positioning and
size have to be properly designed (see Figure 9).
Figure 9. Footprint
&RSSHUSDG'LDPHWHU
—PUHFRPPHQGHG
—PPD[LPXP
6ROGHUPDVNFOHDUDQFH
—PPLQLPXP
6ROGHUVWHQFLORSHQLQJ
—PUHFRPPHQGHG
6WHQFLOWKLFNQHVV—P
Micro vias
An alternative to routing on the top surface is to route out on buried layers. To achieve this,
the pads are connected to the lower layers using micro vias.
10/16
DocID027277 Rev 1
TN1200
5.2
Soldering assembly recommendations
PCB assembly guidelines
For Flip Chip mounting on the PCB. Flip Chips are fully compatible with the use of near
eutectic 95.8% Sn, 3.5% Ag, 0.7% Cu solder paste with no-clean flux. ST's
recommendations for Flip-Chip board mounting are illustrated on the soldering reflow profile
shown in Figure 10.
Figure 10. ST ECOPACK® recommended soldering reflow profile for Flip-Chip
mounting on PCB (definitions)
240-245 °C
Temperature (°C)
250
-2 °C/s
2 - 3 °C/s
60 sec
(90 max)
200
-3 °C/s
150
-6 °C/s
100
0.9 °C/s
50
Time (s)
0
30
60
90
120
150
180
210
240
270
300
Table 4. ST ECOPACK® recommended soldering reflow profile for Flip Chip mounting
on PCB (value)
Probe
Parameter
#1 PLCC 44
#2 PLCC 28
#3 SO-18
Positive temperature gradient °C/s
4.50
3.94
4.49
Time in positive gradient (min/sec)
00:17
00:13
00:16
Time from 150 to 200 °C (min/sec)
01:22
01:36
01:24
Time above 217 °C (min/sec)
02:05
01:50
02:05
Maximum temperature °C
244.0
239.9
243.6
Temperature difference °C
4.1
Negative temperature gradient °C/s
-3.46
-2.88
-3.97
Dwell time in the soldering zone (with temperature higher than 217 °C) has to be kept as
short as possible to prevent component and substrate damages. Peak temperature must
not exceed 260 °C. Controlled atmosphere (N 2 or N2H2) is recommended during the whole
reflow, specially above 150 °C.
Flip Chips are able to withstand three times the previous recommended reflow profile to be
compatible with a double reflow when SMDs are mounted on both sides of the PCB plus
one additional repair.
A maximum of three soldering reflow are allowed for these lead-free packages (with repair
step included).
The use of a no-clean paste is highly recommended to avoid any cleaning operation. To
prevent any bump cracks, ultrasonic cleaning methods are not recommended.
DocID027277 Rev 1
11/16
16
Soldering assembly recommendations
5.3
TN1200
Underfilling
Underfilling is not essential for Flip Chips. These devices can do without an underfill if the
process temperature does not exceed 175 °C and if the process time is short (typically 5
minutes).
5.4
Manual rework
Flip Chips are able to tolerate one repair in addition to the two reflow mentioned in
Section 5.2.
As for other BGA type packages the use of laser systems is the most suitable form for
Flip Chip repair. Manual hot gas soldering is acceptable but iron soldering is not
recommended.
For leaded Flip Chip manual rework the maximum temperature allowed is 260 °C (lead-free
compatibility) and dwell time must not exceed 30 seconds.
For lead-free Flip Chip manual rework, the maximum temperature allowed is 260 °C. The
typical soldering profile of Figure 10 can be used.
5.4.1
Rework procedure
Remove the device
Rework process start with the removal of the device. To remove the device, heat must be
applied to melt the solder joints so that the component can be lifted from the board.
Large area bottom side preheater may be used to raise the temperature of the board. This
may help to minimize warping of the board, and minimize the amount of heat that must be
applied on the component.
Top heating may be applied to the component by using a laser or a convective hot gas
nozzle. Nozzle size must be selected to match the component footprint appropriately. After
top heating has melted the solder, vacuum is applied through the pick-up nozzle, and the
component is lifted from the board.
The heat should be carefully directed at the component to be removed to avoid adjacent
components solder joints being reflowed. Shielding, control of gas flow from the nozzle, and
accurate temperature control are the key parameters.
Removing solder
Next step is cleaning the solder from the work site. Due to space constraints and the need
for accurate temperature control, automatic tools are recommended.
Typically, site cleaners consist of controlled non-contact gas heating and vacuuming tools.
The objective is to remove the residual solder from the site without damaging the pads,
solder masks or adjacent components, and to prepare the site for application of new
component.
12/16
DocID027277 Rev 1
TN1200
Soldering assembly recommendations
New device soldering
For placement of the device several solutions are possible:
•
Use a mini-stencil and solder paste then place the device. This is the preferred solution
to ensure homogeneity of assembly conditions if assembly of WLCSP (wafer level chip
scale package) is performed with solder paste, even if small footprints and tight
dimensions make this operation difficult.
•
Use no-clean flux on the site and place the device.
•
Dip the WLCSP in no-clean flux, and to place it on the board.
Next operation is to reflow the solder joint by applying controlled heat to the component.
This can be done in much the same way as described above for component removal, but
accurate temperature control is necessary to ensure good soldering of the joint.
Alternatively this can be done by putting the whole board in a furnace. See Figure 11 for
reflow profile recommendations.
Equipment
Systems for these operations are available at various levels of automation. Methods and
techniques used in more sophisticated automatic systems can be copied using manual
equipment. Soldering irons should be avoided for these operations. Tweezers or any picking
tools pressuring the sides or bottom (bump side) of the WLCSP must be avoided since such
tools can damage silicon and create chip outs.
Figure 11 shows an example of semi-automatic equipment for component rework. (See the
Web site of Comintec for more information.)
Figure 11.
Comintec ONYX32 - Semi-automatic equipment for component rework
DocID027277 Rev 1
13/16
16
Changes
TN1200
ONYX32 Key Features
•
Fully automated X,Y, Z and theta control
•
Fully automated alignment using digital feature separation (DFS) technology
•
Precision force sensor and mass flow controller
•
Four zone bottom preheater
•
Flux dipping station
•
Fire-wire (IEEE 1394) controls
•
Visual machines software
•
Machine table including power supply cabinet
ONYX32 Options
6
•
Dispensing head for solder paste, flux, underfill or adhesives
•
Non-contact temperature sensor
•
Site solder removal system
Changes
STMicroelectronics reserves the right to implement minor changes of geometry and
manufacturing processes without prior notice. Such changes will not affect electrical
characteristics of the die, the pad layout or the maximum die size. However for confirmed
orders, no variation will be made without customer’s approval.
7
Quality
7.1
Electrical inspection
Products in Flip Chip are 100% electrically probed according to the critical parameters of the
ST product specification. The last operation before packing is 100% electrical testing. The
other parameters are guaranteed by technology, design rules and by continuous monitoring
systems.
7.2
Visual inspection
A visual control is performed on all manufacturing lots according to the MIL-STD-883
method 2010.
14/16
DocID027277 Rev 1
TN1200
8
Conclusion
Conclusion
Lead-free Flip-Chip packages have been developed by STMicroelectronics for electronic
applications where integration and performance are the main concerns of designers.
STMicroelectronics Flip Chips offer:
•
Remarkable board space saving (package size equal to die size and total height less
than 380 µm)
•
Enhanced electrical performance (minimized parasitic inductance due to very short
electrical paths and absence of redistribution layer)
•
High reliability due to integration of a whole function traditionally based on discrete
interconnected components.
Flip Chips are delivered in tape and reel and are fully compatible with other high volume
SMD components (standard plastic packages or CSP/BGA packages) regarding existing
pick and place equipment, standard solder reflow assembly equipment and standard PCB
techniques.
9
Revision history
Table 5. Document revision history
Date
Revision
10-Dec-2014
1
Changes
Initial release.
DocID027277 Rev 1
15/16
16
TN1200
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
16/16
DocID027277 Rev 1
Similar pages