SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 D D D D D D D D D D D SN54GTL16616 . . . WD PACKAGE SN74GTL16616 . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family Universal Bus Transceiver (UBT ) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode GTL Buffered CLKAB Signal (CLKOUT) Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs Equivalent to ’16601 Function Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Ceramic Flat (WD) Packages OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND CLKIN OEBA LEBA description 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND CLKOUT CLKBA CEBA The ’GTL16616 devices are 17-bit universal 27 30 bus transceivers (UBTs) that provide 28 29 LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clocked-enabled modes of data transfer identical to the ’16601 function. Additionally, they provide for a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and output edge control (OEC). The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, OEC, and UBT are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 description (continued) Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54GTL16616 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74GTL16616 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† INPUTS CEAB OEAB LEAB X H L L L OUTPUT B MODE X Z Isolation X B0‡ B0§ Latched storage of A data CLKAB A X X L H or L L L H or L X X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H B0§ Transparent Clocked storage of A data H L L X X Clock inhibit † A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. ‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low § Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 logic diagram (positive logic) 35 VREF OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA A1 1 56 55 2 28 30 29 27 CE 1D 3 CE 1D C1 CLK 54 C1 CLK B1 1 of 17 Channels 31 CLKIN CLKOUT 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC: 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Notes 4 through 6) SN54GTL16616 SN74GTL16616 MIN NOM MAX MIN NOM MAX 3.3 V 3.15 3.3 3.45 3.15 3.3 3.45 5V 4.75 5 5.25 4.75 5 5.25 GTL 1.14 1.2 1.26 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 1.35 1.5 1.65 GTL 0.74 0.8 0.87 0.74 0.8 0.87 GTL+ 0.87 1 1.1 0.87 1 1.1 VCC Supply voltage VTT Termination voltage VREF Supply voltage VI Input voltage VIH High-level g input voltage B port VIL Low-level input voltage B port IIK Input clamp current IOH High-level output current IOL Low-level output current B port VTT 5.5 Except B port Except B port VREF+50 mV 2 VREF+50 mV 2 VREF –50 mV 0.8 Except B port VTT 5.5 UNIT V V V V V VREF –50 mV 0.8 V –18 –18 mA A port –32 –32 mA A port 64 64 B port 40 40 mA TA Operating free-air temperature –55 125 –40 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH A port ort VOL II IOH = –8 mA IOH = –32 mA IOZL ICC (3 3 V) (3.3 ICC (5 V) Ciio VCC–0.2 VCC–0.2 2.4 2.4 2 0.2 0.4 0.4 IOL = 32 mA IOL = 64 mA 0.5 0.5 0.55 0.55 0.4 Control inputs VCC = 0 or 3.45 V, VCC (5 V) = 0 or 5.25 V VI = 5.5 V 10 10 20 A port VI = 5.5 V VI = VCC (3.3 V) 20 VCC (3 (3.3 3 V) = 3 3.45 45 V, V VCC (5 V) = 5 5.25 25 V 1 1 VI = 0 VI = VCC (3.3 V) –30 –30 VI = 0 VCC = 0, VI or VO = 0 to 4.5 V A port A port B port A port B port A or B port ort A or B ort port VCC (3 (3.3 3 V) = 3 3.15 15 V, V VCC (5 V) = 4 4.75 75 V VI = 0.8 V VI = 2 V A port B port 5 –5 100 100 75 75 –75 –75 1 1 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.2 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.5 V 10 10 –1 –1 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.4 V Outputs high VCC (3.3 V) = 3.45 V, Outputs low VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND Outputs disabled –10 –10 1 1 5 5 1 1 Outputs high 120 120 Outputs low 120 120 Outputs disabled 120 120 1 1 VI = 3.15 V or 0 3.5 VO = 3.15 V or 0 Per IEEE Std 1194.1 12 µA µ µA ±500 3.5 µA µA mA mA mA pF 12 5 V µA ±500 VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, A-port or control inputs at VCC (3.3 V) or GND, One input at 2.7 V Control inputs 5 –5 VI = 0 to VCC (3.3 V)‡ VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 3 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND V 2 0.2 0.4 VCC ((3.3 V)) = 3.45 V,, VCC (5 V) = 5.25 V UNIT V IOL = 40 mA ∆ICC§ Ci –1.2 VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V Ioff IOZH –1.2 IOL = 100 µA IOL = 16 mA VCC ((3.3 V)) = 3.15 V,, VCC (5 V) = 4.75 V SN74GTL16616 TYP† MAX MIN B port B port II(hold) ( ) MIN VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, II = –18 mA VCC (3.3 V)= 3.15 V to 3.45 V, IOH = –100 µA VCC (5 V) = 4.75 V to 5.25 V VCC ((3.3 V)) = 3.15 V,, VCC (5 V) = 4.75 V A port SN54GTL16616 TYP† MAX TEST CONDITIONS 5 pF † All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1) SN54GTL16616 MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time MIN 95 3.3 3.3 CLKAB or CLKBA high or low 5.5 5.5 A before CLKAB↑ 1.3 1.3 B before CLKBA↑ 2.5 2.5 A before LEAB↓ 0 0 B before LEBA↓ 1.1 1.1 CEAB before CLKAB↑ 2.2 2.2 CEBA before CLKBA↑ 2.7 2.7 A after CLKAB↑ 1.6 1.6 B after CLKBA↑ 0.4 0.4 A after LEAB↓ 4 4 B after LEBA↓ 3.5 3.5 CEAB after CLKAB↑ 1.1 1.1 CEBA after CLKBA↑ 0.9 0.9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 95 LEAB or LEBA high PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 MAX SN74GTL16616 UNIT MHz ns ns ns SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tdis ten tr tf tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis FROM (INPUT) TO (OUTPUT) SN54GTL16616 TYP† MAX MIN 95 A B LEAB B CLKAB B CLKAB CLKOUT OEAB B or CLKOUT SN74GTL16616 TYP† MAX UNIT 95 MHz MIN 1.4 3 4.6 1.7 3 4.4 1.2 2.8 4.7 1.4 2.8 4.5 2.1 3.8 5.6 2.3 3.8 5.4 1.9 3.7 5.6 2.2 3.7 5.3 2.2 4 5.9 2.4 4 5.7 1.8 3.7 5.7 2.1 3.7 5.4 4.5 6.1 8.2 4.7 6.1 8.1 5.5 7.9 11.4 5.7 7.9 11.3 2 3.8 5.8 2.1 3.8 5.6 2 3.6 5.2 2.1 3.6 5.1 Transition time, B outputs (0.5 V to 1 V) 1.2 1.2 Transition time, B outputs (1 V to 0.5 V) 0.7 0.7 B A LEBA A CLKBA A CLKOUT CLKIN OEBA A or CLKIN ns ns ns ns ns ns ns 1.6 4 6.8 1.7 4 6.7 1.3 2.9 4.7 1.4 2.9 4.7 2.3 3.8 6.1 2.4 3.8 5.8 1.9 3 4.8 2 3 4.6 2.5 4 6.3 2.6 4 6 2.1 3.4 5.1 2.2 3.4 4.9 7.2 10 14.7 7.4 10 14.4 5.9 8.1 11.8 6.1 8.1 11.7 2.7 5.3 8.1 2.8 5.3 7.8 2.6 4.3 6.7 2.7 4.3 6.4 ns ns ns ns ns † All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1) SN54GTL16616 MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time SN74GTL16616 MIN 95 3.3 3.3 CLKAB or CLKBA high or low 5.5 5.5 A before CLKAB↑ 1.3 1.3 B before CLKBA↑ 2.3 2.3 A before LEAB↓ 0 0 B before LEBA↓ 1.3 1.3 CEAB before CLKAB↑ 2.2 2.2 CEBA before CLKBA↑ 2.7 2.7 A after CLKAB↑ 1.6 1.6 B after CLKBA↑ 0.6 0.6 A after LEAB↓ 4 4 B after LEBA↓ 3.5 3.5 CEAB after CLKAB↑ 1.1 1.1 CEBA after CLKBA↑ 0.9 0.9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 95 LEAB or LEBA high PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 MAX UNIT MHz ns ns ns SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tr tf tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis FROM (INPUT) TO (OUTPUT) SN54GTL16616 TYP† MAX MIN 95 A B LEAB B CLKAB B CLKAB CLKOUT OEAB B or CLKOUT SN74GTL16616 TYP† MAX UNIT 95 MHz MIN 1.4 3 4.6 1.7 3 4.4 1.2 2.9 4.8 1.4 2.9 4.6 2.1 3.8 5.6 2.3 3.8 5.4 1.9 3.7 5.7 2.2 3.7 5.4 2.2 4 5.9 2.4 4 5.7 1.8 3.8 5.8 2.1 3.8 5.5 4.5 6.1 8.2 4.7 6.1 8.1 5.5 8 11.5 5.7 8 11.4 2 3.6 5.2 2.1 3.6 5.1 2 3.8 5.9 2.1 3.8 5.7 Transition time, B outputs (0.5 V to 1 V) 1.4 1.4 Transition time, B outputs (1 V to 0.5 V) 1 1 B A LEBA A CLKBA A CLKOUT CLKIN OEBA A or CLKIN ns ns ns ns ns ns ns 1.5 3.9 6.8 1.6 3.9 6.6 1.2 2.8 4.5 1.3 2.8 4.5 2.3 3.8 6.1 2.4 3.8 5.8 1.9 3 4.8 2 3 4.6 2.5 4 6.3 2.6 4 6 2.1 3.4 5.1 2.2 3.4 4.9 7.1 9.9 14.7 7.3 9.9 14.3 5.8 8 11.6 6 8 11.5 2.7 5.3 8.1 2.8 5.3 7.8 2.6 4.3 6.7 2.7 4.3 6.4 ns ns ns ns ns † All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V , VREF = 0.8 V FOR GTL AND VTT = 1.5 V , VREF = 1 V FOR GTL+ VTT 6V S1 500 Ω From Output Under Test Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH GND CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS tw 3V 3V Input VM V VM V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION (VM = 1.5 V for A port and VREF for B port)† Input (see Note B) 3V 1.5 V 1.5 V tsu th 3V Data Input A Port 1.5 V Data Input B Port VREF 1.5 V 0V VTT VREF 0V 0V tPLH VOLTAGE WAVEFORMS SETUP AND HOLD TIMES tPHL VTT Output VREF VREF VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port)† Input (see Note B) VREF 0V tPLH 1.5 V 1.5 V VOL tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note C) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note C) tPHL VOH Output 1.5 V tPZL VTT VREF 3V Output Control (see Note B) 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port and CLKIN) † All control inputs are TTL levels. NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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