Freescale Semiconductor Data Sheet: Technical Data Document Number: P5021 Rev. 1, 05/2014 P5021 P5021 QorIQ Integrated Processor Data Sheet The P5021 QorIQ integrated communication processor combines two Power Architecture® processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design. The chip includes the following function and features: • Two e5500 Power Architecture cores – Each core has a backside 512 KB L2 cache with ECC – Three levels of instructions: user, supervisor, and hypervisor – Independent boot and reset – Secure boot capability • CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints • Frontside 2 MB CoreNet platform cache with ECC • CoreNet bridges between the CoreNet fabric the I/Os, datapath accelerators, and high and low speed peripheral interfaces • Two 10-Gigabit Ethernet (XAUI) controllers • Ten 1-Gigabit Ethernet controllers – SGMII, 2.5Gb/s SGMII and RGMII interfaces • Two 64-bit DDR3/3L SDRAM memory controllers with ECC • Multicore programmable interrupt controller (PIC) • Four I2C controllers • Four 2-pin UARTs or two 4-pin UARTs • Two 4-channel DMA engines • Enhanced local bus controller (eLBC) • Three PCI Express 2.0 controllers/ports Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2013-2014 Freescale Semiconductor, Inc. All rights reserved. FC-PBGA–1295 37.5 mm × 37.5 mm • • • • • Two serial ATA (SATA) 2.0 controllers Enhanced secure digital host controller (SD/MMC) Enhanced serial peripheral interface (eSPI) Two high-speed USB 2.0 controllers with integrated PHYs RAID 5 and 6 storage accelerator with support for end-to-end data protection information • Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: – Frame Manager (FMan) for packet parsing, classification, and distribution – Queue Manager (QMan) for scheduling, packet sequencing and congestion management – Hardware Buffer Manager (BMan) for buffer allocation and deallocation – Encryption/Decryption • 1295 FC-PBGA package This figure shows the major functional units within the chip. Table of Contents 1 2 Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .3 1.1 1295 FC-PBGA ball layout diagrams . . . . . . . . . . . . . . .3 1.2 Pinout list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .52 2.2 Power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3 Power-down requirements . . . . . . . . . . . . . . . . . . . . . .60 2.4 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .60 2.5 Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.6 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 2.7 RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.8 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .66 2.9 DDR3 and DDR3L SDRAM controller. . . . . . . . . . . . . .66 2.10 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 2.11 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 2.12 Ethernet: data path three-speed Ethernet (dTSEC), management interface, IEEE Std 1588. . . . . . . . . . . . .77 2.13 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 2.14 Enhanced local bus interface (eLBC) . . . . . . . . . . . . . .87 2.15 Enhanced secure digital host controller (eSDHC) . . . .92 2.16 Multicore programmable interrupt controller (MPIC) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.17 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 3 4 5 6 7 2.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.19 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.20 High-speed serial interfaces (HSSI) . . . . . . . . . . . . . 101 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . 129 3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 3.2 Supply power default setting . . . . . . . . . . . . . . . . . . . 136 3.3 Power supply design . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.4 Decoupling recommendations . . . . . . . . . . . . . . . . . . 139 3.5 SerDes block power supply decoupling recommendations 140 3.6 Connection recommendations. . . . . . . . . . . . . . . . . . 140 3.7 Recommended thermal model . . . . . . . . . . . . . . . . . 150 3.8 Thermal management information. . . . . . . . . . . . . . . 150 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.1 Package parameters for the FC-PBGA . . . . . . . . . . . 151 4.2 Mechanical dimensions of the FC-PBGA . . . . . . . . . 152 Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.1 Part numbering nomenclature . . . . . . . . . . . . . . . . . . 153 6.2 Orderable part numbers addressed by this document 154 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 2 Freescale Semiconductor Pin assignments and reset states QorIQ P5021 512 KB backside L2 cache Power Architecture® e5500 Core 32 KB D-cache 32 KB I-cache 1024 KB frontside L3 cache 64-bit 1600 MT/s DDR-3 memory controller 1024 KB frontside L3 cache 64-bit 1600 MT/s DDR-3 memory controller eOpenPIC PreBoot Loader CoreNet™ Coherency Fabric Security Monitor PAMU PAMU PAMU PAMU Frame Manager Frame Manager Parse, classify, distribute Buffer Parse, classify, distribute Buffer PAMU Peripheral access management unit (PAMU) Internal BootROM SPI 2x DUART Test Port/ SAP Security 5.0 Queue Mgr 4x I2Cs RAID5/6 2x USB 2.0 + 2x PHY Buffer Mgr 1GE 1GE 10GE 1GE 1GE 10GE 1GE 1GE 1GE Clocks/Reset 1GE 1GE 1GE Real-time debug Watchpoint cross trigger Perf CoreNet monitor trace SATA 2.0 SD/MMC DMA DMA SATA 2.0 eLBC PCIe PCIe PCIe Power mgmt GPIO RGMII CCSR 18-Lane 5-GHz SerDes SATA SerDes Figure 1. P5021 block diagram 1 Pin assignments and reset states 1.1 1295 FC-PBGA ball layout diagrams These figures show the FC-PBGA ball map diagrams. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 3 Pin assignments and reset states 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 D2_ MDQ 21 D2_ MDQ 20 D2_ MDQ 10 D2_ MDQS 1 D2_ MDQS 1 D2_ MDQ 08 D2_ MDQ 03 D2_ MDQ 07 D2_ MDQS 0 D2_ MDQS 0 D2_ MDQ 01 D2_ MDQ 04 D1_ MDQ 03 D1_ MDQ 06 D1_ MDM 0 D1_ MDQ 00 D2_ MDQ 16 GVDD D2_ MDQ 17 D2_ MDQ 11 D2_ MDM 1 D2_ MDQ 13 GVDD D2_ MDQ 02 D2_ MDQ 06 D2_ MDM 0 D2_ MDQ 05 GVDD D1_ MDQ 07 D1_ MDQS 0 D1_ MDQ 05 D2_ MDQS 2 D2_ MDQ 22 D2_ MDQS 2 D2_ MDQ 12 D1_ MDQ 16 D2_ MDQ 00 D1_ MDQ 02 D1_ MDQS 0 D1_ MDQ 04 GVDD NC_ C19 NC_ C20 D2_ MDQ 23 GVDD D1_ MDQ 01 NC_ D18 LCS 00 LCS 1 LCS 3 E D2_ MDQ 19 NC_ E16 GND LA 28 GND LCS 2 D1_ MDQ 12 LA 31 LA 29 LAD 12 D1_ MDQ 09 GVDD GND LAD 31 A B GND D2_ MDM 2 D2_ MDQ 14 GVDD D2_ MDQ 18 GVDD D2_ MDQ 15 D2_ MDQ 09 GVDD D2_ MDQ 29 D2_ MDQ 28 F RSRV _F1 RSRV _F2 GND G RSRV _G1 RSRV _G2 H D2_ MDQ 31 GVDD J D2_ MECC 0 D2_ MECC 5 D2_ MDQS 8 D2_ MDQS 8 D2_ MDM 8 C D K L M D2_ MBA 2 GND GND GND D1_ MDQ 23 GVDD D1_ MDQ 18 D1_ MDQ 29 GND D1_ MDQS 3 D2_ MDM 3 GVDD D2_ MDQS 3 D2_ MDQS 3 GND D2_ MDQ 30 D2_ MDQ 26 D2_ MDQ 27 D1_ MDQ 30 GVDD D1_ MECC 5 D1_ MECC 4 D2_ MCK 2 D2_ MCK 1 D2_ MCK 1 D1_ MCK 1 D1_ MCK 1 W D2_ MCK 3 D2_ MCK 3 D2_ MCK 0 D2_ MCK 0 D1_ MCK 0 D1_ MCK 0 GND D2_MA 00 GND D2_ MBA 0 D2_ MDIC 0 D1_ MDIC 1 D1_ GVDD MAPAR_ OUT D1_ GVDD D1_MA MBA 10 0 Y AA D2_ GVDD MAPAR_ OUT D2_ D2_MA MBA 10 1 AB D2_ MWE D2_ MCS 2 GVDD D1_ MDQ 36 D1_ MDQ 37 AC D2_ MCS 0 GVDD D2_ MCAS D2_MA 13 GND AD D2_ MODT 2 D2_ MODT 0 GND D1_ MDQS 4 AE D2_ MCS 1 D2_ MCS 3 D2_ MODT 3 GVDD AF D2_ MODT 1 GVDD D2_ MDQ 37 D2_ MDQ 36 AG D2_ MDM 4 D2_ MDQ 33 AH D2_ MDQ 38 D2_ MDQS 4 AJ D2_ MDQ 35 GVDD AK RSRV _AK1 RSRV _AK2 AL RSRV _AL1 RSRV _AL2 AM D2_ MDQ 52 GVDD AN D2_ MDQ 48 D2_ MDQ 53 AP D2_ MDQS 6 D2_ MDM 6 AR D2_ MDQS 6 AT D2_ MDQS 4 D2_ MDQ 34 LAD 04 BVDD GND XVDD SD_TX 01 XVDD SD_TX 03 XGND SD_TX 05 SVDD SD_RX SD_RX 05 05 LA 28 LA 25 GND LAD 11 LAD 07 LAD 06 LA 17 LCS 7 NC_ G27 SD_TX 00 XGND SD_TX 02 XGND XVDD SD_TX 05 SGND SVDD SGND G H SVDD SD_RX SD_RX 07 07 GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL LAD 01 VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND GND VDD_PL GND GND GND GND GND VDD_PL GND VDD_PL GND GND GND GND VDD_PL GND GND GND VDD_PL GND GND GND GND VDD_PL GND VDD_PL GND GND GND GND D1_ MECC 3 GND GVDD VDD_PL D1_ MCKE 0 GND D1_ VDD_PL MCKE 1 GVDD GND D1_MA D1_MA VDD_PL 03 04 D1_MA 00 GND GND GVDD VDD_PL D1_ MBA 1 GND GND D1_ VDD_PL MRAS GND D1_ MODT 0 GND GND SGND SENSEVDD_PL 2 RSRV _L28 XGND XVDD XVDD XGND SD_RX SD_RX 08 08 SVDD VDD_PL GND RSRV _M28 XVDD XGND SD_TX 08 SD_TX 08 SVDD SGND SD_RX SD_RX 09 09 VDD_PL GND VDD_PL RSRV _N28 XGND XGND XVDD XGND SD_TX 09 SD_TX 09 SGND VDD_PL GND VDD_PL GND RSRV _P28 XGND XVDD SD_TX 10 SD_TX 10 XVDD XGND SD_RX SD_RX 10 10 VDD_PL GND VDD_PL GND VDD_PL AVDD_ SRDS4 XVDD XGND XVDD XGND SGND SVDD SVDD SGND R VDD_PL GND VDD_PL GND VDD_PL GND AGND_ SRDS4 XVDD SD_TX 11 SD_TX 11 XVDD SD_RX 11 SD_RX 11 SGND AGND_ SRDS2 T VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL SD_ REF_ CLK4 XGND XVDD XGND SVDD SGND AVDD_ SRDS2 U VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND SD_ REF_ CLK4 XGND XVDD XGND XVDD SD_ REF_ CLK2 SD_ REF_ CLK2 SVDD SGND V GND GND VDD_PL GND VDD_PL GND VDD_PL GND NC_ W27 VDD_PL XVDD XGND SD_TX 12 SD_TX 12 SGND SVDD SD_RX SD_RX 12 12 GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL GND XGND SD_TX 13 SD_TX 13 XVDD XGND SD_RX 13 SD_RX 13 SGND GND GND GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL SD1_IMP_ XVDD CAL_TX XGND SD_TX 14 SD_TX 14 SVDD SGND SD_RX SD_RX 14 14 GND GND GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL GND SD_TX 18 SD_TX 18 XVDD XVDD XGND SD_TX 15 SD_TX 15 SVDD SGND AB GND GND GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL VDD_ LL S1VDD XGND SD_ REF_ CLK3 SD_ REF_ CLK3 XVDD XGND SD_RX SD_RX 15 15 AC VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_ LP SD_RX 18 XGND XGND XVDD RSRV _AD33 RSRV _AD34 SGND SVDD AD VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND GND LP_TMP SD_RX _DETECT 18 XVDD SD_TX 16 SD_TX 16 SVDD SGND AVDD_ AGND_ SRDS3 SRDS3 AE GND VDD_PL GND VDD_PL GND VDD_PL GND SGND SD_IMP_ XVDD CAL_TX XGND SD_RX 16 SD_RX 16 SVDD SGND AF PD 17 PD 13 CVDD SD_TX 19 SD_TX X1VDD 19 S1VDD RSRV _AG29 SD_TX 17 SD_TX 17 SGND SVDD SD_RX SD_RX 17 17 AG UART2_ USB1_ AGND CTS USB1_ VDD_ 1P0 USB2_ VDD_ 1P0 USB2_ TMS AGND SPI_ MISO EC2_ SD_PLL4 XGND RX_ER _TPD XVDD SGND GND SGND SVDD AH USB1_ VDD_ 3P3 USB1_ VBUS_ CLMP USB2_ VDD_ 3P3 USB2_ SPI_CS VDD_ 1 3P3 SENSE- SENSEVDD_PL GND_PL 1 1 GND VDD_PL GND VDD_PL GND VDD_PL D1_ MODT 1 RSRV _AG11 RSRV _AG12 IRQ 08 IIC4_ SCL NC_ AG15 GND IRQ 06 RSRV _AH11 RSRV _AH12 GND IRQ 10 IIC1_ SCL IRQ 01 IRQ 04 DMA2_ GPIO OVDD DACK 07 0 IO_ MSRCID VSEL MSRCID GPIO 0 04 2 4 IRQ_ OUT GND EVT 3 EVT 1 D1_ MDQ 49 D1_ MDQ 48 GVDD D1_ MDM 6 IRQ 11 GND IIC2_ SDA IIC4_ SDA OVDD SCAN_ MODE D1_ MDQS 6 D1_ MDQS 6 VID_ VDD_CA _CB3 GVDD IRQ 07 IIC3_ SDA IIC2_ SCL EVT 4 GND VID_ VDD_CA _CB2 IIC1_ SDA GND EVT 2 GND VID_ VDD_CA _CB1 D1_ MDQ 62 D1_ MDQ 59 GVDD GND GND D1_ MDQ 50 D1_ MDQ 51 D2_ MDQ 58 D1_ MDQ 60 GVDD TEST_ SEL2 D1_ MDQ 63 J SD_TX 07 D1_ MODT 3 GVDD F SD_TX 07 D1_ MCS 3 D1_ MDQ 41 E XVDD GVDD VDD_PL D1_ MDM 5 B XGND D1_ MCS 1 GND SEE DETAIL B SVDD A XGND IIC3_ SCL 4 LCS 6 SENSEGND_PL 2 IRQ 02 3 GND LAD 00 IRQ 09 2 LA 19 GND GVDD 1 LA 22 BVDD GND D2_ MDQ 61 BVDD LDP 1 D1_ MDQ 52 D2_ MDQ 55 SVDD BVDD D1_ MDQ 53 D2_ MDQ 51 SGND LA 24 EVT 0 D2_ MDQ 50 SD_TX 04 LA 27 IRQ 00 GND XVDD GND IRQ 03 D2_ MDQ 60 XVDD LAD 14 SENSE- SENSEVDD_CA GND_CA OVDD D2_ MDQ 54 SD_TX 03 LWE 3 IRQ 05 GVDD XGND NC_ K14 OVDD GND SD_TX 01 NC_ K13 GND D2_ MDM 7 XGND NC_ K12 D1_ MDQ 43 D2_ MDQ 56 NC_ E27 NC_ K11 D1_ MDQ 42 GVDD LGPL 5 SGND GVDD D2_ MDQ 49 LGPL 1 SD_TX 06 SEE DETAIL C D1_ MDQ 55 BVDD SD_TX 06 D1_ MCK 3 D1_ MDQ 54 LAD 08 XVDD D1_ MDQ 47 GVDD BVDD XGND GND D1_ MDQ 46 D2_ MDQ 43 D LA 21 XVDD D1_ MDQ 44 D2_ MDQ 42 GND SD_RX 04 XGND D1_ MCK 3 GVDD SGND XVDD D1_ MCK 2 D2_ MDQ 47 SD_TX 04 GND D1_ MCK 2 D2_ MDQ 46 XGND LAD 02 D1_ MDQ 45 GND RSRV _D32 LA 16 GVDD D2_ MDQS 5 SGND LDP 0 D1_ MDQ 35 D2_ MDQS 5 SD_RX 02 GND D1_ MDQ 34 GND SVDD LAD 10 D1_MA 13 D2_ MDQ 40 SD_RX 00 GND GND D2_ MDQ 41 NC_ D27 LA 26 D1_ MDQ 39 GVDD LAD 27 LA 30 D1_ MDQ 38 D2_ MDM 5 LGPL 2 LAD 13 D1_ MODT 2 GVDD LWE 0 LAD 15 D1_ MDM 4 D2_ MDQ 44 LAD 09 LWE 2 GVDD D2_ MDQ 45 C LCS 4 LA 30 D1_ MDQS 4 GND SD_RX 04 NC_ J14 D1_ VDD_PL MCAS GND SVDD NC_ J13 D1_ MCS 0 GND SVDD GVDD GVDD D1_ MDQS 5 SGND NC_ J11 D1_ MDQ 32 D1_ MDQS 5 RSRV _C32 D1_ MDQ 27 GND D1_ MDQ 33 GVDD SVDD SD_RX SD_RX 06 06 GVDD GVDD SD_RX 02 XGND D1_ MCS 2 D1_ MDQ 40 SGND XVDD D1_ MWE GND SD_RX 00 XGND GND D2_ MDQ 32 D2_ MDQ 39 GND NC_ C27 XVDD D1_MA D1_MA 05 06 D2_ MDIC 1 D2_ MRAS GND GVDD NC_ C26 SD_TX 02 D1_MA D1_MA 08 07 D2_ MCK 2 LGPL 4 XGND D1_ D1_ MAPAR_ MCKE 3 ERR D1_ D1_MA D1_MA GVDD MCKE 09 11 2 V LCLK 0 SD_TX 00 GND GVDD LCLK 1 TEMP_ LBCTL ANODE SVDD NC_ H27 D1_ MBA 2 D1_MA D1_MA 01 02 SGND LGPL 3 D1_MA 14 GND AGND_ SRDS1 LAD 03 D1_ VDD_PL MECC 2 D2_MA 02 SVDD LAD 05 D1_ MECC 7 GND SD_RX 03 LA 18 GVDD GVDD SGND LA 20 D1_ MECC 6 D2_MA 01 SD_RX 01 LA 23 GVDD T SD_IMP_ SVDD CAL_RX BVDD D1_ MECC 0 U NC_ B26 LA 29 D1_ MDM 8 GND LGPL 0 GND BVDD D2_ MECC 3 D1_ MDIC 0 BVDD TEMP_ CATHODE GND 36 SGND LDP 02 GVDD D2_ MCKE 1 LCS 5 MVREF 35 SD_ REF_ CLK1 SD_ REF_ CLK1 LDP 3 D2_ MECC 02 GVDD 34 SVDD NC_ H15 SEE DETAIL A D2_MA D2_MA D2_MA 03 04 05 33 AVDD_ SRDS1 GVDD D2_ MCKE 3 GVDD 32 SGND NC_ H13 GND D2_ MCKE 0 31 SD_RX 03 NC_ H12 D2_MA 15 D2_MA 07 30 SVDD GND D1_MA 15 GND 29 SD_RX 01 D1_ MDQ 26 GND D2_MA D2_MA 06 08 28 SGND D1_ MDQ 31 D2_ MECC 7 P 27 NC_ A27 GND D2_ MECC 6 R D1_ MDQS 1 D1_ MDQS 1 26 GND D1_ MDQ 11 GVDD GND GVDD 25 RSRV _A25 D1_ MDM 3 D1_ MDQS 8 D2_ MCKE 2 D1_ MDQ 14 24 LWE 1 GVDD D1_ MDQS 8 D2_MA 11 D1_ MDQ 13 D1_ MDQ 10 GND 23 LALE D1_ MDQS 3 GVDD GVDD D1_ MDQ 08 22 GND D1_ MDQ 15 D2_ MECC 1 GND D1_ MDM 1 21 RSRV _A21 GVDD GVDD D2_MA 09 GND GND 20 AVDD_ CC1 D1_ MDQ 25 D1_ MECC 1 D1_MA 12 D1_ MDQ 17 GND 19 AVDD_ DDR D1_ MDQ 28 D2_ MECC 4 GVDD D1_ MDM 2 D1_ MDQ 19 D1_ MDQ 22 D1_ MDQ 24 D2_ D2_MA D2_MA MAPAR_ 12 14 ERR GVDD GVDD GVDD N D1_ MDQ 20 D1_ MDQS 2 D2_ MDQ 25 GND D1_ MDQ 21 D1_ MDQS 2 D2_ MDQ 24 GND GND GND 18 GND D2_ MDQS 7 D2_ MDQ 62 GVDD D1_ MDQ 61 D1_ MDQ 57 GND D2_ MDQ 57 D2_ MDQS 7 D2_ MDQ 63 D2_ MDQ 59 D1_ MDQ 56 D1_ MDM 7 D1_ MDQS 7 D1_ MDQS 7 D1_ MDQ 58 5 6 7 8 9 10 11 12 13 TDO MDVAL TDI GND OVDD MSRCID DMA2_ DREQ 1 0 IO_ CLK_ GND VSEL OUT 2 HRESET 15 16 17 UART2_ SOUT GPIO 06 GPIO 01 OVDD UART1_ SHDC_ SOUT CLK USB1_ VDD_ 3P3 IO_ CKSTP_ VSEL OUT 3 GPIO 02 GND UART1_ SDHC_ DAT RTS 2 USB_ CLKIN USB1_ AGND USB1_ IBIAS_ REXT USB2_ IBIAS_ REXT TMP_ DETECT GPIO 03 DMA1_ DDONE 0 OVDD UART2_ SIN RTC USB2_ AGND USB2_ AGND USB2_ AGND GND DMA2_ DDONE 0 DMA1_ DREQ 0 GND PD 14 USB2_ AGND USB2_ UDM USB2_ UDP UART1_ SIN OVDD USB1_ AGND USB1_ USB1_ AGND AGND SYSCLK PD 15 USB1_ AGND USB1_ UDM 23 24 25 26 OVDD GND TRST TMS 18 19 20 UART1_ CTS ASLEEP TCK TEST_ SEL GND 21 22 UART2_ USB1_ UID RTS CVDD EMI2_ EC_XTRNL MDIO _TX_STMP 2 GND RSRV _U35 SVDD SVDD TSEC_ TSEC_ LV EMI1_ 1588_PULSE DD 1588_ALARM MDC _OUT1 _OUT2 TSEC_ EC1_ TSEC_ EMI2_ EC_XTRNL EC_XTRNL LVDD GTX_ 1588_ALARM1588_TRIG MDC _RX_STMP _RX_STMP _IN2 CLK125 _OUT2 2 1 TSEC_ EC2_ TSEC_ TSEC_ LV EMI1_ GND GND 1588_PULSE DD GTX_ 1588_CLK 1588_TRIG MDIO _OUT01 CLK125 _IN1 _IN EC1_ LVDD EC1_ EC1_ USB2_ SPI_CS TSEC_ EC_XTRNL GND RXD _TX_STMP RX_CLK RX_DV AGND 3 1588_CLK_ 03 1 OUT EC1_ EC1_ EC1_ LVDD USB2_ SPI_CS GND PD PD RXD RXD RXD AGND 06 12 0 2 1 0 GPIO 00 DMA1_ DACK 0 XGND SEE DETAIL D USB1_ AGND OVDD IO_ VSEL 0 OVDD RESET_ VID_ AVDD_ AVDD_ AVDD_ POVDD VDD_CA FM CC2 PLAT REQ _CB0 14 GPIO 05 USB2_ USB2_ GND VBUS_ UID CLMP USB2_ USB1_ USB1_ USB1_ VDD_1P8 VDD_1P8 AGND AGND _DECAP _DECAP IO_ OVDD PORESET VSEL 1 GND GND SD1_IMP SD_RX SD_RX 19 CAL_RX 19 RSRV _U32 SGND SPI_ CLK P W Y AA AJ AK AL AM AN AP LVDD EC1_ TX_EN AR PD 11 EC1_ TXD 2 EC1_ TXD 0 33 34 35 PD 07 PD 05 USB2_ SPI_CS AGND 2 PD 03 PD 09 GND PD 10 SPI_ MOSI PD 04 PD 01 PD 08 29 30 31 32 28 N EC1_ TXD 1 LVDD 27 M EC1_ TXD 3 PD 02 USB1_ USB2_ AGND UDP L EC1_ GTX_ CLK CVDD USB2_ AGND K GND GND AT 36 Signal Groups OVDD I/O Supply Voltage SVDD SerDes Core Power Supply AVDD_ SRDS1 SerDes 1 PLL Supply Voltage SENSEVDD Core Group A Voltage Sense LVDD I/O Supply Voltage XVDD SerDes Transcvr Pad Supply AVDD_ SRDS2 SerDes 2 PLL Supply Voltage SENSEVDD_CB Core Group B Voltage Sense GVDD DDR DRAM I/O Supply VDD_ PL Platform Supply Voltage AVDD_ PLAT Platform PLL Supply Voltage RSRV CVDD SPI Voltage Supply VDD_ CA Core Group A Supply Voltage AVDD_ CC Core PLL Supply Voltage BVDD Local Bus I/O Supply SENSEVDD_PL Platform Voltage Sense POVDD Reserved Fuse Programming Override Supply Figure 2. 1295 BGA ball map diagram (top view) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 4 Freescale Semiconductor Pin assignments and reset states 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 D2_ MDQ 21 D2_ MDQ 20 D2_ MDQ 10 D2_ MDQS 1 D2_ MDQS 1 D2_ MDQ 08 D2_ MDQ 03 D2_ MDQ 07 D2_ MDQS 0 D2_ MDQS 0 D2_ MDQ 01 D2_ MDQ 04 D1_ MDQ 03 D1_ MDQ 06 D1_ MDM 0 D1_ MDQ 00 D2_ MDQ 16 GVDD D2_ MDQ 17 D2_ MDQ 11 D2_ MDM 1 D2_ MDQ 13 GVDD D2_ MDQ 02 D2_ MDQ 06 D2_ MDM 0 D2_ MDQ 05 GVDD D1_ MDQ 07 D1_ MDQS 0 D1_ MDQ 05 D2_ MDQS 2 D2_ MDQ 22 D2_ MDQS 2 D2_ MDQ 12 D1_ MDQ 16 D2_ MDQ 00 D1_ MDQ 02 D1_ MDQS 0 D1_ MDQ 04 GVDD D2_ MDQ 23 GVDD D1_ MDQ 01 NC_ D18 E D2_ MDQ 19 NC_ E16 GND LAD 28 F D1_ MDQ 12 LAD 31 LAD 29 D1_ MDQ 09 GVDD GND LA 31 A B GND D2_ MDM 2 D2_ MDQ 14 GVDD D2_ MDQ 18 GVDD D2_ MDQ 15 D2_ MDQ 09 GVDD D2_ MDQ 29 D2_ MDQ 28 RSRV _F1 RSRV _F2 GND G RSRV _G1 RSRV _G2 H D2_ MDQ 31 GVDD J D2_ MECC 0 D2_ MECC 5 D2_ MDQS 8 D2_ MDQS 8 D2_ MDM 8 C D K L M D2_ MBA 2 GND GND D2_ MDQS 3 D2_ MDQS 3 D2_ MDQ 30 D2_ MDQ 26 GND D1_ MDQ 17 D1_ MDQ 19 D1_ MDQ 29 GVDD D1_ MDM 2 D1_ MDQ 18 D1_ MDQ 24 D2_ MDM 3 GVDD GVDD GVDD GVDD D1_ MDQ 20 D1_ MDQS 2 D1_ MDQ 23 D2_ MDQ 25 D1_ MDQ 21 D1_ MDQS 2 D1_ MDQ 22 D2_ MDQ 24 GND GND GND GND GVDD NC_ H15 LDP 3 LDP 2 BVDD D1_ MDQ 27 NC_ J11 GVDD NC_ J13 NC_ J14 LAD 30 LWE 2 LAD 15 LAD 13 NC_ K11 NC_ K12 NC_ K13 NC_ K14 LWE 3 GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL D2_ MECC 1 GVDD D1_ MDQS 8 D1_ MDQS 8 GVDD D2_ MECC 6 D2_ MECC 7 GND D1_MA 15 D2_MA 15 GND D2_ MCKE 3 D2_ MECC 2 GVDD D2_ MECC 3 D1_ D1_ MAPAR_ MCKE 3 ERR D1_ GV D1_MA D1_MA DD MCKE 09 11 2 GVDD VDD_PL D1_ VDD_PL MCKE 1 N D2_ D2_MA D2_MA MAPAR_ 12 14 ERR GVDD P D2_MA 09 GVDD D2_ MCKE 2 R D2_MA D2_MA 06 08 T U V D2_MA 11 GND D1_MA 12 D2_MA 07 D2_ MCKE 0 GVDD D2_MA D2_MA D2_MA 03 04 05 GVDD D2_ MCKE 1 D1_ MDIC 0 D2_MA 01 GVDD GND D2_MA 02 GND D2_ MCK 2 D2_ MCK 2 D2_ MCK 1 D2_ MCK 1 D1_ MCK 1 GND D1_ MDM 8 D1_ MECC 0 GVDD D1_ MECC 6 GVDD D1_ MECC 7 D1_ VDD_PL MECC 2 D1_MA 14 D1_ MBA 2 GND D1_MA D1_MA 07 08 GND D1_MA D1_MA 01 02 D1_ MCK 1 GND GVDD GND D1_MA D1_MA 06 05 GVDD D1_ MCK 2 D1_ MECC 3 D1_ MCKE 0 GVDD GND GND GND D1_MA D1_MA VDD_PL 03 04 D1_ MCK 2 D1_ MDQS 1 D1_ MDQS 1 NC_ H13 GVDD GND D1_ MDQ 15 NC_ H12 D1_ MECC 1 GND GVDD GND D1_ MDQ 26 D1_ MECC 4 D1_ MDQ 14 D1_ MDQ 11 D1_ MDQ 31 D1_ MECC 5 D1_ MDQ 13 D1_ MDQ 10 D1_ MDM 3 D2_ MECC 4 GND D1_ MDQ 08 GVDD GVDD GVDD D1_ MDM 1 GND D1_ MDQ 25 D1_ MDQS 3 D1_ MDQ 30 GND GND GND GND D1_ MDQ 28 D1_ MDQS 3 D2_ MDQ 27 GND 18 GND GND GND GND SENSE- SENSEVDD_CA GND_CA LAD 14 DETAIL A Figure 3. 1295 BGA ball map diagram (detail view A) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 5 Pin assignments and reset states 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 SD_ REF_ CLK1 SD_ REF_ CLK1 36 SGND SD_RX 01 SVDD SD_RX 03 SGND AVDD_ SRDS1 SVDD SD_IMP_ SVDD CAL_RX SD_RX 01 SGND SD_RX 03 SVDD AGND_ SRDS1 SGND SD_RX 00 SGND SD_RX 02 SVDD RSRV _C32 SGND SVDD SVDD SD_RX 04 C NC_ D27 SD_RX 00 SVDD SD_RX 02 SGND RSRV _D32 XGND SD_TX 04 SGND SD_RX 04 D LGPL 5 NC_ E27 XGND SD_TX 01 XGND SD_TX 03 XVDD XVDD SD_TX 04 SGND SVDD LAD 04 BVDD GND XVDD SD_TX 01 XVDD SD_TX 03 XGND SD_TX 05 SVDD SD_RX 05 SD_RX 05 LAD 06 LA 17 LCS 7 NC_ G27 SD_TX 00 XGND SD_TX 02 XGND XVDD SD_TX 05 SGND SVDD SGND LA 18 LAD 05 LAD 03 LGPL 3 NC_ H27 SD_TX 00 XGND SD_TX 02 XVDD XGND XVDD XGND SD_RX 06 SD_RX 06 LAD 10 GND LDP 00 LA 16 LAD 02 GND XVDD XGND XVDD XGND XVDD SD_TX 06 SD_TX 06 SGND SVDD LA 24 BVDD LDP 1 BVDD GND LAD 00 SENSEGND_PL 02 XGND XGND XVDD SD_TX 07 SD_TX 07 SGND SVDD SD_RX 07 SD_RX 07 GND VDD_PL GND VDD_PL GND VDD_PL LAD 01 SENSEVDD_PL 02 RSRV _L28 XGND XVDD XVDD XGND SD_RX 08 SD_RX 08 SVDD SGND GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND RSRV _M28 XVDD XGND SD_TX 08 SD_TX 08 SVDD SGND SD_RX 09 SD_RX 09 VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL RSRV _N28 XGND XGND XVDD XGND SD_TX 09 SD_TX 09 SGND SVDD GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND XGND XVDD SD_TX 10 SD_TX 10 XVDD XGND SD_RX 10 SD_RX 10 VDD_CA GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL AVDD_ SRDS4 XVDD XGND XVDD XGND SGND SVDD SVDD SGND GND VDD_CA GND VDD_PL GND VDD_PL GND VDD_PL GND AGND_ SRDS4 XVDD SD_TX 11 SD_TX 11 XVDD SD_RX 11 SD_RX 11 SGND AGND_ SRDS2 T VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL SD_ REF_ CLK4 XGND XVDD XGND RSRV _U32 SVDD SGND RSRV _U35 AVDD_ SRDS2 U GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND SD_ REF_ CLK4 XGND XVDD XGND XVDD SD_ REF_ CLK2 SD_ REF_ CLK2 SVDD SGND AVDD_ CC1 RSRV _A21 GND GND TEMP_ CATHODE GND NC_ C19 NC_ C20 TEMP_ ANODE LCS 0 LCS 1 GND NC_ A27 LWE 1 RSRV _A25 GND LCS 5 BVDD LGPL 0 NC_ B26 LBCTL LCLK 1 LCLK 0 LGPL 4 NC_ C26 NC_ C27 LCS 3 LCS 4 LAD 09 LWE 0 LGPL 2 LAD 27 LCS 2 LA 21 BVDD LAD 08 BVDD LGPL 1 LAD 12 BVDD LA 22 LA 19 GND LCS 06 LA 28 LA 25 GND LAD 11 LAD 07 LA 29 BVDD LA 23 LA 20 LA 30 LA 26 GND GND LA 27 VDD_PL AVDD_ DDR MVREF LALE RSRV _P28 SGND SVDD A B E F G H J K L M N P R V DETAIL B Figure 4. 1295 BGA ball map diagram (detail view B) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 6 Freescale Semiconductor Pin assignments and reset states DETAIL C W Y AA D2_ MCK 3 D2_ MCK 3 D2_ GVDD MAPAR_ OUT D2_ D2_MA MBA 10 1 D2_ MCK 0 D2_ MCK 0 D1_ MCK 0 GND D2_MA 00 GND D2_ MBA 0 D2_ MDIC 0 D1_ MDIC 1 D1_ GVDD MAPAR_ OUT D1_ GVDD D1_MA MBA 10 0 D1_ MDQ 37 AB D2_ MRAS D2_ MWE D2_ MCS 2 GVDD D1_ MDQ 36 AC D2_ MCS 0 GVDD D2_ MCAS D2_MA 13 GND AD D2_ MODT 2 D2_ MODT 0 D1_ MDQS 4 AE D2_ MCS 1 D2_ MCS 3 D2_ MODT 3 GVDD AF D2_ MODT 1 GVDD D2_ MDQ 37 D2_ MDQ 36 AG D2_ MDM 4 D2_ MDQ 33 AH D2_ MDQ 38 D2_ MDQS 4 AJ D2_ MDQ 35 GVDD AK RSRV _AK1 RSRV _AK2 AL RSRV _AL1 RSRV _AL2 AM D2_ MDQ 52 GVDD AN D2_ MDQ 48 D2_ MDQ 53 AP D2_ MDQS 6 D2_ MDM 6 AR D2_ MDQS 6 AT GND GND D2_ MDQS 4 D2_ MDQ 34 D1_ MCK 0 D1_MA 00 GVDD VDD_PL D1_ MBA 1 GND GND D1_ VDD_PL MRAS D1_ MWE D1_ MCS 2 GVDD D1_ MDQ 33 D1_ MDQ 32 GVDD D1_ MCS 0 D1_ VDD_PL MCAS D1_ MDQS 4 GVDD D1_ MDM 4 D1_ MODT 2 D1_ MDQ 38 D1_ MDQ 39 GND D1_MA 13 D1_ MDQ 34 D1_ MDQ 35 GVDD D1_ MDQ 45 D1_ MDQ 44 GND D1_ MDQ 40 GVDD GVDD D1_ MDQS 5 D1_ MDQS 5 GND D2_ MDQ 40 D2_ MDQS 5 D2_ MDQS 5 GND D2_ MDQ 56 D2_ MDM 7 GVDD D2_ MDQ 54 D2_ MDQ 60 D2_ MDQ 50 D2_ MDQ 51 D2_ MDQ 55 D2_ MDQ 61 1 2 3 4 GND GND VDD_PL GND GND GND GND GND VDD_PL GND GND GND GND GND VDD_PL GND GND GND GND GND GND GND VDD_PL GND GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND D1_ MCS 1 GVDD VDD_PL D1_ MCS 3 D1_ MODT 3 SENSE- SENSEVDD_PL GND_PL 1 1 GND VDD_PL GND VDD_PL GND VDD_PL D1_ MODT 1 RSRV _AG11 RSRV _AG12 IRQ 08 IIC4_ SCL NC_ AG15 GND IRQ 06 GND RSRV _AH11 RSRV _AH12 GND IRQ 10 IIC1_ SCL IRQ 01 IRQ 04 MSRCID 2 GND OVDD IRQ 05 OVDD IRQ 03 IRQ 00 EVT 0 OVDD GND IRQ 02 IIC3_ SCL IRQ_ OUT GND EVT 3 EVT 1 IO_ VSEL 2 D1_ MDQ 49 D1_ MDQ 48 GVDD D1_ MDM 6 IRQ 11 GND IIC2_ SDA IIC4_ SDA OVDD SCAN_ MODE IO_ VSEL 0 D1_ MDQS 6 D1_ MDQS 6 GND VID_ VDD_CA _CB3 IRQ 07 IIC3_ SDA IIC2_ SCL EVT 4 GND D1_ MDQ 50 D1_ MDQ 51 GVDD VID_ VDD_CA _CB2 IIC1_ SDA GND EVT 2 TEST_ SEL2 D1_ MDQ 63 GND VID_ VDD_CA _CB1 D1_ MDQ 62 D1_ MDQ 59 GVDD D1_ MDQ 55 GVDD VDD_PL IRQ 09 D1_ MDQ 54 D2_ MDQ 49 GND GVDD GVDD GVDD GND GND D2_ MDQ 47 D2_ MDQ 43 GND D1_ MDQ 43 D2_ MDQ 46 D2_ MDQ 42 GND D1_ MDQ 42 D1_ MDQ 52 D2_ MDQ 41 GND GND GVDD D1_ MDQ 53 GVDD D1_ MODT 0 VDD_PL D1_ MDQ 41 GVDD D2_ MDM 5 GND GND GND D1_ MDM 5 D1_ MDQ 47 GVDD GND GND D1_ MDQ 46 D2_ MDQ 44 GND D1_ MCK 3 GND D2_ MDQ 45 GND D1_ MCK 3 D2_ MDIC 1 D2_ MDQ 32 D2_ MDQ 39 GND GND D2_ MDQ 58 D1_ MDQ 60 GVDD D2_ MDQS 7 D2_ MDQ 62 GVDD D1_ MDQ 61 D1_ MDQ 57 D2_ MDQ 57 D2_ MDQS 7 D2_ MDQ 63 D2_ MDQ 59 D1_ MDQ 56 D1_ MDM 7 D1_ MDQS 7 D1_ MDQS 7 D1_ MDQ 58 5 6 7 8 9 10 11 12 13 GND GND TDO MDVAL OVDD GND TDI IO_ VSEL 3 OVDD IO_ PORESET VSEL 1 HRESET GND OVDD RESET_ VID_ AVDD_ POVDD VDD_CA CC3 REQ _CB0 14 15 16 17 18 Figure 5. 1295 BGA ball map diagram (detail view C) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 7 Pin assignments and reset states DETAIL D GND GND VDD_PL GND VDD_PL GND VDD_PL GND NC_ W27 VDD_PL XVDD XGND SD_TX 12 SD_TX 12 SGND SVDD SD_RX 12 SD_RX 12 W GND GND GND VDD_PL GND VDD_PL GND VDD_PL GND XGND SD_TX 13 SD_TX 13 XVDD XGND SD_RX 13 SD_RX 13 SGND SVDD Y GND GND GND GND VDD_PL GND VDD_PL GND VDD_PL SD1_IMP XVDD _CAL_TX XGND SD_TX 14 SD_TX 14 SVDD SGND SD_RX 14 SD_RX 14 AA GND GND GND VDD_PL GND VDD_PL GND VDD_PL GND SD_TX 18 SD_TX 18 XVDD XVDD XGND SD_TX 15 SD_TX 15 SVDD SGND AB GND GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL VDD_ LL S1VDD XGND SD_ REF_ CLK3 SD_ REF_ CLK3 XVDD XGND SD_RX 15 SD_RX 15 AC GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND VDD_ LP SD_RX 18 XGND XGND XVDD RSRV _AD33 RSRV _AD34 SGND SVDD AD VDD_PL GND VDD_PL GND VDD_PL GND VDD_PL GND GND LP_ SD_RX TEMP_ 18 DETECT XVDD SD_TX 16 SD_TX 16 SVDD SGND AVDD_ AGND_ SRDS3 SRDS3 AE GND VDD_PL GND VDD_PL GND VDD_PL GND SD_RX 19 SGND SD_IMP_ XVDD CAL_TX XGND SD_RX 16 SD_RX 16 SVDD SGND AF CVDD SD_TX 19 S1VDD RSRV _AG29 SD_TX 17 SD_TX 17 SGND SVDD SD_RX 17 SD_RX 17 AG SGND GND SGND SVDD AH DMA2_ GPIO OVDD DACK 07 0 IO_ GPIO VSEL MSRCID 04 0 4 SDHC_ SDHC_ DAT CMD 3 GND UART2_ CTS USB1_ AGND DMA2_ DREQ 0 GPIO 05 UART2_ SOUT OVDD USB1_ AGND GND CLK_ OUT GPIO 06 GPIO 01 UART2_ RTS USB2_ UID DMA1_ DACK 0 OVDD GPIO 00 UART1_ SDHC_ CLK SOUT USB1_ VDD_ 3P3 CKSTP_ OUT GPIO 02 GND UART1_ SDHC_ DAT RTS 02 RSRV USB_ [29] CLKIN TMP_ DETECT GPIO 03 DMA1_ DDONE 00 GND DMA2_ DDONE 0 TRST TMS MSRCID 1 AVDD_ AVDD_ PLAT FM 19 20 OVDD DMA1_ UART1_ DREQ CTS 0 ASLEEP TCK TEST_ SEL GND 21 22 SD1_IMP SD_RX _CAL_RX 19 SD_TX 19 X1VDD XGND USB1_ VDD_ 1P0 USB1_ VDD_ 3P3 USB1_ VBUS_ CLMP USB2_ USB2_ SPI_ EC_RX_ SD_PLL4 XGND XVDD TMS VDD_ AGND MISO _TPD ER 1P0 USB2_ USB2_ SPI_CS CVDD EMI2_ EC_XTRNL GND _VDD_ VDD_ MDIO _TX_STMP 1 3P3 3P3 2 USB2_ EC_XTRNL EC_XTRNL EMI2_ SPI_ USB2_ GND VBUS_ UID MDC _RX_STMP _RX_STMP CLK CLMP 2 1 USB1_ TSEC_ USB2_ LVDD USB2_ GND EMI1_ USB1 VDD_1P8_ 1588_PULSE _DD_1P8_ AGND _AGND MDIO DECAP _OUT1 DECAP USB1_ USB2_ USB1_ IBIAS_ USB2_ SPI_CS TSEC_ EC_XTRNL GND IBIAS_ 1588_CLK_ _TX_STMP AGND AGND 3 REXT REXT 1 OUT EC2_ EC2_ USB2_ USB2_ USB2_ USB2_ SPI_CS GND RXD GTX_ AGND AGND AGND AGND 0 2 CLK TSEC_ TSEC_ LVDD EMI1_ 1588_ALARM 1588_PULSE MDC _OUT1 _OUT2 AJ TSEC_ EC1_ TSEC_ GTX_ 1588_ALARM 1588_TRIG CLK125 _OUT2 _IN2 AK TSEC_ TSEC_ 1588_CLK 1588_TRIG _IN1 _IN AL LVDD EC2_ GTX_ CLK125 GND EC1_ RXD 3 EC1_ RX_DV LVDD EC1_ RX_CLK AM LVDD EC1_ RXD 2 EC1_ RXD 1 EC1_ RXD 0 AN EC1_ GTX_ CLK EC1_ TXD 3 AP EC1_ TX_EN AR UART2_ SIN RTC GND SDHC_ DAT 0 USB2_ USB2_ AGND UDM USB2_ UDP USB2_ AGND CVDD EC2_ TXD 2 LVDD EC2_ RXD 1 EC2_ RXD 3 UART1_ SIN OVDD USB1_ AGND USB1_ AGND USB1_ AGND USB1_ SPI_CS AGND 2 EC2_ TXD 1 EC2_ TX_EN GND EC2_ RX_DV EC1_ TXD 1 LVDD SDHC_ USB1_ DAT AGND 1 USB1_ UDM USB1_ UDP USB1_ AGND SPI_ MOSI EC2_ TXD 0 EC2_ TXD 3 EC2_ RXD 0 EC2_ RX_CLK EC1_ TXD 2 EC1_ TXD 0 26 27 28 29 30 31 32 33 34 35 SYSCLK 23 24 25 GND GND AT 36 Figure 6. 1295 BGA ball map diagram (detail view D) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 8 Freescale Semiconductor Pin assignments and reset states 1.2 Pinout list This table provides the pinout listing for the 1295 FC-PBGA package by bus. Table 1. Pins listed by bus Signal Signal description Package Pin Power pin number type supply Notes DDR SDRAM Memory interface 1 D1_MDQ00 Data A17 I/O GVDD — D1_MDQ01 Data D17 I/O GVDD — D1_MDQ02 Data C14 I/O GVDD — D1_MDQ03 Data A14 I/O GVDD — D1_MDQ04 Data C17 I/O GVDD — D1_MDQ05 Data B17 I/O GVDD — D1_MDQ06 Data A15 I/O GVDD — D1_MDQ07 Data B15 I/O GVDD — D1_MDQ08 Data D15 I/O GVDD — D1_MDQ09 Data G15 I/O GVDD — D1_MDQ10 Data E12 I/O GVDD — D1_MDQ11 Data G12 I/O GVDD — D1_MDQ12 Data F16 I/O GVDD — D1_MDQ13 Data E15 I/O GVDD — D1_MDQ14 Data E13 I/O GVDD — D1_MDQ15 Data F13 I/O GVDD — D1_MDQ16 Data C8 I/O GVDD — D1_MDQ17 Data D12 I/O GVDD — D1_MDQ18 Data E9 I/O GVDD — D1_MDQ19 Data E10 I/O GVDD — D1_MDQ20 Data C11 I/O GVDD — D1_MDQ21 Data C10 I/O GVDD — D1_MDQ22 Data E6 I/O GVDD — D1_MDQ23 Data E7 I/O GVDD — D1_MDQ24 Data F7 I/O GVDD — D1_MDQ25 Data F11 I/O GVDD — D1_MDQ26 Data H10 I/O GVDD — D1_MDQ27 Data J10 I/O GVDD — D1_MDQ28 Data F10 I/O GVDD — D1_MDQ29 Data F8 I/O GVDD — D1_MDQ30 Data H7 I/O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 9 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D1_MDQ31 Data H9 I/O GVDD — D1_MDQ32 Data AC7 I/O GVDD — D1_MDQ33 Data AC6 I/O GVDD — D1_MDQ34 Data AF6 I/O GVDD — D1_MDQ35 Data AF7 I/O GVDD — D1_MDQ36 Data AB5 I/O GVDD — D1_MDQ37 Data AB6 I/O GVDD — D1_MDQ38 Data AE5 I/O GVDD — D1_MDQ39 Data AE6 I/O GVDD — D1_MDQ40 Data AG5 I/O GVDD — D1_MDQ41 Data AH9 I/O GVDD — D1_MDQ42 Data AJ9 I/O GVDD — D1_MDQ43 Data AJ10 I/O GVDD — D1_MDQ44 Data AG8 I/O GVDD — D1_MDQ45 Data AG7 I/O GVDD — D1_MDQ46 Data AJ6 I/O GVDD — D1_MDQ47 Data AJ7 I/O GVDD — D1_MDQ48 Data AL9 I/O GVDD — D1_MDQ49 Data AL8 I/O GVDD — D1_MDQ50 Data AN10 I/O GVDD — D1_MDQ51 Data AN11 I/O GVDD — D1_MDQ52 Data AK8 I/O GVDD — D1_MDQ53 Data AK7 I/O GVDD — D1_MDQ54 Data AN7 I/O GVDD — D1_MDQ55 Data AN8 I/O GVDD — D1_MDQ56 Data AT9 I/O GVDD — D1_MDQ57 Data AR10 I/O GVDD — D1_MDQ58 Data AT13 I/O GVDD — D1_MDQ59 Data AR13 I/O GVDD — D1_MDQ60 Data AP9 I/O GVDD — D1_MDQ61 Data AR9 I/O GVDD — D1_MDQ62 Data AR12 I/O GVDD — D1_MDQ63 Data AP12 I/O GVDD — D1_MECC0 Error Correcting Code K9 I/O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 10 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D1_MECC1 Error Correcting Code J5 I/O GVDD — D1_MECC2 Error Correcting Code L10 I/O GVDD — D1_MECC3 Error Correcting Code M10 I/O GVDD — D1_MECC4 Error Correcting Code J8 I/O GVDD — D1_MECC5 Error Correcting Code J7 I/O GVDD — D1_MECC6 Error Correcting Code L7 I/O GVDD — D1_MECC7 Error Correcting Code L9 I/O GVDD — D1_MAPAR_ERR Address Parity Error N8 I GVDD 40 D1_MAPAR_OUT Address Parity Out Y7 O GVDD — D1_MDM0 Data Mask A16 O GVDD — D1_MDM1 Data Mask D14 O GVDD — D1_MDM2 Data Mask D11 O GVDD — D1_MDM3 Data Mask G11 O GVDD — D1_MDM4 Data Mask AD7 O GVDD — D1_MDM5 Data Mask AH8 O GVDD — D1_MDM6 Data Mask AL11 O GVDD — D1_MDM7 Data Mask AT10 O GVDD — D1_MDM8 Data Mask K8 O GVDD — D1_MDQS0 Data Strobe C16 I/O GVDD — D1_MDQS1 Data Strobe G14 I/O GVDD — D1_MDQS2 Data Strobe D9 I/O GVDD — D1_MDQS3 Data Strobe G9 I/O GVDD — D1_MDQS4 Data Strobe AD5 I/O GVDD — D1_MDQS5 Data Strobe AH6 I/O GVDD — D1_MDQS6 Data Strobe AM10 I/O GVDD — D1_MDQS7 Data Strobe AT12 I/O GVDD — D1_MDQS8 Data Strobe K6 I/O GVDD — D1_MDQS0 Data Strobe B16 I/O GVDD — D1_MDQS1 Data Strobe F14 I/O GVDD — D1_MDQS2 Data Strobe D8 I/O GVDD — D1_MDQS3 Data Strobe G8 I/O GVDD — D1_MDQS4 Data Strobe AD4 I/O GVDD — D1_MDQS5 Data Strobe AH5 I/O GVDD — D1_MDQS6 Data Strobe AM9 I/O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 11 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D1_MDQS7 Data Strobe AT11 I/O GVDD — D1_MDQS8 Data Strobe K5 I/O GVDD — D1_MBA0 Bank Select AA8 O GVDD — D1_MBA1 Bank Select Y10 O GVDD — D1_MBA2 Bank Select M8 O GVDD — D1_MA00 Address Y9 O GVDD — D1_MA01 Address U6 O GVDD — D1_MA02 Address U7 O GVDD — D1_MA03 Address U9 O GVDD — D1_MA04 Address U10 O GVDD — D1_MA05 Address T8 O GVDD — D1_MA06 Address T9 O GVDD — D1_MA07 Address R8 O GVDD — D1_MA08 Address R7 O GVDD — D1_MA09 Address P6 O GVDD — D1_MA10 Address AA7 O GVDD — D1_MA11 Address P7 O GVDD — D1_MA12 Address N6 O GVDD — D1_MA13 Address AE8 O GVDD — D1_MA14 Address M7 O GVDD — D1_MA15 Address L6 O GVDD — D1_MWE Write Enable AB8 O GVDD — D1_MRAS Row Address Strobe AA10 O GVDD — D1_MCAS Column Address Strobe AC10 O GVDD — D1_MCS0 Chip Select AC9 O GVDD — D1_MCS1 Chip Select AE9 O GVDD — D1_MCS2 Chip Select AB9 O GVDD — D1_MCS3 Chip Select AF9 O GVDD — D1_MCKE0 Clock Enable P10 O GVDD — D1_MCKE1 Clock Enable R10 O GVDD — D1_MCKE2 Clock Enable P9 O GVDD — D1_MCKE3 Clock Enable N9 O GVDD — D1_MCK0 Clock W6 O GVDD — D1_MCK1 Clock V6 O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 12 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D1_MCK2 Clock V8 O GVDD — D1_MCK3 Clock W9 O GVDD — D1_MCK0 Clock Complements W5 O GVDD — D1_MCK1 Clock Complements V5 O GVDD — D1_MCK2 Clock Complements V9 O GVDD — D1_MCK3 Clock Complements W8 O GVDD — D1_MODT0 On Die Termination AD10 O GVDD — D1_MODT1 On Die Termination AG10 O GVDD — D1_MODT2 On Die Termination AD8 O GVDD — D1_MODT3 On Die Termination AF10 O GVDD — D1_MDIC0 Driver Impedance Calibration T6 I/O GVDD 16 D1_MDIC1 Driver Impedance Calibration AA5 I/O GVDD 16 DDR SDRAM Memory interface 2 D2_MDQ00 Data C13 I/O GVDD — D2_MDQ01 Data A12 I/O GVDD — D2_MDQ02 Data B9 I/O GVDD — D2_MDQ03 Data A8 I/O GVDD — D2_MDQ04 Data A13 I/O GVDD — D2_MDQ05 Data B13 I/O GVDD — D2_MDQ06 Data B10 I/O GVDD — D2_MDQ07 Data A9 I/O GVDD — D2_MDQ08 Data A7 I/O GVDD — D2_MDQ09 Data D6 I/O GVDD — D2_MDQ10 Data A4 I/O GVDD — D2_MDQ11 Data B4 I/O GVDD — D2_MDQ12 Data C7 I/O GVDD — D2_MDQ13 Data B7 I/O GVDD — D2_MDQ14 Data C5 I/O GVDD — D2_MDQ15 Data D5 I/O GVDD — D2_MDQ16 Data B1 I/O GVDD — D2_MDQ17 Data B3 I/O GVDD — D2_MDQ18 Data D3 I/O GVDD — D2_MDQ19 Data E1 I/O GVDD — D2_MDQ20 Data A3 I/O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 13 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D2_MDQ21 Data A2 I/O GVDD — D2_MDQ22 Data D1 I/O GVDD — D2_MDQ23 Data D2 I/O GVDD — D2_MDQ24 Data F4 I/O GVDD — D2_MDQ25 Data F5 I/O GVDD — D2_MDQ26 Data H4 I/O GVDD — D2_MDQ27 Data H6 I/O GVDD — D2_MDQ28 Data E4 I/O GVDD — D2_MDQ29 Data E3 I/O GVDD — D2_MDQ30 Data H3 I/O GVDD — D2_MDQ31 Data H1 I/O GVDD — D2_MDQ32 Data AG4 I/O GVDD — D2_MDQ33 Data AG2 I/O GVDD — D2_MDQ34 Data AJ3 I/O GVDD — D2_MDQ35 Data AJ1 I/O GVDD — D2_MDQ36 Data AF4 I/O GVDD — D2_MDQ37 Data AF3 I/O GVDD — D2_MDQ38 Data AH1 I/O GVDD — D2_MDQ39 Data AJ4 I/O GVDD — D2_MDQ40 Data AL6 I/O GVDD — D2_MDQ41 Data AL5 I/O GVDD — D2_MDQ42 Data AN4 I/O GVDD — D2_MDQ43 Data AN5 I/O GVDD — D2_MDQ44 Data AK5 I/O GVDD — D2_MDQ45 Data AK4 I/O GVDD — D2_MDQ46 Data AM6 I/O GVDD — D2_MDQ47 Data AM7 I/O GVDD — D2_MDQ48 Data AN1 I/O GVDD — D2_MDQ49 Data AP3 I/O GVDD — D2_MDQ50 Data AT1 I/O GVDD — D2_MDQ51 Data AT2 I/O GVDD — D2_MDQ52 Data AM1 I/O GVDD — D2_MDQ53 Data AN2 I/O GVDD — D2_MDQ54 Data AR3 I/O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 14 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D2_MDQ55 Data AT3 I/O GVDD — D2_MDQ56 Data AP5 I/O GVDD — D2_MDQ57 Data AT5 I/O GVDD — D2_MDQ58 Data AP8 I/O GVDD — D2_MDQ59 Data AT8 I/O GVDD — D2_MDQ60 Data AR4 I/O GVDD — D2_MDQ61 Data AT4 I/O GVDD — D2_MDQ62 Data AR7 I/O GVDD — D2_MDQ63 Data AT7 I/O GVDD — D2_MECC0 Error Correcting Code J1 I/O GVDD — D2_MECC1 Error Correcting Code K3 I/O GVDD — D2_MECC2 Error Correcting Code M5 I/O GVDD — D2_MECC3 Error Correcting Code N5 I/O GVDD — D2_MECC4 Error Correcting Code J4 I/O GVDD — D2_MECC5 Error Correcting Code J2 I/O GVDD — D2_MECC6 Error Correcting Code L3 I/O GVDD — D2_MECC7 Error Correcting Code L4 I/O GVDD — D2_MAPAR_ERR Address Parity Error N2 I GVDD — D2_MAPAR_OUT Address Parity Out Y1 O GVDD — D2_MDM0 Data Mask B12 O GVDD — D2_MDM1 Data Mask B6 O GVDD — D2_MDM2 Data Mask C4 O GVDD — D2_MDM3 Data Mask G3 O GVDD — D2_MDM4 Data Mask AG1 O GVDD — D2_MDM5 Data Mask AL3 O GVDD — D2_MDM6 Data Mask AP2 O GVDD — D2_MDM7 Data Mask AP6 O GVDD — D2_MDM8 Data Mask K2 O GVDD — D2_MDQS0 Data Strobe A10 I/O GVDD — D2_MDQS1 Data Strobe A5 I/O GVDD — D2_MDQS2 Data Strobe C2 I/O GVDD — D2_MDQS3 Data Strobe G6 I/O GVDD — D2_MDQS4 Data Strobe AH2 I/O GVDD — D2_MDQS5 Data Strobe AM4 I/O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 15 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D2_MDQS6 Data Strobe AR1 I/O GVDD — D2_MDQS7 Data Strobe AR6 I/O GVDD — D2_MDQS8 Data Strobe L1 I/O GVDD — D2_MDQS0 Data Strobe A11 I/O GVDD — D2_MDQS1 Data Strobe A6 I/O GVDD — D2_MDQS2 Data Strobe C1 I/O GVDD — D2_MDQS3 Data Strobe G5 I/O GVDD — D2_MDQS4 Data Strobe AH3 I/O GVDD — D2_MDQS5 Data Strobe AM3 I/O GVDD — D2_MDQS6 Data Strobe AP1 I/O GVDD — D2_MDQS7 Data Strobe AT6 I/O GVDD — D2_MDQS8 Data Strobe K1 I/O GVDD — D2_MBA0 Bank Select AA3 O GVDD — D2_MBA1 Bank Select AA1 O GVDD — D2_MBA2 Bank Select M1 O GVDD — D2_MA00 Address Y4 O GVDD — D2_MA01 Address U1 O GVDD — D2_MA02 Address U4 O GVDD — D2_MA03 Address T1 O GVDD — D2_MA04 Address T2 O GVDD — D2_MA05 Address T3 O GVDD — D2_MA06 Address R1 O GVDD — D2_MA07 Address R4 O GVDD — D2_MA08 Address R2 O GVDD — D2_MA09 Address P1 O GVDD — D2_MA10 Address AA2 O GVDD — D2_MA11 Address P3 O GVDD — D2_MA12 Address N1 O GVDD — D2_MA13 Address AC4 O GVDD — D2_MA14 Address N3 O GVDD — D2_MA15 Address M2 O GVDD — D2_MWE Write Enable AB2 O GVDD — D2_MRAS Row Address Strobe AB1 O GVDD — D2_MCAS Column Address Strobe AC3 O GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 16 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes D2_MCS0 Chip Select AC1 O GVDD — D2_MCS1 Chip Select AE1 O GVDD — D2_MCS2 Chip Select AB3 O GVDD — D2_MCS3 Chip Select AE2 O GVDD — D2_MCKE0 Clock Enable R5 O GVDD — D2_MCKE1 Clock Enable T5 O GVDD — D2_MCKE2 Clock Enable P4 O GVDD — D2_MCKE3 Clock Enable M4 O GVDD — D2_MCK0 Clock W3 O GVDD — D2_MCK1 Clock V3 O GVDD — D2_MCK2 Clock V1 O GVDD — D2_MCK3 Clock W2 O GVDD — D2_MCK0 Clock Complements W4 O GVDD — D2_MCK1 Clock Complements V4 O GVDD — D2_MCK2 Clock Complements V2 O GVDD — D2_MCK3 Clock Complements W1 O GVDD — D2_MODT0 On Die Termination AD2 O GVDD — D2_MODT1 On Die Termination AF1 O GVDD — D2_MODT2 On Die Termination AD1 O GVDD — D2_MODT3 On Die Termination AE3 O GVDD — D2_MDIC0 Driver Impedance Calibration AA4 I/O GVDD 16 D2_MDIC1 Driver Impedance Calibration Y6 I/O GVDD 16 Local bus controller interface LAD00 Muxed Data/Address K26 I/O BVDD 3 LAD01 Muxed Data/Address L26 I/O BVDD 3 LAD02 Muxed Data/Address J26 I/O BVDD 3 LAD03 Muxed Data/Address H25 I/O BVDD 3 LAD04 Muxed Data/Address F25 I/O BVDD 3 LAD05 Muxed Data/Address H24 I/O BVDD 3 LAD06 Muxed Data/Address G24 I/O BVDD 3 LAD07 Muxed Data/Address G23 I/O BVDD 3 LAD08 Muxed Data/Address E23 I/O BVDD 3 LAD09 Muxed Data/Address D23 I/O BVDD 3 LAD10 Muxed Data/Address J22 I/O BVDD 3 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 17 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes LAD11 Muxed Data/Address G22 I/O BVDD 3 LAD12 Muxed Data/Address F19 I/O BVDD 3 LAD13 Muxed Data/Address J18 I/O BVDD 3 LAD14 Muxed Data/Address K18 I/O BVDD 3 LAD15 Muxed Data/Address J17 I/O BVDD 3 LAD16 Muxed Data/Address J25 I/O BVDD 3 LAD17 Muxed Data/Address G25 I/O BVDD 3 LAD18 Muxed Data/Address H23 I/O BVDD 3,35 LAD19 Muxed Data/Address F22 I/O BVDD 3,35 LAD20 Muxed Data/Address H22 I/O BVDD 3,35 LAD21 Muxed Data/Address E21 I/O BVDD 3,35 LAD22 Muxed Data/Address F21 I/O BVDD 3,35 LAD23 Muxed Data/Address H21 I/O BVDD 3 LAD24 Muxed Data/Address K21 I/O BVDD 3 LAD25 Muxed Data/Address G20 I/O BVDD 3,35 LAD26 Muxed Data/Address J20 I/O BVDD 32 LAD27 Muxed Data/Address D26 I/O BVDD — LAD28 Muxed Data/Address E18 I/O BVDD — LAD29 Muxed Data/Address F18 I/O BVDD — LAD30 Muxed Data/Address J15 I/O BVDD — LAD31 Muxed Data/Address F17 I/O BVDD — LDP0 Data Parity J24 I/O BVDD — LDP1 Data Parity K23 I/O BVDD — LDP2 Data Parity H17 I/O BVDD — LDP3 Data Parity H16 I/O BVDD — LA27 Address K20 O BVDD — LA28 Address G19 O BVDD 35 LA29 Address H19 O BVDD 35 LA30 Address J19 O BVDD 35 LA31 Address G18 O BVDD 35 LCS0 Chip Selects D19 O BVDD 5 LCS1 Chip Selects D20 O BVDD 5 LCS2 Chip Selects E20 O BVDD 5 LCS3 Chip Selects D21 O BVDD 5 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 18 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes LCS4 Chip Selects D22 O BVDD 5 LCS5 Chip Selects B23 O BVDD 5 LCS6 Chip Selects F24 O BVDD 5 LCS7 Chip Selects G26 O BVDD 5 LWE0 Write Enable D24 O BVDD — LWE1 Write Enable A24 O BVDD — LWE2 Write Enable J16 O BVDD — LWE3 Write Enable K15 O BVDD — LBCTL Buffer Control C22 O BVDD — LALE Address Latch Enable A23 I/O BVDD — LGPL0/LFCLE UPM General Purpose Line 0/ LFCLE—FCM B25 O BVDD 3, 4 LGPL1/LFALE UPM General Purpose Line 1/ LFALE—FCM E25 O BVDD 3, 4 LGPL2/LOE/LFRE UPM General Purpose Line 2/ LOE_B—Output Enable D25 O BVDD 3, 4 LGPL3/LFWP UPM General Purpose LIne 3/ LFWP_B—FCM H26 O BVDD 3, 4 LGPL4/LGTA/LUPWAIT/LPBSE UPM General Purpose Line 4/ LGTA_B—FCM C25 I/O BVDD 39 LGPL5 UPM General Purpose Line 5 / Amux E26 O BVDD 3, 4 LCLK0 Local Bus Clock C24 O BVDD — LCLK1 Local Bus Clock C23 O BVDD — DMA DMA1_DREQ0/GPIO18 DMA1 Channel 0 Request AP21 I OVDD 26 DMA1_DACK0/GPIO19 DMA1 Channel 0 Acknowledge AL19 O OVDD 26 DMA1_DDONE0 DMA1 Channel 0 Done AN21 O OVDD 27 DMA2_DREQ0/GPIO20/ALT_MDVAL DMA2 Channel 0 Request AJ20 I OVDD 26 DMA2_DACK0/EVT7/ALT_MDSRCID0 DMA2 Channel 0 Acknowledge AG19 O OVDD 26 DMA2_DDONE0/EVT8/ALT_MDSRCID1 DMA2 Channel 0 Done AP20 O OVDD 26 USB Port 1 USB1_UDP USB1 PHY Data Plus AT27 I/O USB_VDD_ 3P3 — USB1_UDM USB1 PHY Data Minus AT26 I/O USB_VDD_ 3P3 — USB1_VBUS_CLMP USB1 PHY VBUS Divided Signal AK25 I USB_VDD_ 3P3 38 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 19 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes USB1_UID USB1 PHY ID Detect AK24 I USB1_VDD _1P8 _DECAP — USB1_DRVVBUS/GPIO04 USB1 5V Supply Enable AH21 O OVDD 26,38 USB1_PWRFAULT/GPIO05 USB1 Power Fault AJ21 I OVDD 26,38 USB_CLKIN USB PHY Clock Input AM24 I OVDD — USB Port 2 USB2_UDP USB2 PHY Data Plus AP27 I/O USB_VDD_ 3P3 — USB2_UDM USB2 PHY Data Minus AP26 I/O USB_VDD_ 3P3 — USB2_VBUS_CLMP USB2 PHY VBUS Divided Signal AK26 I USB_VDD_ 3P3 38 USB2_UID USB2 PHY ID Detect AK27 I USB2_VDD _1P8 _DECAP — USB2_DRVVBUS/GPIO06 USB2 5V Supply Enable AK21 O OVDD 26,38 USB2_PWRFAULT/GPIO07 USB2 Power Fault AG20 O OVDD 26,38 Programmable Interrupt controller IRQ00 External Interrupts AJ16 I OVDD — IRQ01 External Interrupts AH16 I OVDD — IRQ02 External Interrupts AK12 I OVDD — IRQ03/GPIO21 External Interrupts AJ15 I OVDD 26 IRQ04/GPIO22 External Interrupts AH17 I OVDD 26 IRQ05/GPIO23 External Interrupts AJ13 I OVDD 26 IRQ06/GPIO24 External Interrupts AG17 I OVDD 26 IRQ07/GPIO25 External Interrupts AM13 I OVDD 26 IRQ08/GPIO26 External Interrupts AG13 I OVDD 26 IRQ09/GPIO27 External Interrupts AK11 I OVDD 26 IRQ10/GPIO28 External Interrupts AH14 I OVDD 26 IRQ11/GPIO29 External Interrupts AL12 I OVDD 26 IRQ_OUT/EVT9 Interrupt Output AK14 O OVDD 1, 2, 26 Trust TMP_DETECT Tamper Detect AN19 I OVDD 27 LP_TMP_DETECT Low Power Tamper Detect AE28 I VDD_LP — AG23 I/O CVDD — eSDHC SDHC_CMD Command/Response P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 20 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes SDHC_DAT0 Data AP24 I/O CVDD — SDHC_DAT1 Data AT24 I/O CVDD — SDHC_DAT2 Data AM23 I/O CVDD — SDHC_DAT3 Data AG22 I/O CVDD — SDHC_DAT4/SPI_CS0 Data AN29 I/O CVDD 26, 31 SDHC_DAT5/SPI_CS1 Data AJ28 I/O CVDD 26, 31 SDHC_DAT6/SPI_CS2 Data AR29 I/O CVDD 26, 31 SDHC_DAT7/SPI_CS3 Data AM29 I/O CVDD 26, 31 SDHC_CLK Host to Card Clock AL23 O CVDD — SDHC_CD/IIC3_SCL/GPIO16 Card Detection AK13 I OVDD 26,27,31 SDHC_WP/IIC3_SDA/GPIO17 Card Write Protection AM14 I OVDD 26,27,31 eSPI SPI_MOSI Master Out Slave In AT29 I/O CVDD — SPI_MISO Master In Slave Out AH28 I CVDD — SPI_CLK eSPI clock AK29 O CVDD — SPI_CS0/SDHC_DAT4 eSPI chip select AN29 O CVDD 26 SPI_CS1/SDHC_DAT5 eSPI chip select AJ28 O CVDD 26 SPI_CS2/SDHC_DAT6 eSPI chip select AR29 O CVDD 26 SPI_CS3/SDHC_DAT7 eSPI chip select AM29 O CVDD 26 IEEE 1588 TSEC_1588_CLK_IN Clock In AL35 I LVDD — TSEC_1588_TRIG_IN1 Trigger In 1 AL36 I LVDD — TSEC_1588_TRIG_IN2/EC1_RX_ER Trigger In 2 AK36 I LVDD — TSEC_1588_ALARM_OUT1 Alarm Out 1 AJ36 O LVDD — TSEC_1588_ALARM_OUT2/EC1_COL/GPIO30 Alarm Out 2 AK35 O LVDD 26 TSEC_1588_CLK_OUT Clock Out AM30 O LVDD — TSEC_1588_PULSE_OUT1 Pulse Out1 AL30 O LVDD — TSEC_1588_PULSE_OUT2/EC1_CRS/GPIO31 Pulse Out2 AJ34 O LVDD 26 Ethernet Management interface 1 EMI1_MDC Management Data Clock AJ33 O LVDD — EMI1_MDIO Management Data In/Out AL32 I/O LVDD — AK30 O 1.2 V 2, 18, 22 Ethernet Management interface 2 EMI2_MDC Management Data Clock P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 21 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description EMI2_MDIO Management Data In/Out Package Pin Power pin number type supply Notes AJ30 I/O 1.2 V 2, 18, 22 Ethernet Reference Clock EC1_GTX_CLK125/ EC1_TX_CLK Reference Clock (RGMII) Transmit Clock (MII) AK34 I LVDD 27 EC2_GTX_CLK125/ EC2_TX_CLK Reference Clock (RGMII) Transmit Clock (MII) AL33 I LVDD 27 Ethernet External Timestamping EC_XTRNL_TX_STMP1 External Timestamp Transmit 1 AM31 I LVDD — EC_XTRNL_RX_STMP1 External Timestamp Receive 1 AK32 I LVDD — EC_XTRNL_TX_STMP2/EC2_COL External Timestamp Transmit 2 AJ31 I LVDD — EC_XTRNL_RX_STMP2/EC2_CRS External Timestamp Receive 2 AK31 I LVDD — Three-Speed Ethernet controller 1 EC1_TXD3 Transmit Data AP36 O LVDD 35 EC1_TXD2 Transmit Data AT34 O LVDD 35 EC1_TXD1 Transmit Data AR34 O LVDD 35 EC1_TXD0 Transmit Data AT35 O LVDD 35 EC1_TX_EN Transmit Enable AR36 O LVDD 15 EC1_GTX_CLK/ EC1_TX_ER Transmit Clock Out (RGMII) Transmit Error (MII) AP35 O LVDD 26 EC1_RXD3 Receive Data AM33 I LVDD 27 EC1_RXD2 Receive Data AN34 I LVDD 27 EC1_RXD1 Receive Data AN35 I LVDD 27 EC1_RXD0 Receive Data AN36 I LVDD 27 EC1_RX_DV Receive Data Valid AM34 I LVDD 27 EC1_RX_CLK Receive Clock AM36 I LVDD 27 EC1_RX_ER/TSEC_1588_TRIG_IN2 Receive Error (MII) AK36 I LVDD — EC1_COL/GPIO30/TSEC_1588_ALARM_OUT2 Collision Detect (MII) AK35 O LVDD 26 EC1_CRS/GPIO31/TSEC_1588_PULSE_OUT2 Carrier Sense (MII) AJ34 O LVDD 26 Three-Speed Ethernet controller 2 EC2_TXD3 Transmit Data AT31 O LVDD 35 EC2_TXD2 Transmit Data AP30 O LVDD 35 EC2_TXD1 Transmit Data AR30 O LVDD 35 EC2_TXD0 Transmit Data AT30 O LVDD 35 EC2_TX_EN Transmit Enable AR31 O LVDD 15 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 22 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes EC2_GTX_CLK/ EC2_TX_ER Transmit Clock Out (RGMII) Transmit Error (MII) AN31 O LVDD 26 EC2_RXD3 Receive Data AP33 I LVDD 27 EC2_RXD2 Receive Data AN32 I LVDD 27 EC2_RXD1 Receive Data AP32 I LVDD 26, 27 EC2_RXD0 Receive Data AT32 I LVDD 26, 27 EC2_RX_DV Receive Data Valid AR33 I LVDD 27 EC2_RX_CLK Receive Clock AT33 I LVDD 27 EC2_RX_ER Receive Error (MII) AH29 I LVDD — EC2_COL/EC_XTRNL_TX_STMP2 Collision Detect (MII) AJ31 O LVDD 26 EC2_CRS/EC_XTRNL_RX_STMP2 Carrier Sense (MII) AK31 O LVDD 26 UART UART1_SOUT/GPIO8 Transmit Data AL22 O OVDD 26 UART2_SOUT/GPIO9 Transmit Data AJ22 O OVDD 26 UART1_SIN/GPIO10 Receive Data AR23 I OVDD 26 UART2_SIN/GPIO11 Receive Data AN23 I OVDD 26 UART1_RTS/UART3_SOUT/GPIO12 Ready to Send AM22 O OVDD 26 UART2_RTS/UART4_SOUT/GPIO13 Ready to Send AK23 O OVDD 26 UART1_CTS/UART3_SIN/GPIO14 Clear to Send AP22 I OVDD 26 UART2_CTS/UART4_SIN/GPIO15 Clear to Send AH23 I OVDD 26 I2C interface IIC1_SCL Serial Clock AH15 I/O OVDD 2, 14 IIC1_SDA Serial Data AN14 I/O OVDD 2, 14 IIC2_SCL Serial Clock AM15 I/O OVDD 2, 14 IIC2_SDA Serial Data AL14 I/O OVDD 2, 14 IIC3_SCL/SDHC_CD/GPIO16 Serial Clock AK13 I/O OVDD 2, 14, 27 IIC3_SDA/SDHC_WP/GPIO17 Serial Data AM14 I/O OVDD 2, 14, 27 IIC4_SCL/EVT5 Serial Clock AG14 I/O OVDD 2, 14 IIC4_SDA/EVT6 Serial Data AL15 I/O OVDD 2, 14 SerDes (x20) PCIe, Aurora, 10GE, 1GE, SATA SD_TX19 Transmit Data (positive) AG25 O XVDD — SD_TX18 Transmit Data (positive) AB28 O XVDD — SD_TX17 Transmit Data (positive) AG31 O XVDD — SD_TX16 Transmit Data (positive) AE31 O XVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 23 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes SD_TX15 Transmit Data (positive) AB33 O XVDD — SD_TX14 Transmit Data (positive) AA31 O XVDD — SD_TX13 Transmit Data (positive) Y29 O XVDD — SD_TX12 Transmit Data (positive) W31 O XVDD — SD_TX11 Transmit Data (positive) T30 O XVDD — SD_TX10 Transmit Data (positive) P31 O XVDD — SD_TX09 Transmit Data (positive) N33 O XVDD — SD_TX08 Transmit Data (positive) M31 O XVDD — SD_TX07 Transmit Data (positive) K31 O XVDD — SD_TX06 Transmit Data (positive) J33 O XVDD — SD_TX05 Transmit Data (positive) G33 O XVDD — SD_TX04 Transmit Data (positive) D34 O XVDD — SD_TX03 Transmit Data (positive) F31 O XVDD — SD_TX02 Transmit Data (positive) H30 O XVDD — SD_TX01 Transmit Data (positive) F29 O XVDD — SD_TX00 Transmit Data (positive) H28 O XVDD — SD_TX19 Transmit Data (negative) AG26 O XVDD — SD_TX18 Transmit Data (negative) AB29 O XVDD — SD_TX17 Transmit Data (negative) AG32 O XVDD — SD_TX16 Transmit Data (negative) AE32 O XVDD — SD_TX15 Transmit Data (negative) AB34 O XVDD — SD_TX14 Transmit Data (negative) AA32 O XVDD — SD_TX13 Transmit Data (negative) Y30 O XVDD — SD_TX12 Transmit Data (negative) W32 O XVDD — SD_TX11 Transmit Data (negative) T31 O XVDD — SD_TX10 Transmit Data (negative) P32 O XVDD — SD_TX09 Transmit Data (negative) N34 O XVDD — SD_TX08 Transmit Data (negative) M32 O XVDD — SD_TX07 Transmit Data (negative) K32 O XVDD — SD_TX06 Transmit Data (negative) J34 O XVDD — SD_TX05 Transmit Data (negative) F33 O XVDD — SD_TX04 Transmit Data (negative) E34 O XVDD — SD_TX03 Transmit Data (negative) E31 O XVDD — SD_TX02 Transmit Data (negative) G30 O XVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 24 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes SD_TX01 Transmit Data (negative) E29 O XVDD — SD_TX00 Transmit Data (negative) G28 O XVDD — SD_RX19 Receive Data (positive) AF27 I XVDD — SD_RX18 Receive Data (positive) AD29 I XVDD — SD_RX17 Receive Data (positive) AG36 I XVDD — SD_RX16 Receive Data (positive) AF34 I XVDD — SD_RX15 Receive Data (positive) AC36 I XVDD — SD_RX14 Receive Data (positive) AA36 I XVDD — SD_RX13 Receive Data (positive) Y34 I XVDD — SD_RX12 Receive Data (positive) W36 I XVDD — SD_RX11 Receive Data (positive) T34 I XVDD — SD_RX10 Receive Data (positive) P36 I XVDD — SD_RX09 Receive Data (positive) M36 I XVDD — SD_RX08 Receive Data (positive) L34 I XVDD — SD_RX07 Receive Data (positive) K36 I XVDD — SD_RX06 Receive Data (positive) H36 I XVDD — SD_RX05 Receive Data (positive) F36 I XVDD — SD_RX04 Receive Data (positive) D36 I XVDD — SD_RX03 Receive Data (positive) A31 I XVDD — SD_RX02 Receive Data (positive) C30 I XVDD — SD_RX01 Receive Data (positive) A29 I XVDD — SD_RX00 Receive Data (positive) C28 I XVDD — SD_RX19 Receive Data (negative) AF28 I XVDD — SD_RX18 Receive Data (negative) AE29 I XVDD — SD_RX17 Receive Data (negative) AG35 I XVDD — SD_RX16 Receive Data (negative) AF33 I XVDD — SD_RX15 Receive Data (negative) AC35 I XVDD — SD_RX14 Receive Data (negative) AA35 I XVDD — SD_RX13 Receive Data (negative) Y33 I XVDD — SD_RX12 Receive Data (negative) W35 I XVDD — SD_RX11 Receive Data (negative) T33 I XVDD — SD_RX10 Receive Data (negative) P35 I XVDD — SD_RX09 Receive Data (negative) M35 I XVDD — SD_RX08 Receive Data (negative) L33 I XVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 25 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes SD_RX07 Receive Data (negative) K35 I XVDD — SD_RX06 Receive Data (negative) H35 I XVDD — SD_RX05 Receive Data (negative) F35 I XVDD — SD_RX04 Receive Data (negative) C36 I XVDD — SD_RX03 Receive Data (negative) B31 I XVDD — SD_RX02 Receive Data (negative) D30 I XVDD — SD_RX01 Receive Data (negative) B29 I XVDD — SD_RX00 Receive Data (negative) D28 I XVDD — SD_REF_CLK1 SerDes Bank 1 PLL Reference Clock A35 I XVDD — SD_REF_CLK1 SerDes Bank 1 PLL Reference Clock Complement B35 I XVDD — SD_REF_CLK2 SerDes Bank 2 PLL Reference Clock V34 I XVDD — SD_REF_CLK2 SerDes Bank 2 PLL Reference Clock Complement V33 I XVDD — SD_REF_CLK3 SerDes Bank 3 PLL Reference Clock AC32 I XVDD — SD_REF_CLK3 SerDes Bank 3 PLL Reference Clock Complement AC31 I XVDD — SD_REF_CLK4 SerDes Bank 4 PLL Reference Clock U28 I XVDD — SD_REF_CLK4 SerDes Bank 4 PLL Reference Clock Complement V28 I XVDD — General-Purpose Input/Output GPIO00 General Purpose Input / Output AL21 I/O OVDD — GPIO01 General Purpose Input / Output AK22 I/O OVDD — GPIO02 General Purpose Input / Output AM20 I/O OVDD — GPIO03 General Purpose Input / Output AN20 I/O OVDD — GPIO04/USB1_DRVVBUS General Purpose Input / Output AH21 I/O OVDD — GPIO05/USB1_PWRFAULT General Purpose Input / Output AJ21 I/O OVDD — GPIO06/USB2_DRVVBUS General Purpose Input / Output AK21 I/O OVDD — GPIO07/USB2_PWRFAULT General Purpose Input / Output AG20 I/O OVDD — GPIO08/UART1_SOUT General Purpose Input / Output AL22 I/O OVDD — GPIO09/UART2_SOUT General Purpose Input / Output AJ22 I/O OVDD — GPIO10/UART1_SIN General Purpose Input / Output AR23 I/O OVDD — GPIO11/UART2_SIN General Purpose Input / Output AN23 I/O OVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 26 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GPIO12/UART1_RTS/UART3_SOUT General Purpose Input / Output AM22 I/O OVDD — GPIO13/UART2_RTS/UART4_SOUT General Purpose Input / Output AK23 I/O OVDD — GPIO14/UART1_CTS/UART3_SIN General Purpose Input / Output AP22 I/O OVDD — GPIO15/UART2_CTS/UART4_SIN General Purpose Input / Output AH23 I/O OVDD — GPIO16/IIC3_SCL/SDHC_CD General Purpose Input / Output AK13 I/O OVDD 27 GPIO17/IIC3_SDA/SDHC_WP General Purpose Input / Output AM14 I/O OVDD 27 GPIO18/DMA1_DREQ0 General Purpose Input / Output AP21 I/O OVDD — GPIO19/DMA1_DACK0 General Purpose Input / Output AL19 I/O OVDD — GPIO20/DMA2_DREQ0/ALT_MDVAL General Purpose Input / Output AJ20 I/O OVDD — GPIO21/IRQ3 General Purpose Input / Output AJ15 I/O OVDD — GPIO22/IRQ4 General Purpose Input / Output AH17 I/O OVDD — GPIO23/IRQ5 General Purpose Input / Output AJ13 I/O OVDD — GPIO24/IRQ6 General Purpose Input / Output AG17 I/O OVDD — GPIO25/IRQ7 General Purpose Input / Output AM13 I/O OVDD — GPIO26/IRQ8 General Purpose Input / Output AG13 I/O OVDD — GPIO27/IRQ9 General Purpose Input / Output AK11 I/O OVDD — GPIO28/IRQ10 General Purpose Input / Output AH14 I/O OVDD — GPIO29/IRQ11 General Purpose Input / Output AL12 I/O OVDD — GPIO30/TSEC_1588_ALARM_OUT2/EC1_COL General Purpose Input / Output AK35 I/O LVDD 25 GPIO31/TSEC_1588_PULSE_OUT2/EC1_CRS General Purpose Input / Output AJ34 I/O LVDD 25 System Control PORESET Power On Reset AP17 I OVDD — HRESET Hard Reset AR17 I/O OVDD 1, 2 RESET_REQ Reset Request AT16 O OVDD 35 CKSTP_OUT Checkstop Out AM19 O OVDD 1, 2 Debug EVT0 Event 0 AJ17 I/O OVDD 20 EVT1 Event 1 AK17 I/O OVDD — EVT2 Event 2 AN16 I/O OVDD — EVT3 Event 3 AK16 I/O OVDD — EVT4 Event 4 AM16 I/O OVDD — EVT5/IIC4_SCL Event 5 AG14 I/O OVDD — EVT6/IIC4_SDA Event 6 AL15 I/O OVDD — EVT7/DMA2_DACK0/ALT_MSRCID0 Event 7 AG19 I/O OVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 27 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes EVT8/DMA2_DDONE0/ALT_MSRCID1 Event 8 AP20 I/O OVDD — EVT9/IRQ_OUT Event 9 AK14 I/O OVDD — MDVAL Debug Data Valid AR15 O OVDD — MSRCID0 Debug Source ID 0 AH20 O OVDD 4,20,35 MSRCID1 Debug Source ID 1 AJ19 O OVDD — MSRCID2 Debug Source ID 2 AH18 O OVDD — ALT_MDVAL/DMA2_DREQ0/GPIO20 Alternate Debug Data Valid AJ20 O OVDD 26 ALT_MSRCID0/DMA2_DACK0/EVT7 Alternate Debug Source ID 0 AG19 O OVDD 26 ALT_MSRCID1/DMA2_DDONE0/EVT8 Alternate Debug Source ID 1 AP20 O OVDD 26 CLK_OUT Clock Out AK20 O OVDD 6 Clock RTC Real Time Clock AN24 I OVDD — SYSCLK System Clock AT23 I OVDD — JTAG TCK Test Clock AR22 I OVDD — TDI Test Data In AN17 I OVDD 7 TDO Test Data Out AP15 O OVDD 6 TMS Test Mode Select AR20 I OVDD 7 TRST Test Reset AR19 I OVDD 7 DFT SCAN_MODE Scan Mode AL17 I OVDD 12 TEST_SEL Test Mode Select AT21 I OVDD 28 TEST_SEL2 Test Mode Select 2 AP11 I OVDD 44 AR21 O OVDD 35 Power Management ASLEEP Asleep Input/Output Voltage Select IO_VSEL0 I/O Voltage Select AL18 I OVDD 30 IO_VSEL1 I/O Voltage Select AP18 I OVDD 30 IO_VSEL2 I/O Voltage Select AK18 I OVDD 30 IO_VSEL3 I/O Voltage Select AM18 I OVDD 30 IO_VSEL4 I/O Voltage Select AH19 I OVDD 30 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 28 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes Core Voltage ID Signals VID_VDD_CA_CB0 Core voltage ID 0 AT14 O OVDD 42 VID_VDD_CA_CB1 Core voltage ID 1 AP14 O OVDD 42 VID_VDD_CA_CB2 Core voltage ID 2 AN13 O OVDD 42 VID_VDD_CA_CB3 Core voltage ID 3 AM12 O OVDD 42 Power and Ground Signals GND Ground C3 — — — GND Ground B5 — — — GND Ground F3 — — — GND Ground E5 — — — GND Ground D7 — — — GND Ground C9 — — — GND Ground B11 — — — GND Ground J3 — — — GND Ground H5 — — — GND Ground G7 — — — GND Ground G17 — — — GND Ground F9 — — — GND Ground E11 — — — GND Ground D13 — — — GND Ground C15 — — — GND Ground K19 — — — GND Ground B20 — — — GND Ground B22 — — — GND Ground E19 — — — GND Ground L22 — — — GND Ground J23 — — — GND Ground A22 — — — GND Ground L20 — — — GND Ground A26 — — — GND Ground A18 — — — GND Ground E17 — — — GND Ground F23 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 29 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GND Ground J27 — — — GND Ground F27 — — — GND Ground G21 — — — GND Ground K25 — — — GND Ground B18 — — — GND Ground L18 — — — GND Ground J21 — — — GND Ground M27 — — — GND Ground G13 — — — GND Ground F15 — — — GND Ground H11 — — — GND Ground J9 — — — GND Ground K7 — — — GND Ground L5 — — — GND Ground M3 — — — GND Ground R3 — — — GND Ground P5 — — — GND Ground N7 — — — GND Ground M9 — — — GND Ground V25 — — — GND Ground R9 — — — GND Ground T7 — — — GND Ground U5 — — — GND Ground U3 — — — GND Ground Y3 — — — GND Ground Y5 — — — GND Ground W7 — — — GND Ground V10 — — — GND Ground AA9 — — — GND Ground AB7 — — — GND Ground AC5 — — — GND Ground AD3 — — — GND Ground AD9 — — — GND Ground AE7 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 30 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GND Ground AF5 — — — GND Ground AG3 — — — GND Ground AG9 — — — GND Ground AH7 — — — GND Ground AJ5 — — — GND Ground AK3 — — — GND Ground AN3 — — — GND Ground AM5 — — — GND Ground AL7 — — — GND Ground AK9 — — — GND Ground AJ11 — — — GND Ground AH13 — — — GND Ground AR5 — — — GND Ground AP7 — — — GND Ground AN9 — — — GND Ground AM11 — — — GND Ground AL13 — — — GND Ground AK15 — — — GND Ground AG18 — — — GND Ground AR11 — — — GND Ground AP13 — — — GND Ground AN15 — — — GND Ground AM17 — — — GND Ground AK19 — — — GND Ground AF13 — — — GND Ground AR18 — — — GND Ground AB27 — — — GND Ground AP19 — — — GND Ground AH22 — — — GND Ground AM21 — — — GND Ground AL29 — — — GND Ground AR16 — — — GND Ground AT22 — — — GND Ground AP23 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 31 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GND Ground AR32 — — — GND Ground AK28 — — — GND Ground AE27 — — — GND Ground L16 — — — GND Ground AP34 — — — GND Ground AJ32 — — — GND Ground AN30 — — — GND Ground AH34 — — — GND Ground AT36 — — — GND Ground AL34 — — — GND Ground AM32 — — — GND Ground AE26 — — — GND Ground AC26 — — — GND Ground AA26 — — — GND Ground W26 — — — GND Ground U26 — — — GND Ground R26 — — — GND Ground N26 — — — GND Ground M11 — — — GND Ground P11 — — — GND Ground T11 — — — GND Ground V11 — — — GND Ground Y11 — — — GND Ground AB11 — — — GND Ground AD11 — — — GND Ground AE12 — — — GND Ground AC12 — — — GND Ground AA12 — — — GND Ground W12 — — — GND Ground U12 — — — GND Ground R12 — — — GND Ground N12 — — — GND Ground M13 — — — GND Ground P13 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 32 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GND Ground T13 — — — GND Ground V13 — — — GND Ground Y13 — — — GND Ground AB13 — — — GND Ground AD13 — — — GND Ground AE14 — — — GND Ground AC14 — — — GND Ground AA14 — — — GND Ground W14 — — — GND Ground U14 — — — GND Ground R14 — — — GND Ground N14 — — — GND Ground L14 — — — GND Ground M15 — — — GND Ground P15 — — — GND Ground T15 — — — GND Ground V15 — — — GND Ground Y15 — — — GND Ground AB15 — — — GND Ground AD15 — — — GND Ground AF15 — — — GND Ground W16 — — — GND Ground AC16 — — — GND Ground AA16 — — — GND Ground AE16 — — — GND Ground U16 — — — GND Ground R16 — — — GND Ground N16 — — — GND Ground M17 — — — GND Ground P17 — — — GND Ground T17 — — — GND Ground N18 — — — GND Ground R18 — — — GND Ground U18 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 33 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GND Ground Y17 — — — GND Ground AB17 — — — GND Ground AD17 — — — GND Ground AF17 — — — GND Ground W18 — — — GND Ground AC18 — — — GND Ground AA18 — — — GND Ground AE18 — — — GND Ground AF19 — — — GND Ground AD19 — — — GND Ground AB19 — — — GND Ground Y19 — — — GND Ground V19 — — — GND Ground T19 — — — GND Ground P19 — — — GND Ground M19 — — — GND Ground N20 — — — GND Ground R20 — — — GND Ground U20 — — — GND Ground AE20 — — — GND Ground AA20 — — — GND Ground AC20 — — — GND Ground W20 — — — GND Ground AF21 — — — GND Ground AD21 — — — GND Ground AB21 — — — GND Ground Y21 — — — GND Ground V21 — — — GND Ground T21 — — — GND Ground P21 — — — GND Ground M21 — — — GND Ground AE22 — — — GND Ground AC22 — — — GND Ground AA22 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 34 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GND Ground W22 — — — GND Ground U22 — — — GND Ground R22 — — — GND Ground N22 — — — GND Ground AF23 — — — GND Ground AD23 — — — GND Ground AB23 — — — GND Ground Y23 — — — GND Ground V23 — — — GND Ground T23 — — — GND Ground P23 — — — GND Ground M23 — — — GND Ground L24 — — — GND Ground N24 — — — GND Ground R24 — — — GND Ground U24 — — — GND Ground W24 — — — GND Ground AA24 — — — GND Ground AC24 — — — GND Ground AE24 — — — GND Ground AF25 — — — GND Ground AD25 — — — GND Ground AB25 — — — GND Ground Y25 — — — GND Ground P27 — — — GND Ground V17 — — — GND Ground T25 — — — GND Ground P25 — — — GND Ground M25 — — — GND Ground T27 — — — GND Ground V27 — — — GND Ground Y27 — — — GND Ground AD27 — — — GND Ground L12 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 35 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GND Ground AG16 — — — GND Ground W15 — — — GND Ground W19 — — — GND Ground AA19 — — — GND Ground Y20 — — — GND Ground AB14 — — — GND Ground AA21 — — — GND Ground Y16 — — — GND Ground AA15 — — — GND Ground AC15 — — — GND Ground AA17 — — — GND Ground AC17 — — — GND Ground W17 — — — GND Ground Y18 — — — GND Ground AB18 — — — GND Ground AB16 — — — GND Ground AC19 — — — GND Ground AB20 — — — XGND SerDes Transceiver GND AA30 — — — XGND SerDes Transceiver GND AB32 — — — XGND SerDes Transceiver GND AC30 — — — XGND SerDes Transceiver GND AC34 — — — XGND SerDes Transceiver GND AD30 — — — XGND SerDes Transceiver GND AD31 — — — XGND SerDes Transceiver GND AF32 — — — XGND SerDes Transceiver GND AG30 — — — XGND SerDes Transceiver GND D33 — — — XGND SerDes Transceiver GND E28 — — — XGND SerDes Transceiver GND E30 — — — XGND SerDes Transceiver GND F32 — — — XGND SerDes Transceiver GND G29 — — — XGND SerDes Transceiver GND G31 — — — XGND SerDes Transceiver GND H29 — — — XGND SerDes Transceiver GND H32 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 36 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes XGND SerDes Transceiver GND H34 — — — XGND SerDes Transceiver GND J29 — — — XGND SerDes Transceiver GND J31 — — — XGND SerDes Transceiver GND K28 — — — XGND SerDes Transceiver GND K29 — — — XGND SerDes Transceiver GND L29 — — — XGND SerDes Transceiver GND L32 — — — XGND SerDes Transceiver GND M30 — — — XGND SerDes Transceiver GND N29 — — — XGND SerDes Transceiver GND N30 — — — XGND SerDes Transceiver GND N32 — — — XGND SerDes Transceiver GND P29 — — — XGND SerDes Transceiver GND P34 — — — XGND SerDes Transceiver GND R30 — — — XGND SerDes Transceiver GND R32 — — — XGND SerDes Transceiver GND U29 — — — XGND SerDes Transceiver GND U31 — — — XGND SerDes Transceiver GND V29 — — — XGND SerDes Transceiver GND V31 — — — XGND SerDes Transceiver GND W30 — — — XGND SerDes Transceiver GND Y32 — — — XGND SerDes Transceiver GND AH31 — — — XGND SerDes Transceiver GND Y28 — — — SGND SerDes Core Logic GND A28 — — — SGND SerDes Core Logic GND A32 — — — SGND SerDes Core Logic GND A36 — — — SGND SerDes Core Logic GND AA34 — — — SGND SerDes Core Logic GND AB36 — — — SGND SerDes Core Logic GND AD35 — — — SGND SerDes Core Logic GND AE34 — — — SGND SerDes Core Logic GND AF36 — — — SGND SerDes Core Logic GND AG33 — — — SGND SerDes Core Logic GND B30 — — — SGND SerDes Core Logic GND B34 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 37 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes SGND SerDes Core Logic GND C29 — — — SGND SerDes Core Logic GND C33 — — — SGND SerDes Core Logic GND D31 — — — SGND SerDes Core Logic GND D35 — — — SGND SerDes Core Logic GND E35 — — — SGND SerDes Core Logic GND G34 — — — SGND SerDes Core Logic GND G36 — — — SGND SerDes Core Logic GND J35 — — — SGND SerDes Core Logic GND K33 — — — SGND SerDes Core Logic GND L36 — — — SGND SerDes Core Logic GND M34 — — — SGND SerDes Core Logic GND N35 — — — SGND SerDes Core Logic GND R33 — — — SGND SerDes Core Logic GND R36 — — — SGND SerDes Core Logic GND T35 — — — SGND SerDes Core Logic GND U34 — — — SGND SerDes Core Logic GND V36 — — — SGND SerDes Core Logic GND W33 — — — SGND SerDes Core Logic GND Y35 — — — SGND SerDes Core Logic GND AH35 — — — SGND SerDes Core Logic GND AH33 — — — SGND SerDes Core Logic GND AF29 — — — AGND_SRDS1 SerDes PLL1 GND B33 — — — AGND_SRDS2 SerDes PLL2 GND T36 — — — AGND_SRDS3 SerDes PLL3 GND AE36 — — — AGND_SRDS4 SerDes PLL4 GND T28 — — — SENSEGND_PL1 Platform GND Sense 1 AF12 — — 8 SENSEGND_PL2 Platform GND Sense 2 K27 — — 8 SENSEGND_CA Core Group A GND Sense K17 — — 8 USB1_AGND USB1 PHY Transceiver GND AH24 — — — USB1_AGND USB1 PHY Transceiver GND AJ24 — — — USB1_AGND USB1 PHY Transceiver GND AL25 — — — USB1_AGND USB1 PHY Transceiver GND AM25 — — — USB1_AGND USB1 PHY Transceiver GND AR25 — — — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 38 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes USB1_AGND USB1 PHY Transceiver GND AR26 — — — USB1_AGND USB1 PHY Transceiver GND AR27 — — — USB1_AGND USB1 PHY Transceiver GND AR28 — — — USB1_AGND USB1 PHY Transceiver GND AT25 — — — USB1_AGND USB1 PHY Transceiver GND AT28 — — — USB2_AGND USB2 PHY Transceiver GND AH27 — — — USB2_AGND USB2 PHY Transceiver GND AL28 — — — USB2_AGND USB2 PHY Transceiver GND AM28 — — — USB2_AGND USB2 PHY Transceiver GND AN25 — — — USB2_AGND USB2 PHY Transceiver GND AN26 — — — USB2_AGND USB2 PHY Transceiver GND AN27 — — — USB2_AGND USB2 PHY Transceiver GND AN28 — — — USB2_AGND USB2 PHY Transceiver GND AP25 — — — USB2_AGND USB2 PHY Transceiver GND AP28 — — — OVDD General I/O Supply AN22 — OVDD — OVDD General I/O Supply AJ14 — OVDD — OVDD General I/O Supply AJ18 — OVDD — OVDD General I/O Supply AL16 — OVDD — OVDD General I/O Supply AJ12 — OVDD — OVDD General I/O Supply AN18 — OVDD — OVDD General I/O Supply AG21 — OVDD — OVDD General I/O Supply AL20 — OVDD — OVDD General I/O Supply AT15 — OVDD — OVDD General I/O Supply AJ23 — OVDD — OVDD General I/O Supply AP16 — OVDD — OVDD General I/O Supply AR24 — OVDD — CVDD eSPI & eSDHC Supply AG24 — CVDD — CVDD eSPI & eSDHC Supply AJ29 — CVDD — CVDD eSPI & eSDHC Supply AP29 — CVDD — GVDD DDR Supply B2 — GVDD — GVDD DDR Supply B8 — GVDD — GVDD DDR Supply B14 — GVDD — GVDD DDR Supply C18 — GVDD — GVDD DDR Supply C12 — GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 39 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GVDD DDR Supply C6 — GVDD — GVDD DDR Supply D4 — GVDD — GVDD DDR Supply D10 — GVDD — GVDD DDR Supply D16 — GVDD — GVDD DDR Supply E14 — GVDD — GVDD DDR Supply E8 — GVDD — GVDD DDR Supply E2 — GVDD — GVDD DDR Supply F6 — GVDD — GVDD DDR Supply F12 — GVDD — GVDD DDR Supply AR8 — GVDD — GVDD DDR Supply G4 — GVDD — GVDD DDR Supply G10 — GVDD — GVDD DDR Supply G16 — GVDD — GVDD DDR Supply H14 — GVDD — GVDD DDR Supply H8 — GVDD — GVDD DDR Supply H2 — GVDD — GVDD DDR Supply J6 — GVDD — GVDD DDR Supply K10 — GVDD — GVDD DDR Supply K4 — GVDD — GVDD DDR Supply L2 — GVDD — GVDD DDR Supply L8 — GVDD — GVDD DDR Supply M6 — GVDD — GVDD DDR Supply N4 — GVDD — GVDD DDR Supply N10 — GVDD — GVDD DDR Supply P8 — GVDD — GVDD DDR Supply P2 — GVDD — GVDD DDR Supply R6 — GVDD — GVDD DDR Supply T10 — GVDD — GVDD DDR Supply T4 — GVDD — GVDD DDR Supply J12 — GVDD — GVDD DDR Supply U2 — GVDD — GVDD DDR Supply U8 — GVDD — GVDD DDR Supply V7 — GVDD — GVDD DDR Supply AK10 — GVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 40 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes GVDD DDR Supply W10 — GVDD — GVDD DDR Supply AA6 — GVDD — GVDD DDR Supply AR2 — GVDD — GVDD DDR Supply Y2 — GVDD — GVDD DDR Supply Y8 — GVDD — GVDD DDR Supply AC2 — GVDD — GVDD DDR Supply AD6 — GVDD — GVDD DDR Supply AE10 — GVDD — GVDD DDR Supply AE4 — GVDD — GVDD DDR Supply AF2 — GVDD — GVDD DDR Supply AF8 — GVDD — GVDD DDR Supply AB4 — GVDD — GVDD DDR Supply AB10 — GVDD — GVDD DDR Supply AC8 — GVDD — GVDD DDR Supply AG6 — GVDD — GVDD DDR Supply AH10 — GVDD — GVDD DDR Supply AH4 — GVDD — GVDD DDR Supply AJ2 — GVDD — GVDD DDR Supply AJ8 — GVDD — GVDD DDR Supply AR14 — GVDD — GVDD DDR Supply AK6 — GVDD — GVDD DDR Supply AL4 — GVDD — GVDD DDR Supply AL10 — GVDD — GVDD DDR Supply AM2 — GVDD — GVDD DDR Supply AM8 — GVDD — GVDD DDR Supply AP10 — GVDD — GVDD DDR Supply AN12 — GVDD — GVDD DDR Supply AN6 — GVDD — GVDD DDR Supply AP4 — GVDD — BVDD Local Bus Supply B24 — BVDD — BVDD Local Bus Supply K22 — BVDD — BVDD Local Bus Supply F20 — BVDD — BVDD Local Bus Supply F26 — BVDD — BVDD Local Bus Supply E24 — BVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 41 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes BVDD Local Bus Supply E22 — BVDD — BVDD Local Bus Supply K24 — BVDD — BVDD Local Bus Supply H20 — BVDD — BVDD Local Bus Supply H18 — BVDD — SVDD SerDes Core Logic Supply A30 — SVDD — SVDD SerDes Core Logic Supply A34 — SVDD — SVDD SerDes Core Logic Supply AA33 — SVDD — SVDD SerDes Core Logic Supply AB35 — SVDD — SVDD SerDes Core Logic Supply AD36 — SVDD — SVDD SerDes Core Logic Supply AE33 — SVDD — SVDD SerDes Core Logic Supply AF35 — SVDD — SVDD SerDes Core Logic Supply AG34 — SVDD — SVDD SerDes Core Logic Supply B28 — SVDD — SVDD SerDes Core Logic Supply B32 — SVDD — SVDD SerDes Core Logic Supply B36 — SVDD — SVDD SerDes Core Logic Supply C31 — SVDD — SVDD SerDes Core Logic Supply C34 — SVDD — SVDD SerDes Core Logic Supply C35 — SVDD — SVDD SerDes Core Logic Supply D29 — SVDD — SVDD SerDes Core Logic Supply E36 — SVDD — SVDD SerDes Core Logic Supply F34 — SVDD — SVDD SerDes Core Logic Supply G35 — SVDD — SVDD SerDes Core Logic Supply J36 — SVDD — SVDD SerDes Core Logic Supply K34 — SVDD — SVDD SerDes Core Logic Supply L35 — SVDD — SVDD SerDes Core Logic Supply M33 — SVDD — SVDD SerDes Core Logic Supply N36 — SVDD — SVDD SerDes Core Logic Supply R34 — SVDD — SVDD SerDes Core Logic Supply R35 — SVDD — SVDD SerDes Core Logic Supply U33 — SVDD — SVDD SerDes Core Logic Supply V35 — SVDD — SVDD SerDes Core Logic Supply W34 — SVDD — SVDD SerDes Core Logic Supply Y36 — SVDD — SVDD SerDes Core Logic Supply AH36 — SVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 42 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes S1VDD SerDes Core Logic Supply AC29 — SVDD — S1VDD SerDes Core Logic Supply AG28 — SVDD — XVDD SerDes Transceiver Supply AA29 — XVDD — XVDD SerDes Transceiver Supply AB30 — XVDD — XVDD SerDes Transceiver Supply AB31 — XVDD — XVDD SerDes Transceiver Supply AC33 — XVDD — XVDD SerDes Transceiver Supply AD32 — XVDD — XVDD SerDes Transceiver Supply AE30 — XVDD — XVDD SerDes Transceiver Supply AF31 — XVDD — XVDD SerDes Transceiver Supply E32 — XVDD — XVDD SerDes Transceiver Supply E33 — XVDD — XVDD SerDes Transceiver Supply F28 — XVDD — XVDD SerDes Transceiver Supply F30 — XVDD — XVDD SerDes Transceiver Supply G32 — XVDD — XVDD SerDes Transceiver Supply H31 — XVDD — XVDD SerDes Transceiver Supply H33 — XVDD — XVDD SerDes Transceiver Supply J28 — XVDD — XVDD SerDes Transceiver Supply J30 — XVDD — XVDD SerDes Transceiver Supply J32 — XVDD — XVDD SerDes Transceiver Supply K30 — XVDD — XVDD SerDes Transceiver Supply L30 — XVDD — XVDD SerDes Transceiver Supply L31 — XVDD — XVDD SerDes Transceiver Supply M29 — XVDD — XVDD SerDes Transceiver Supply N31 — XVDD — XVDD SerDes Transceiver Supply P30 — XVDD — XVDD SerDes Transceiver Supply P33 — XVDD — XVDD SerDes Transceiver Supply R29 — XVDD — XVDD SerDes Transceiver Supply R31 — XVDD — XVDD SerDes Transceiver Supply T29 — XVDD — XVDD SerDes Transceiver Supply T32 — XVDD — XVDD SerDes Transceiver Supply U30 — XVDD — XVDD SerDes Transceiver Supply V30 — XVDD — XVDD SerDes Transceiver Supply V32 — XVDD — XVDD SerDes Transceiver Supply W29 — XVDD — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 43 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes XVDD SerDes Transceiver Supply Y31 — XVDD — XVDD SerDes Transceiver Supply AH32 — XVDD — X1VDD SerDes Transceiver Supply AG27 — XVDD — VDD_LL SerDes B4 Logic supply AC28 — VDD_PL 43 LVDD Ethernet Controller 1 and 2 Supply AK33 — LVDD — LVDD Ethernet Controller 1 and 2 Supply AP31 — LVDD — LVDD Ethernet Controller 1 and 2 Supply AL31 — LVDD — LVDD Ethernet Controller 1 and 2 Supply AN33 — LVDD — LVDD Ethernet Controller 1 and 2 Supply AJ35 — LVDD — LVDD Ethernet Controller 1 and 2 Supply AR35 — LVDD — LVDD Ethernet Controller 1 and 2 Supply AM35 — LVDD — POVDD Fuse Programming Override Supply AT17 — POVDD 33 VDD_PL Platform Supply M26 — VDD_PL — VDD_PL Platform Supply P26 — VDD_PL — VDD_PL Platform Supply T26 — VDD_PL — VDD_PL Platform Supply V26 — VDD_PL — VDD_PL Platform Supply Y26 — VDD_PL — VDD_PL Platform Supply AB26 — VDD_PL — VDD_PL Platform Supply AD26 — VDD_PL — VDD_PL Platform Supply N11 — VDD_PL — VDD_PL Platform Supply R11 — VDD_PL — VDD_PL Platform Supply W11 — VDD_PL — VDD_PL Platform Supply AA11 — VDD_PL — VDD_PL Platform Supply AE11 — VDD_PL — VDD_PL Platform Supply M12 — VDD_PL — VDD_PL Platform Supply P12 — VDD_PL — VDD_PL Platform Supply T12 — VDD_PL — VDD_PL Platform Supply V12 — VDD_PL — VDD_PL Platform Supply Y12 — VDD_PL — VDD_PL Platform Supply AB12 — VDD_PL — VDD_PL Platform Supply AD12 — VDD_PL — VDD_PL Platform Supply AE13 — VDD_PL — VDD_PL Platform Supply AE15 — VDD_PL — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 44 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes VDD_PL Platform Supply V16 — VDD_PL — VDD_PL Platform Supply AE17 — VDD_PL — VDD_PL Platform Supply L11 — VDD_PL — VDD_PL Platform Supply AE19 — VDD_PL — VDD_PL Platform Supply U11 — VDD_PL — VDD_PL Platform Supply AC11 — VDD_PL — VDD_PL Platform Supply V20 — VDD_PL — VDD_PL Platform Supply AE21 — VDD_PL — VDD_PL Platform Supply V22 — VDD_PL — VDD_PL Platform Supply U13 — VDD_PL — VDD_PL Platform Supply R27 — VDD_PL — VDD_PL Platform Supply U23 — VDD_PL — VDD_PL Platform Supply W23 — VDD_PL — VDD_PL Platform Supply AA27 — VDD_PL — VDD_PL Platform Supply AC27 — VDD_PL — VDD_PL Platform Supply AE23 — VDD_PL — VDD_PL Platform Supply M24 — VDD_PL — VDD_PL Platform Supply P24 — VDD_PL — VDD_PL Platform Supply T24 — VDD_PL — VDD_PL Platform Supply V24 — VDD_PL — VDD_PL Platform Supply Y24 — VDD_PL — VDD_PL Platform Supply AB24 — VDD_PL — VDD_PL Platform Supply AD24 — VDD_PL — VDD_PL Platform Supply N25 — VDD_PL — VDD_PL Platform Supply R25 — VDD_PL — VDD_PL Platform Supply U25 — VDD_PL — VDD_PL Platform Supply W25 — VDD_PL — VDD_PL Platform Supply AA25 — VDD_PL — VDD_PL Platform Supply AC25 — VDD_PL — VDD_PL Platform Supply N27 — VDD_PL — VDD_PL Platform Supply U27 — VDD_PL — VDD_PL Platform Supply W28 — VDD_PL — VDD_PL Platform Supply AE25 — VDD_PL — VDD_PL Platform Supply AF24 — VDD_PL — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 45 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes VDD_PL Platform Supply AF22 — VDD_PL — VDD_PL Platform Supply AF20 — VDD_PL — VDD_PL Platform Supply AF16 — VDD_PL — VDD_PL Platform Supply W13 — VDD_PL — VDD_PL Platform Supply AF18 — VDD_PL — VDD_PL Platform Supply V14 — VDD_PL — VDD_PL Platform Supply V18 — VDD_PL — VDD_PL Platform Supply L13 — VDD_PL — VDD_PL Platform Supply L15 — VDD_PL — VDD_PL Platform Supply L17 — VDD_PL — VDD_PL Platform Supply L19 — VDD_PL — VDD_PL Platform Supply L21 — VDD_PL — VDD_PL Platform Supply L23 — VDD_PL — VDD_PL Platform Supply L25 — VDD_PL — VDD_PL Platform Supply AF14 — VDD_PL — VDD_PL Platform Supply N23 — VDD_PL — VDD_PL Platform Supply R23 — VDD_PL — VDD_PL Platform Supply AA23 — VDD_PL — VDD_PL Platform Supply AC23 — VDD_PL — VDD_PL Platform Supply U21 — VDD_PL — VDD_PL Platform Supply W21 — VDD_PL — VDD_PL Platform Supply U15 — VDD_PL — VDD_PL Platform Supply AC21 — VDD_PL — VDD_PL Platform Supply AD22 — VDD_PL — VDD_PL Platform Supply M22 — VDD_PL — VDD_PL Platform Supply N13 — VDD_PL — VDD_PL Platform Supply AC13 — VDD_PL — VDD_PL Platform Supply P22 — VDD_PL — VDD_PL Platform Supply T22 — VDD_PL — VDD_PL Platform Supply Y22 — VDD_PL — VDD_PL Platform Supply AB22 — VDD_PL — VDD_PL Platform Supply AA13 — VDD_PL — VDD_PL Platform Supply R13 — VDD_PL — VDD_PL Platform Supply M14 — VDD_PL — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 46 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes VDD_PL Platform Supply U17 — VDD_PL — VDD_PL Platform Supply U19 — VDD_PL — VDD_PL Platform Supply T14 — VDD_PL — VDD_PL Platform Supply AD14 — VDD_PL — VDD_PL Platform Supply AD16 — VDD_PL — VDD_PL Platform Supply AD18 — VDD_PL — VDD_PL Platform Supply AD20 — VDD_PL — VDD_PL Platform Supply Y14 — VDD_PL — VDD_CA Core/L2 Group A Supply T20 — VDD_CA — VDD_CA Core/L2 Group A Supply P20 — VDD_CA — VDD_CA Core/L2 Group A Supply R21 — VDD_CA — VDD_CA Core/L2 Group A Supply R19 — VDD_CA — VDD_CA Core/L2 Group A Supply P14 — VDD_CA — VDD_CA Core/L2 Group A Supply N19 — VDD_CA — VDD_CA Core/L2 Group A Supply M20 — VDD_CA — VDD_CA Core/L2 Group A Supply N21 — VDD_CA — VDD_CA Core/L2 Group A Supply M16 — VDD_CA — VDD_CA Core/L2 Group A Supply N15 — VDD_CA — VDD_CA Core/L2 Group A Supply P16 — VDD_CA — VDD_CA Core/L2 Group A Supply T16 — VDD_CA — VDD_CA Core/L2 Group A Supply R17 — VDD_CA — VDD_CA Core/L2 Group A Supply T18 — VDD_CA — VDD_CA Core/L2 Group A Supply R15 — VDD_CA — VDD_CA Core/L2 Group A Supply N17 — VDD_CA — VDD_CA Core/L2 Group A Supply M18 — VDD_CA — VDD_CA Core/L2 Group A Supply P18 — VDD_CA — VDD_LP Low Power Security Monitor Supply AD28 — VDD_LP — AVDD_CC1 Core Cluster PLL1 Supply A20 — — 13 AVDD_CC2 Core Cluster PLL2 Supply AT18 — — 13 AVDD_PLAT Platform PLL Supply AT20 — — 13 AVDD_DDR DDR PLL Supply A19 — — 13 AVDD_FM FMan PLL Supply AT19 — — 13 AVDD_SRDS1 SerDes PLL1 Supply A33 — — 13 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 47 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes AVDD_SRDS2 SerDes PLL2 Supply U36 — — 13 AVDD_SRDS3 SerDes PLL3 Supply AE35 — — 13 AVDD_SRDS4 SerDes PLL4 Supply R28 — — 13 SENSEVDD_PL1 Platform Vdd Sense AF11 — — 8 SENSEVDD_PL2 Platform Vdd Sense L27 — — 8 SENSEVDD_CA Core Group A Vdd Sense K16 — — 8 USB1_VDD_3P3 USB1 PHY Transceiver 3.3V Supply AL24 — — — USB1_VDD_3P3 USB1 PHY Transceiver 3.3V Supply AJ25 — — — USB2_VDD_3P3 USB2 PHY Transceiver 3.3V Supply AJ26 — — — USB2_VDD_3P3 USB2 PHY Transceiver 3.3V Supply AJ27 — — — USB1_VDD_1P0 USB1 PHY PLL 1.0V Supply AH25 — — — USB2_VDD_1P0 USB2 PHY PLL 1.0V Supply AH26 — — — B19 I GVDD/2 — Analog Signals MVREF SSTL_1.5/1.35 Reference Voltage SD_IMP_CAL_TX SerDes transmitter Impedance Calibration AF30 I 200Ω (±1%) to XVDD 23 SD1_IMP_CAL_TX SerDes transmitter Impedance Calibration AA28 I 200Ω (±1%) to XVDD 23 SD_IMP_CAL_RX SerDes receiver Impedance Calibration B27 I 200Ω (±1%) to SVDD 24 SD1_IMP_CAL_RX SerDes receiver Impedance Calibration AF26 I 200Ω (±1%) to SVDD 24 TEMP_ANODE Temperature Diode Anode C21 — internal diode 9 TEMP_CATHODE Temperature Diode Cathode B21 — internal diode 9 USB1_IBIAS_REXT USB PHY1 Reference Bias Current Generation AM26 — — 36 USB2_IBIAS_REXT USB PHY2 Reference Bias Current Generation AM27 — — 36 USB1_VDD_1P8_DECAP USB1 PHY 1.8V Output to External Decap AL26 — — 37 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 48 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal USB2_VDD_1P8_DECAP Signal description USB2 PHY 1.8V Output to External Decap Package Pin Power pin number type supply Notes AL27 — — 37 No Connection Pins NC_A27 No Connection A27 — — 11 NC_B26 No Connection B26 — — 11 NC_C19 No Connection C19 — — 11 NC_C20 No Connection C20 — — 11 NC_C26 No Connection C26 — — 11 NC_C27 No Connection C27 — — 11 NC_D18 No Connection D18 — — 11 NC_D27 No Connection D27 — — 11 NC_E16 No Connection E16 — — 11 NC_E27 No Connection E27 — — 11 NC_G27 No Connection G27 — — 11 NC_H12 No Connection H12 — — 11 NC_H13 No Connection H13 — — 11 NC_H15 No Connection H15 — — 11 NC_H27 No Connection H27 — — 11 NC_J11 No Connection J11 — — 11 NC_J13 No Connection J13 — — 11 NC_J14 No Connection J14 — — 11 NC_K11 No Connection K11 — — 11 NC_K12 No Connection K12 — — 11 NC_K13 No Connection K13 — — 11 NC_K14 No Connection K14 — — 11 NC_W27 No Connection W27 — — 11 NC_AG15 No Connection AG15 — — 11 Reserved Pins Reserve_A21 — A21 — — 41 Reserve_A25 — A25 — — 11 Reserve_C32 — C32 — — 11 Reserve_D32 — D32 — — 11 Reserve_F1 — F1 — — 11 Reserve_F2 — F2 — — 11 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 49 Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes Reserve_G1 — G1 — — 11 Reserve_G2 — G2 — — 11 Reserve_L28 — L28 — GND 21 Reserve_M28 — M28 — GND 21 Reserve_N28 — N28 — GND 21 Reserve_P28 — P28 — GND 21 Reserve_U32 — U32 — — 11 Reserve_U35 — U35 — — 11 Reserve_AD33 — AD33 — — 11 Reserve_AD34 — AD34 — — 11 Reserve_AG11 — AG11 — GND 21 Reserve_AG12 — AG12 — GND 21 Reserve_AG26 — AG26 — — 11 Reserve_AG29 — AG29 — — 11 Reserve_AH11 — AH11 — GND 21 Reserve_AH12 — AH12 — GND 21 Reserve_AH30 — AH30 — — 11 Reserve_AK1 — AK1 — — 11 Reserve_AK2 — AK2 — — 11 Reserve_AL1 — AL1 — — 11 Reserve_AL2 — AL2 — — 11 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 50 Freescale Semiconductor Pin assignments and reset states Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes Notes: 1. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD. 2. This pin is an open drain signal. 3. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pull up or active driver is needed. 4. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan. 5. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to BVDD, to ensure no random chip select assertion due to possible noise, and so forth. 6. This output is actively driven during reset rather than being three-stated during reset. 7. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 8. These pins are connected to the correspondent power and ground nets internally and may be connected as a differential pair to be used by the voltage regulators with remote sense function. 9. These pins may be connected to a thermal diode monitoring device such as the ADT7461A only with a clear understanding that proper thermal diode operation is not implied and the thermal diode feature may not be available in the production device. 11. Do not connect. 12. These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ) to OVDD for normal device operation. 13. Independent supplies derived from board VDD_PL (Core clusters, Platform, DDR) or SVDD (SerDes). 14. Recommend a pull-up resistor of 1-kΩ be placed on this pin to OVDD if I2C interface is used. 15. This pin requires an external 1-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. 16. For DDR3 and DDR3L, Dn_MDIC[0] is grounded through an 40.2-Ω (half-strength mode) precision 1% resistor and Dn_MDIC[1] is connected to GVDD through an 40.2-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the DDR3 and DDR3L IOs. 18. These pins should be pulled up to 1.2V through a 180Ω ± 1% resistor for EM2_MDC and a 330Ω ± 1% resistor for EM2_MDIO. 20. Pin has a weak internal pull-up. 21. These pins should be pulled to ground (GND). 22. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels. LVDD must be powered to use this interface. 23. This pin requires a 200-Ω pull-up to XVDD. 24. This pin requires a 200-Ω pull-up to SVDD. 25. This GPIO pin is on LVDD power plane, not OVDD. 26. Functionally, this pin is an I/O, but may act as an output only or an input only depending on the pin mux configuration defined by the RCW. 27. See Section 3.6, “Connection recommendations,” for additional details on this signal. 28. This signal must be pulled low to GND. 30. Warning, incorrect voltage select settings can lead to irreversible device damage. See Section 3.2, “Supply power default setting.” 31. SDHC_DAT[4:7] require CVDD = 3.3 V when muxed extended SDHC data signals are enabled via the RCW[SPI] field. 32. The cfg_xvdd_sel(LAD[26]) reset configuration pin must select the correct voltage that is being supplied on the XVDD pin. Incorrect voltage select settings can lead to irreversible device damage. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 51 Electrical characteristics Table 1. Pins listed by bus (continued) Signal Signal description Package Pin Power pin number type supply Notes 33. See Section 2.2, “Power-up sequencing and Section 5, “Security fuse processor,” for additional details on this signal. 35. Pin must NOT be pulled down by a resistor or the component it is connected to during power-on reset. 36. This pin should be connected to GND through a 10kΩ ± 0.1% resistor with a low temperature coefficient of ≤ 25ppm/°C for bias generation. 37. A 1uF to 1.5uF capacitor connected to GND is required on this signal. A list of recommended capacitors are shown in Section 3.6.4.2, “USBn_VDD_1P8_DECAP capacitor options.” 38. A divider network is required on this signal. See Section 3.6.4.1, “USB divider network.” 39. For systems which boot from local bus (GPCM)-controlled NOR flash or (FCM)-controlled NAND flash, a pullup on LGPL4 is required. 40. Functionally, this pin is an input, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin is therefore described as an I/O for boundary scan. 41. If migration from a P4 device, this pin is allowed to be powered by AVDD_CC2. If not migrating, do not connect. 42. The VDD_VID_CA_CB pins are inputs at POR. If a voltage regulator is connected directly to the VID_VDD_CA_CB pins, customers need to put weak pull-ups or pull-downs on their board so that their voltage regulator drives a guaranteed-to-work voltage with the cores configured to run at a safe frequency for that voltage. This is needed so that a working voltage can be applied until the operating voltage is determined (for example, so that PLLs can begin to lock, and so on, during this time frame or while the voltage is ramping). The safe boot voltage for the chip is 1.1 V. Note that the P5021 does not require VID to meet it's performance and power envelope. All power rails should be fixed at the operating values specified in Table 3. “Recommended operating conditions.” 43. VDD_LL should be connected directly to VDD_PL. 44. Normally tied to GND. See the applicable migration application note if moving from P3041 (AN4395) or P5020/P5010 (AN4400). 2 Electrical characteristics This section provides the AC and DC electrical specifications for the chip. The chip is currently targeted to these specifications, some of which are independent of the I/O cell but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC electrical characteristics This section describes the ratings, conditions, and other electrical characteristics. 2.1.1 Absolute maximum ratings This table provides the absolute maximum ratings. Table 2. Absolute maximum operating conditions1 Parameter Symbol Maximum value Unit Notes Core group A (core 0,1) supply voltage VDD_CA –0.3 to 1.32 V 9,11 Platform supply voltage VDD_PL –0.3 to 1.1 V 9,10, 11 AVDD –0.3 to 1.1 V — AVDD_SRDS –0.3 to 1.1 V — PLL supply voltage (core, platform, DDR) PLL supply voltage (SerDes, filtered from SVDD) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 52 Freescale Semiconductor Electrical characteristics Table 2. Absolute maximum operating conditions1 (continued) Parameter Symbol Maximum value Unit Notes POVDD –0.3 to 1.65 V 1 DMA, MPIC, GPIO, system control and power DUART, I management, clocking, debug, I/O voltage select, and JTAG I/O voltage OVDD –0.3 to 3.63 V — eSPI, eSHDC CVDD –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 V — DDR3 and DDR3L DRAM I/O voltage GVDD –0.3 to 1.65 V — Enhanced local bus I/O voltage BVDD –0.3 to 3.63 –0.3 to 2.75 –0.3 to 1.98 V — Core power supply for SerDes transceivers SVDD –0.3 to 1.1 V — Pad power supply for SerDes transceivers XVDD –0.3 to 1.98 –0.3 to 1.65 V — Ethernet I/O, Ethernet management interface 1 (EMI1), 1588, GPIO LVDD –0.3 to 3.63 –0.3 to 2.75 V 3 — –0.3 to 1.32 V 8 USB PHY Transceiver supply voltage USB_VDD_3P3 –0.3 to 3.63 V — USB PHY PLL supply voltage USB_VDD_1P0 –0.3 to 1.1 V — VDD_LP –0.3 to 1.1 V — Fuse programming override supply 2C, Ethernet management interface 2 (EMI2) Low-power security monitor supply P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 53 Electrical characteristics Table 2. Absolute maximum operating conditions1 (continued) Parameter Input voltage7 Symbol Maximum value Unit Notes MVIN –0.3 to (GVDD + 0.3) V 2, 7 MVREF –0.3 to (GVDD/2+ 0.3) V 2, 7 Ethernet signals (except EMI2) LVIN –0.3 to (LVDD + 0.3) V 3, 7 eSPI, eSHDC CVIN –0.3 to (CVDD + 0.3) V 4, 7 Enhanced local bus signals BVIN –0.3 to (BVDD + 0.3) V 5, 7 DUART, I C, DMA, MPIC, GPIO, system control and power management, clocking, debug, I/O voltage select, and JTAG I/O voltage OVIN –0.3 to (OVDD + 0.3) V 6, 7 SerDes signals XVIN –0.4 to (XVDD + 0.3) V 7 USB_VIN_3P3 –0.3 to (USB_VDD_3P3 + 0.3) V 7 — –0.3 to (1.2 + 0.3) V 7 Tstg –55 to 150 °C — DDR3 and DDR3L DRAM signals DDR3 and DDR3L DRAM reference 2 USB PHY transceiver signals Ethernet management interface 2 (EMI2) signals Storage junction temperature range Notes: 1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only; functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: CVIN must not exceed CVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. Caution: BVIN must not exceed BVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. (C,X,B,G,L,O)VIN may overshoot (for VIH) or undershoot (for VIL) to the voltages and maximum duration shown in Figure 7. 8. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels. LVDD must be powered to use this interface. 9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin. 10. Implementation may choose either VDD_PL pin for feedback loop. If the platform and core groups are supplied by a single regulator, it is recommended that VDD_CA be used. 11. VDD_PL voltage must not exceed VDD_CA. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 54 Freescale Semiconductor Electrical characteristics 2.1.2 Recommended operating conditions This table provides the recommended operating conditions for this device. Note that proper device operation outside these conditions is not guaranteed. Table 3. Recommended operating conditions Parameter Symbol Recommended value Unit Notes Core group A (core 0,1) supply voltage VDD_CA 1.1 ± 50mV (core frequency ≤ 2000 MHz) 1.2V ± 30mV (core frequency > 2000 MHz) V 1,6 Platform supply voltage VDD_PL 1.0 ± 50mV V 1,6 AVDD 1.0 ± 50mV V — AVDD_SRDS 1.0 ± 50mV V — POVDD 1.5 ± 75mV V 2 DUART, I2C, DMA, MPIC, GPIO, system control and power management, clocking, debug, I/O voltage select, and JTAG I/O voltage OVDD 3.3 ± 165mV V — eSPI, eSDHC CVDD 3.3 ± 165mV 2.5 ± 125mV 1.8 ± 90mV V — GVDD 1.5 ± 75mV V — PLL supply voltage (core, platform, DDR, FMan) PLL supply voltage (SerDes) Fuse programming override supply DDR DRAM I/O voltage DDR3 DDR3L 1.35 ± 67mV Enhanced local bus I/O voltage BVDD 3.3 ± 165mV 2.5 ± 125mV 1.8 ± 90mV V — Main power supply for internal circuitry of SerDes and pad power supply for SerDes receiver SVDD 1.0 + 50mV 1.0 – 30mV V — Pad power supply for SerDes transmitter XVDD 1.8 ± 90mV 1.5 ± 75mV V — Ethernet I/O, Ethernet Management interface 1 (EMI1), 1588, GPIO LVDD 3.3 ± 165mV 2.5 ± 125mV V 3 USB PHY transceiver supply voltage USB_VDD_3P3 3.3 ± 165mV V — USB PHY PLL supply voltage USB_VDD_1P0 1.0 ± 50mV V — VDD_LP 1.0 ± 50mV V — Low-power security monitor supply P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 55 Electrical characteristics Table 3. Recommended operating conditions (continued) Symbol Recommended value Unit Notes DDR3 and DDR3L DRAM signals MVIN GND to GVDD V 7 DDR3 and DDR3L DRAM reference MVREF GVDD/2 ± 1% V 7 Ethernet signals (except EMI2) LVIN GND to LVDD V 7 eSPI, eSHDC CVIN GND to CVDD V 7 Enhanced local bus signals BVIN GND to BVDD V 7 DUART, I2C, DMA, MPIC, GPIO, system control and power management, clocking, debug, I/O voltage select, and JTAG I/O voltage OVIN GND to OVDD V 7 SerDes signals SVIN GND to SVDD V 7 USB_VIN_3P3 GND to USB_VDD_3P3 V 7 Ethernet Management interface 2 (EMI2) signals — GND to 1.2V V 4, 7 Normal Operation TA, TJ TA = 0 (min) to TJ = 105 (max) (90 (max) core frequency > 2000 MHz) °C — Extended Temperature TA, TJ TA = -40 (min) to TJ = 105 (max) °C — Secure Boot Fuse Programming TA, TJ TA = 0 (min) to TJ = 70 (max) °C 2 Parameter Input voltage USB PHY Transceiver signals Operating Temperature range Notes: 1. VDD_PL voltage must not exceed VDD_CA. 2. POVDD must be supplied 1.5 V and the chip must operate in the specified fuse programming temperature range only during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the power sequencing constraints shown in Section 2.2, “Power-up sequencing.” 3. Selecting RGMII limits LVDD to 2.5V. 4. Ethernet Management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal voltage levels. LVDD must be powered to use this interface.6. Supply voltage specified at the voltage sense pin. Voltage input pins must be regulated to provide specified voltage at the sense pin. 7. All input signals must increase/decrease monotonically throughout the entire rise/fall duration. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 56 Freescale Semiconductor Electrical characteristics This figure shows the undershoot and overshoot voltages at the interfaces of the chip. Nominal C/X/B/G/L/OVDD + 20% C/X/B/G/L/OVDD + 5% C/X/B/G/L/OVDD VIH GND GND – 0.3V VIL GND – 0.7 V Not to Exceed 10% of tCLOCK Note: tCLOCK refers to the clock period associated with the respective interface: For I2C, tCLOCK refers to SYSCLK. For DDR GVDD, tCLOCK refers to Dn_MCK. For eSPI CVDD, tCLOCK refers to SPI_CLK. For eLBC BVDD, tCLOCK refers to LCLK. For SerDes XVDD, tCLOCK refers to SD_REF_CLK. For dTSEC LVDD, tCLOCK refers to EC_GTX_CLK125. For JTAG OVDD, tCLOCK refers to TCK. Figure 7. Overshoot/Undershoot voltage for BVDD/GVDD/LVDD/OVDD The core and platform voltages must always be provided at nominal 1.0 V or 1.2 V. See Table 3 for the actual recommended core voltage conditions. Voltage to the processor interface I/Os is provided through separate sets of supply pins and must be provided at the voltages shown in Table 3. The input voltage threshold scales with respect to the associated I/O supply voltage. CVDD, BVDD, OVDD, and LVDD-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied MVREF signal (nominally set to GVDD/2) as is appropriate for the SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 57 Electrical characteristics 2.1.3 Output driver characteristics This table provides information about the characteristics of the output driver strengths. The values are preliminary estimates. Table 4. Output drive capability Output impedance (Ω) (Nominal) supply voltage 45 45 45 BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V — DDR3 signal 20 (full-strength mode) 40 (half-strength mode) GVDD = 1.5 V 1 DDR3L signal 20 (full-strength mode) 40 (half-strength mode) GVDD = 1.35 V 1 eTSEC/10/100 signals 45 45 LVDD = 3.3 V LVDD = 2.5 V — DUART, system control, JTAG 45 OVDD = 3.3 V — 45 OVDD = 3.3 V — 45 45 45 CVDD = 3.3 V CVDD = 2.5 V CVDD = 1.8 V — Driver type Local bus interface utilities signals I 2C eSPI and SD/MMC Notes Note: 1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GVDD (min). 2.2 Power-up sequencing The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up: 1. 2. 3. 4. 5. Bring up OVDD, LVDD, BVDD, CVDD, and USB_VDD_3P3. Drive POVDD = GND. — PORESET input must be driven asserted and held during this step — IO_VSEL inputs must be driven during this step and held stable during normal operation. — USB_VDD_3P3 rise time (10% to 90%) has a minimum of 350 μs. Bring up VDD_PL, VDD_CA, SVDD, AVDD (cores, platform, DDR, SerDes) and USB_VDD_1P0. VDD_PL and USB_VDD_1P0 must be ramped up simultaneously. Bring up GVDD and XVDD. Negate PORESET input as long as the required assertion/hold time has been met per Table 15. For secure boot fuse programming: After negation of PORESET, drive POVDD = 1.5 V after a required minimum delay per Table 5. After fuse programming is completed, it is required to return POVDD = GND before the system is power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in Table 5. See Section 5, “Security fuse processor,” for additional details. WARNING Only two secure boot fuse programming events are permitted per lifetime of a device. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 58 Freescale Semiconductor Electrical characteristics WARNING Only 100,000 POR cycles are permitted per lifetime of a device. WARNING While VDD is ramping, current may be supplied from VDD through the P5021 to GVDD. Nevertheless, GVDD from an external supply should follow the sequencing described above. All supplies must be at their stable values within 75 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. This figure provides the POVDD timing diagram. Fuse programming 1 POVDD 10% POVDD 10% POVDD 90% VDD_PL tPOVDD_VDD VDD_PL PORESET tPOVDD_PROG 90% OVDD 90% OVDD tPOVDD_RST tPOVDD_DELAY NOTE: POVDD must be stable at 1.5 V prior to initiating fuse programming. Figure 8. POVDD timing diagram This table provides information on the power-down and power-up sequence parameters for POVDD. Table 5. POVDD timing 5 Driver type Min Max Unit Notes tPOVDD_DELAY 100 — SYSCLKs 1 tPOVDD_PROG 0 — μs 2 tPOVDD_VDD 0 — μs 3 tPOVDD_RST 0 — μs 4 Notes: 1. Delay required from the negation of PORESET to driving POVDD ramp up. Delay measured from PORESET negation at 90% OVDD to 10% POVDD ramp up. 2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD is stable at 1.5 V. No activity other than that required for secure boot fuse programming is permitted while POVDD driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. After fuse programming is completed, it is required to return POVDD = GND. 3. Delay required from POVDD ramp down complete to VDD_PL ramp down start. POVDD must be grounded to minimum 10% POVDD before VDD_PL is at 90% VDD. 4. Delay required from POVDD ramp down complete to PORESET assertion. POVDD must be grounded to minimum 10% POVDD before PORESET assertion reaches 90% OVDD. 5. Only two secure boot fuse programming events are permitted per lifetime of a device. To guarantee MCKE low during power up, the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power up, the sequencing for GVDD is not required. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 59 Electrical characteristics WARNING Incorrect voltage select settings can lead to irreversible device damage. See Section 3.2, “Supply power default setting.” NOTE From a system standpoint, if any of the I/O power supplies ramp prior to the VDD_CA, or VDD_PL supplies, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. 2.3 Power-down requirements The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be started. If performing secure boot fuse programming per Section 2.2, “Power-up sequencing,” it is required that POVDD = GND before the system is power cycled (PORESET assertion) or powered down (VDD_PL ramp down) per the required timing specified in Table 5. VDD_PL and USB_VDD_1P0 must be ramped down simultaneously. USB_VDD_1P8_DECAP should starts ramping down only after USB_VDD_3P3 is below 1.65 V. 2.4 Power characteristics This table shows the power dissipations of the VDD_CA, SVDD, and VDD_PL supply for various operating platform clock frequencies versus the core and DDR clock frequencies for the chip. Table 6. Power dissipation Power Mode Core Plat freq freq (MHz) (MHz) DDR VDD_PL, VDD_CA data FM freq SVDD (V) rate (MHz) (V) (MHz) Typical Thermal Core Junction and plat- VDD_PL VDD_CA power power temp form (W) (W) (°C) power1 (W) 65 2200 800 1600 600 1.0 1.2 SVDD power (W) Note 23 — — — — 33 — — — — 34 17 15 15 2.2 21 — — — — 30 — — — — 31 16 13 13 2.2 90 Maximum Typical Thermal 65 2000 700 1333 600 1.0 1.1 105 Maximum P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 60 Freescale Semiconductor Electrical characteristics Table 6. Power dissipation (continued) Power Mode Core Plat freq freq (MHz) (MHz) Core Junction and plat- VDD_PL VDD_CA power power temp form (W) (W) (°C) power1 (W) DDR VDD_PL, VDD_CA data FM freq SVDD (V) rate (MHz) (V) (MHz) Typical Thermal 65 1800 600 1200 450 1.0 1.1 SVDD power (W) Note 20 — — — — 29 — — — — 30 15 13 13 2.2 105 Maximum Notes: 1. Combined power of VDD_PL, VDD_CA, SVDD with both DDR controllers and all SerDes banks active. Does not include I/O power. 2. Typical power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform with 90% activity factor. 3. Typical power based on nominal processed device. 4. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and executing DMA on the platform at 100% activity factor. 5. Thermal power assumes Dhrystone running with activity factor of 80% (on all cores) and executing DMA on the platform at 90% activity factor. 6. Maximum power provided for power supply design sizing. 7. Thermal and maximum power are based on worst case processed device. This table shows the estimated power dissipation on the AVDD and AVDD_SRDS supplies for the chip’s PLLs, at allowable voltage levels. Table 7. AVDD power dissipation AVDDs Typical Maximum Unit Notes AVDD_DDR 5 15 mW 1 AVDD_CC1 5 15 mW AVDD_CC2 5 15 mW AVDD_PLAT 5 15 mW AVDD_FM 5 15 mW AVDD_SRDS1 — 36 mW AVDD_SRDS2 — 36 mW AVDD_SRDS3 — 36 mW AVDD_SRDS4 — 36 mW USB_VDD_1P0 — 10 mW VDD_LP — 5 mW 2 3 Note: 1. VDD_CA = 1.2 V, TA = 80°C, TJ = 105°C 2. VDD_PL, SVDD = 1.0 V, TA = 80°C, TJ = 105°C 3. USB_VDD_1P0, VDD_LP = 1.0 V, TA = 80°C, TJ = 105°C P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 61 Electrical characteristics This table shows the estimated power dissipation on the POVDD supply for the chip, at allowable voltage levels. Table 8. POVDD power dissipation Supply Maximum Unit Notes POVDD 450 mW 1 Note: 1. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature range per Table 3. This table shows the estimated power dissipation on the VDD_LP supply for the chip, at allowable voltage levels. Table 9. VDD_LP Power Dissipation Supply Maximum Unit Note VDD_LP (P5021 on, 105C) 1.5 mW 1 VDD_LP (P5021 off, 70C) 195 uW 2 VDD_LP (P5021 off, 40C) 132 uW 2 Note: 1. VDD_LP = 1.0 V, TJ = 105°C. 2. When P5021 is off, VDD_LP may be supplied by battery power to the Zeroizable Master Key and other Trust Architecture state. Board should implement a PMIC which switches VDD_LP to battery when P5021 is powered down. See P5040 Reference Manual Trust Architecture chapter for more information. 2.5 Thermal This table shows the thermal characteristics for the chip. Table 10. Package thermal characteristics 6 Rating Board Symbol Value Junction to ambient, natural convection Single-layer board (1s) RΘJA 14 Junction to ambient, natural convection Four-layer board (2s2p) RΘJA 10 Junction to ambient (at 200 ft./min.) Single-layer board (1s) RΘJMA 9 Junction to ambient (at 200 ft./min.) Four-layer board (2s2p) RΘJMA 7 Unit °C/W °C/W °C/W °C/W Notes 1, 2 1, 2 1, 2 1, 2 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 62 Freescale Semiconductor Electrical characteristics Table 10. Package thermal characteristics (continued)6 Rating Board Symbol Value Junction to board — RΘJB 3 Junction to case top — RΘJCtop 0.44 Junction to lid top — RΘJClid 0.17 Unit °C/W °C/W °C/W Notes 3 4 5 Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 3. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. 4. Junction-to-Lid-Top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold plate, the lid top temperature is used here for the reference case temperature. The reported value does not include the thermal resistance of the interface layer between the package and cold plate. 5. Junction-to-lid-top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the thermal resistance of the interface layer between the package and cold plate. 6. Reference Section 3.8, “Thermal management information,” for additional details. 2.6 Input clocks This section discusses the system clock timing specifications for DC and AC power, spread spectrum sources, real time clock timing, and dTSEC gigabit Ethernet reference clocks AC timing. 2.6.1 System clock (SYSCLK) timing specifications This table provides the system clock (SYSCLK) DC specifications. Table 11. SYSCLK DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 2.0 — — V 1 Input low voltage VIL — — 0.8 V 1 Input current (OVIN= 0 V or OVIN = OVDD) IIN — — ±40 μA 2 Notes: 1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3. 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 63 Electrical characteristics This table provides the system clock (SYSCLK) AC timing specifications. Table 12. SYSCLK AC timing specifications For recommended operating conditions, see Table 3. Parameter/Condition Symbol Min Typ Max Unit Notes SYSCLK frequency fSYSCLK 100 — 166 MHz 1, 2 SYSCLK cycle time tSYSCLK 6 — 10 ns 1, 2 SYSCLK duty cycle tKHK / tSYSCLK 40 — 60 % 2 SYSCLK slew rate — 1 — 4 V/ns 3 SYSCLK peak period jitter — — — 150 ps — SYSCLK jitter phase noise — — — 500 KHz 4 ΔVAC 1.9 — — V — AC Input Swing Limits at 3.3 V OVDD Notes: 1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency, do not exceed their respective maximum or minimum operating frequencies. 2. Measured at the rising edge and/or the falling edge at OVDD/2. 3. Slew rate as measured from ±0.3 ΔVAC at center of peak to peak voltage at clock input. 4. Phase noise is calculated as FFT of TIE jitter. 2.6.2 Spread-spectrum sources recommendations Spread-spectrum clock sources is an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter specification given in Table 13 considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns; the chip is compatible with spread spectrum sources if the recommendations listed in Table 13 are observed. Table 13. Spread-spectrum clock source recommendations For recommended operating conditions, see Table 3. Parameter Min Max Unit Notes Frequency modulation — 60 kHz — Frequency spread — 1.0 % 1, 2 Notes: 1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and maximum specifications given in Table 12. 2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device. CAUTION The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated core/platform/DDR frequency should avoid violating the stated limits by using down-spreading only. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 64 Freescale Semiconductor Electrical characteristics 2.6.3 Real time clock timing The real time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum pulse width of the RTC signal should be greater than 16× the period of the platform clock with a 50% duty cycle. There is no minimum RTC frequency; RTC may be grounded if not needed. 2.6.4 dTSEC gigabit Ethernet reference clock timing This table provides the dTSEC gigabit Ethernet reference clocks AC timing specifications. Table 14. EC_GTX_CLK125 AC timing specifications Parameter/Condition Symbol Min Typical Max Unit Notes EC_GTX_CLK125 frequency tG125 — 125 — MHz — EC_GTX_CLK125 cycle time tG125 — 8 — ns — EC_GTX_CLK125 rise and fall time LVDD = 2.5 V LVDD = 3.3 V tG125R/tG125F — — ns 1 EC_GTX_CLK125 duty cycle 1000Base-T for RGMII tG125H/tG125 % 2 ps 2 EC_GTX_CLK125 jitter 0.75 1.0 — 47 — 53 — — ± 150 Note: 1. Rise and fall times for EC_GTX_CLK125 are measured from 20% to 80% (rise time) and 80% to 20% (fall time) of LVDD. 2. EC_GTX_CLK125 is used to generate the GTX clock for the dTSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the dTSEC GTX_CLK. See Section 2.12.2.3, “RGMII AC timing specifications,” for duty cycle for 10Base-T and 100Base-T reference clock. 2.6.5 Other input clocks A description of the overall clocking of this device is available in the applicable chip reference manual in the form of a clock subsystem block diagram. For information on the input clock requirements of functional blocks sourced external of the device, such as SerDes, Ethernet Management, eSDHC, Local bus, see the specific interface section. 2.7 RESET initialization This section describes the AC electrical specifications for the RESET initialization timing requirements. This table provides the RESET initialization AC timing specifications. Table 15. RESET initialization timing specifications Min Max Unit1 Notes Required assertion time of PORESET 1 — ms 3 Required input assertion time of HRESET 32 — SYSCLKs 1, 2 Input setup time for POR configurations with respect to negation of PORESET 4 — SYSCLKs 1 Parameter P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 65 Electrical characteristics Table 15. RESET initialization timing specifications (continued) Min Max Unit1 Notes Input hold time for all POR configurations with respect to negation of PORESET 2 — SYSCLKs 1 Maximum valid-to-high impedance time for actively driven POR configurations with respect to negation of PORESET — 5 SYSCLKs 1 Parameter Notes: 1. SYSCLK is the primary clock input for the chip. 2. The device asserts HRESET as an output when PORESET is asserted to initiate the power-on reset process. The device releases HRESET sometime after PORESET is negated. The exact sequencing of HRESET negation is documented in Section 4.4.1 “Power-On Reset Sequence,” of the applicable chip reference manual. 3. PORESET must be driven asserted before the core and platform power supplies are powered up , see Section 2.2, “Power-up sequencing.” This table provides the PLL lock times. Table 16. PLL lock times Parameter PLL lock times 2.8 Min Max Unit Notes — 100 μs — Power-on ramp rate This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum Power-On Ramp Rate is required to avoid falsely triggering the ESD circuitry. This table provides the power supply ramp rate specifications. Table 17. Power supply ramp rate Parameter Required ramp rate for all voltage supplies (including OVDD/CVDD/ GVDD/BVDD/SVDD/XVDD/LVDD all VDD supplies, MVREF and all AVDD supplies.) Min Max Unit Notes — 36000 V/s 1, 2 Notes: 1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry. 2. Over full recommended operating temperature range (see Table 3). 2.9 DDR3 and DDR3L SDRAM controller This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM. NOTE When operating at DDR data rates of 1600 MT/s only one dual-ranked module per memory controller is supported. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 66 Freescale Semiconductor Electrical characteristics 2.9.1 DDR3 and DDR3L SDRAM interface DC electrical characteristics This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM. Table 18. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)1 For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Note MVREF 0.49 × GVDD 0.51 × GVDD V 2, 3, 4 Input high voltage VIH MVREF + 0.100 GVDD V 5 Input low voltage VIL GND MVREF – 0.100 V 5 I/O leakage current IOZ –50 50 μA 6 I/O reference voltage Notes: 1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source. 2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed the MVREF DC level by more than ±1% of the DC value (that is, ±15 mV). 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC level of MVREF. 4. The voltage regulator for MVREF must meet the specifications stated in Table 21. 5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models. 6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD. This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L SDRAM. Table 19. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1 For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Note MVREF 0.49 × GVDD 0.51 × GVDD V 2, 3, 4 Input high voltage VIH MVREF + 0.090 GVDD V 5 Input low voltage VIL GND MVREF – 0.090 V 5 I/O reference voltage P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 67 Electrical characteristics Table 19. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1 (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Note I/O leakage current IOZ –50 50 μA 6 Output high current (VOUT = 0.641 V) IOH — –23.3 mA 7, 8 Output low current (VOUT = 0.641 V) IOL 23.3 — mA 7, 8 Notes: 1. GVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source. 2. MVREF is expected to be equal to 0.5 × GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed the MVREF DC level by more than ±1% of the DC value (that is, ±13.5 mV). 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to MVREF with a min value of MVREF – 0.04 and a max value of MVREF + 0.04. VTT should track variations in the DC level of MVREF. 4. The voltage regulator for MVREF must meet the specifications stated in Table 21. 5. Input capacitance load for DQ, DQS, and DQS are available in the IBIS models. 6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD. 7. Refer to the IBIS model for the complete output IV curve characteristics. 8. IOH and IOL are measured at GVDD = 1.283 V This table provides the DDR controller interface capacitance for DDR3 and DDR3L. Table 20. DDR3 and DDR3L SDRAM Capacitance For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input/output capacitance: DQ, DQS, DQS CIO 6 8 pF 1, 2 Delta input/output capacitance: DQ, DQS, DQS CDIO — 0.5 pF 1, 2 Notes: 1. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25 °C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.150 V. 2. This parameter is sampled. GVDD = 1.35 V – 0.067 V ÷ + 0.100 V (for DDR3L), f = 1 MHz, TA = 25 °C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.167 V. This table provides the current draw characteristics for MVREF. Table 21. Current Draw Characteristics for MVREF For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Current draw for DDR3 SDRAM for MVREF MVREF — 1250 μA — Current draw for DDR3L SDRAM for MVREF MVREF — 1250 μA — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 68 Freescale Semiconductor Electrical characteristics 2.9.2 DDR3 and DDR3L SDRAM interface AC timing specifications This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports DDR3 and DDR3L memories. Note that the required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM. 2.9.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM. Table 22. DDR3 SDRAM interface input AC timing specifications For recommended operating conditions, see Table 3. Parameter AC input low voltage > 1200 MT/s data rate Symbol Min Max Unit Notes VILAC — MVREF – 0.150 V — V — ≤ 1200 MT/s data rate AC input high voltage > 1200 MT/s data rate MVREF – 0.175 VIHAC ≤ 1200 MT/s data rate MVREF + 0.150 — MVREF + 0.175 This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3L SDRAM. Table 23. DDR3L SDRAM interface input AC timing specifications For recommended operating conditions, see Table 3. Parameter AC input low voltage > 1067 MT/s data rate Symbol Min Max Unit Notes VILAC — MVREF – 0.135 V — V — ≤ 1067 MT/sdata rate AC input high voltage > 1067 MT/s data rate MVREF – 0.160 VIHAC ≤ 1067 MT/s data rate MVREF + 0.135 — MVREF + 0.160 This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM. Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Controller Skew for MDQS—MDQ/MECC Min Max tCISKEW 1600 MT/s data rate –112 112 1333 MT/s data rate –125 125 1200 MT/s data rate –147.5 147.5 1066 MT/s data rate –170 170 800 MT/s data rate –200 200 Unit Notes ps 1 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 69 Electrical characteristics Table 24. DDR3 and DDR3L SDRAM interface input AC timing specifications (continued) For recommended operating conditions, see Table 3. Parameter Symbol Tolerated Skew for MDQS—MDQ/MECC Min Max tDISKEW 1600 MT/s data rate –200 200 1333 MT/s data rate –250 250 1200 MT/s data rate –275 275 1066 MT/s data rate –300 300 800 MT/s data rate –425 425 Unit Notes ps 2 Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram. MCK[n] MCK[n] tMCK MDQS[n] tDISKEW MDQ[x] D0 D1 tDISKEW tDISKEW Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 70 Freescale Semiconductor Electrical characteristics 2.9.2.2 DDR3 and DDDR3L SDRAM interface output AC timing specifications This table contains the output AC timing targets for the DDR3 SDRAM interface. Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications For recommended operating conditions, see Table 3. Parameter MCK[n] cycle time ADDR/CMD output setup with respect to MCK Symbol1 Min Max Unit Notes tMCK 1.25 2.5 ns 2 ns 3 ns 3 ns 3 ns 3 ns 4 tDDKHAS 1600 MT/s data rate 0.495 — 1333 MT/s data rate 0.606 — 1200 MT/s data rate 0.675 — 1066 MT/s data rate 0.744 — 800 MT/s data rate 0.917 — ADDR/CMD output hold with respect to MCK tDDKHAX 1600 MT/s data rate 0.495 — 1333 MT/s data rate 0.606 — 1200 MT/s data rate 0.675 — 1066 MT/s data rate 0.744 — 800 MT/s data rate 0.917 — MCS[n] output setup with respect to MCK tDDKHCS 1600 MT/s data rate 0.495 — 1333 MT/s data rate 0.606 — 1200 MT/s data rate 0.675 — 1066 MT/s data rate 0.744 — 800 MT/s data rate 0.917 — MCS[n] output hold with respect to MCK tDDKHCX 1600 MT/sdata rate 0.495 — 1333 MT/s data rate 0.606 — 1200 MT/s data rate 0.675 — 1066 MT/sdata rate 0.744 — 800 MT/s data rate 0.917 — MCK to MDQS Skew tDDKHMH > 1066 MT/s data rate –0.245 0.245 800 MT/s data rate –0.375 0.375 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 71 Electrical characteristics Table 25. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued) For recommended operating conditions, see Table 3. Parameter Symbol1 MDQ/MECC/MDM output setup with respect to MDQS tDDKHDS, tDDKLDS Min Max 1600 MT/s data rate 200 — 1333 MT/s data rate 250 — 1200 MT/s data rate 275 — 1066 MT/s data rate 300 — 800 MT/s data rate 375 — MDQ/MECC/MDM output hold with respect to MDQS tDDKHDX, tDDKLDX 1600 MT/s data rate 200 — 1333 MT/s data rate 250 — 1200 MT/s data rate 275 — 1066 MT/s data rate 300 — 800 MT/s data rate 375 — Unit Notes ps 5 ps 5 MDQS preamble tDDKHMP 0.9 × tMCK — ns — MDQS post-amble tDDKHME 0.4 × tMCK 0.6 × tMCK ns — Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK and MDQS/MDQS referenced measurements are made from the crossing of the two signals. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the applicable chip reference manual for a description and explanation of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. NOTE For the ADDR/CMD setup and hold specifications in Table 25, it is assumed that the clock control register is set to adjust the memory clocks by ½ applied cycle. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 72 Freescale Semiconductor Electrical characteristics This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] tMCK tDDKHMH(max) MDQS[n] tDDKHMH(min) MDQS[n] Figure 10. tDDKHMH timing diagram This figure shows the DDR3 and DDR3L SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS, tDDKHCS tDDKHAX, tDDKHCX ADDR/CMD Write A0 NOOP tDDKHMP tDDKHMH MDQS[n] tDDKHME tDDKHDS tDDKLDS MDQ[x] D0 D1 tDDKLDX tDDKHDX Figure 11. DDR3 and DDR3L output timing diagram P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 73 Electrical characteristics This figure provides the AC test load for the DDR3 and DDR3L controller bus. Z0 = 50 Ω Output RL = 50 Ω GVDD/2 Figure 12. DDR3 and DDR3L controller bus AC test load 2.10 eSPI This section describes the DC and AC electrical specifications for the eSPI interface. 2.10.1 eSPI DC electrical characteristics This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 3.3 V. Table 26. eSPI DC electrical characteristics (CVDD = 3.3 V)1,2 For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Input current (VIN = 0 V or VIN = CVDD) IIN — ±40 μA 2 Output high voltage (CVDD = min, IOH = –2 mA) VOH 2.4 — V — Output low voltage (CVDD = min, IOL = 2 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3. 2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 2.5 V. Table 27. eSPI DC electrical characteristics (CVDD = 2.5 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.7 — V 1 Input low voltage VIL — 0.7 V 1 Input current (VIN = 0 V or VIN = CVDD) IIN — ±40 μA 2 Output high voltage (CVDD = min, IOH = –1 mA) VOH 2.0 — V — Output low voltage (CVDD = min, IOL = 1 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3. 2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 74 Freescale Semiconductor Electrical characteristics This table provides the DC electrical characteristics for the eSPI interface operating at CVDD = 1.8 V. Table 28. eSPI DC electrical characteristics (CVDD = 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.25 — V 1 Input low voltage VIL — 0.6 V 1 Input current (VIN = 0 V or VIN = CVDD) IIN — ±40 μA 2 Output high voltage (CVDD = min, IOH = –0.5 mA) VOH 1.35 — V — Output low voltage (CVDD = min, IOL = 0.5 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3. 2. The symbol VIN, in this case, represents the CVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” 2.10.2 eSPI AC timing specifications This table provides the eSPI input and output AC timing specifications. Table 29. eSPI AC timing specifications For recommended operating conditions, see Table 3. Symbol1 Min Max SPI_MOSI output—Master data (internal clock) hold time tNIKHOX 2.36 + (tPLATFORM_CLK * SP MODE[HO_ADJ]) — — SPI_MOSI output—Master data (internal clock) delay tNIKHOV — SPI_CS outputs—Master data (internal clock) hold time tNIKHOX2 0 — ns 2 SPI_CS outputs—Master data (internal clock) delay tNIKHOV2 — 6.0 ns 2 eSPI inputs—Master data (internal clock) input setup time tNIIVKH 5 — ns — eSPI inputs—Master data (internal clock) input hold time tNIIXKH 0 — ns — Parameter Unit Note ns 2, 3 ns 5.24 + (tPLATFORM_CLK * SPMODE[HO_ADJ]) 2, 3 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V). 2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 3. See the applicable chip reference manual for details on the SPMODE register. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 75 Electrical characteristics This figure provides the AC test load for the eSPI. Z0 = 50 Ω Output RL = 50 Ω CVDD/2 Figure 13. eSPI AC test load This figure represents the AC timing from Table 29 in master mode (internal clock). Note that although timing specifications generally refer to the rising edge of the clock, this figure also applies when the falling edge is the active edge. Also, note that the clock edge is selectable on eSPI. SPICLK (output) tNIIVKH Input Signals: SPIMISO1 tNIIXKH tNIKHOX tNIKHOV Output Signals: SPIMOSI1 tNIKHOV2 tNIKHOX2 Output Signals: SPI_CS[0:3]1 Figure 14. eSPI AC timing in master mode (Internal Clock) diagram 2.11 DUART This section describes the DC and AC electrical specifications for the DUART interface. 2.11.1 DUART DC electrical characteristics This table provides the DC electrical characteristics for the DUART interface. Table 30. DUART DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2 — V 1 Input low voltage VIL — 0.8 V 1 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 76 Freescale Semiconductor Electrical characteristics Table 30. DUART DC electrical characteristics (OVDD = 3.3 V) (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes IIN — ±40 μA 2 Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V — Output low voltage (OVDD = min, IOL = 2 mA) VOL — 0.4 V — Input current (OVIN = 0 V or OVIN = OVDD) Notes: 1. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3. 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” 2.11.2 DUART AC electrical specifications This table provides the AC timing parameters for the DUART interface. Table 31. DUART AC timing specifications For recommended operating conditions, see Table 3. Parameter Value Unit Notes Minimum baud rate fPLAT/(2*1,048,576) baud 1 Maximum baud rate fPLAT/(2*16) baud 1,2 16 — 3 Oversample rate Notes: 1. fPLAT refers to the internal platform clock. 2. The actual attainable baud rate is limited by the latency of interrupt processing. 3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. 2.12 Ethernet: data path three-speed Ethernet (dTSEC), management interface, IEEE Std 1588 This section provides the AC and DC electrical characteristics for the data path three-speed Ethernet controller, the Ethernet management interface, and the IEEE Std 1588 interface. 2.12.1 SGMII timing specifications See Section 2.20.8, “SGMII interface.” 2.12.2 MII and RGMII timing specifications This section discusses the electrical characteristics for the MII and RGMII interfaces. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 77 Electrical characteristics 2.12.2.1 MII and RGMII DC electrical characteristics This table shows the MII DC electrical characteristics when operating at LVDD = 3.3 V supply. Table 32. MII DC electrical characteristics (LVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.90 V — Input high current (VIN = LVDD) IIH — 40 μA 2 Input low current (VIN = GND) IIL –600 — μA 2 Output high voltage (LVDD = min, IOH = –4.0 mA) VOH 2.4 LVDD + 0.3 V — Output low voltage (LVDD = min, IOL = 4.0 mA) VOL GND 0.50 V — Notes: 1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3. 2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3. This table shows the MII and RGMII DC electrical characteristics when operating at LVDD = 2.5 V supply. Table 33. MII and RGMII DC electrical characteristics (LVDD = 2.5 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.7 — V 1 Input low voltage VIL — 0.7 V 1 Input current (LVIN = 0 V or LVIN = LVDD) IIH — ±40 μA 2 Output high voltage (LVDD = min, IOH = –1.0 mA) VOH 2.0 — V — Output low voltage (LVDD = min, IOL = 1.0 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3. 2. The symbol VIN, in this case, represents the LVIN symbols referenced in Table 2 and Table 3. 2.12.2.2 MII AC timing specifications This section describes the MII transmit and receive AC timing specifications. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 78 Freescale Semiconductor Electrical characteristics This table provides the MII transmit AC timing specifications. Table 34. MII transmit AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit TX_CLK clock period 10 Mbps tMTX 399.96 400 400.04 ns TX_CLK clock period 100 Mbps tMTX 39.996 40 40.004 ns tMTXH/tMTX 35 — 65 % tMTKHDX 0 — 25 ns TX_CLK data clock rise (20%–80%) tMTXR 1.0 — 4.0 ns TX_CLK data clock fall (80%–20%) tMTXF 1.0 — 4.0 ns TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay This figure shows the MII transmit AC timing diagram. tMTXR tMTX TX_CLK tMTXH tMTXF TXD[3:0] TX_EN TX_ER tMTKHDX Figure 15. MII transmit AC timing diagram This table provides the MII receive AC timing specifications. Table 35. MII Receive AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit RX_CLK clock period 10 Mbps tMRX 399.96 400 400.04 ns RX_CLK clock period 100 Mbps tMRX 39.996 40 40.004 ns tMRXH/tMRX 35 — 65 % RXD[3:0], RX_DV, RX_ER setup time to RX_CLK tMRDVKH 10.0 — — ns RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 10.0 — — ns RX_CLK clock rise (20%-80%) tMRXR 1.0 — 4.0 ns RX_CLK clock fall time (80%-20%) tMRXF 1.0 — 4.0 ns RX_CLK duty cycle Note: The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 79 Electrical characteristics This figure provides the AC test load for eTSEC. Z0 = 50 Ω Output RL = 50 Ω LVDD/2 Figure 16. eTSEC AC test load This figure shows the MII receive AC timing diagram. tMRXR tMRX RX_CLK tMRXF tMRXH RXD[3:0] RX_DV RX_ER Valid Data tMRDVKH tMRDXKL Figure 17. MII Receive AC timing diagram 2.12.2.3 RGMII AC timing specifications This table presents the RGMII AC timing specifications. Table 36. RGMII AC timing specifications For recommended operating conditions, see Table 3. Symbol1 Min Typ Max Unit Notes Data to clock output skew (at transmitter) tSKRGT_TX –500 0 500 ps 5 Data to clock input skew (at receiver) tSKRGT_RX 1.0 — 2.6 ns 2 tRGT 7.2 8.0 8.8 ns 3 Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 4 Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % — Rise time (20%–80%) tRGTR — — 0.75 ns — Parameter Clock period duration P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 80 Freescale Semiconductor Electrical characteristics Table 36. RGMII AC timing specifications (continued) For recommended operating conditions, see Table 3. Parameter Fall time (20%–80%) Symbol1 Min Typ Max Unit Notes tRGTF — — 0.75 ns — Notes: 1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT). 2. The tSKRGT_RX specification implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their chip. If so, additional PCB delay is probably not needed. 3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speeds transitioned between. 5. The frequency of RX_CLK should not exceed frequency of GTX_CLK125 by more than 300ppm. This figure shows the RGMII AC timing and multiplexing diagrams. Figure 18. RGMII AC timing and multiplexing diagrams 2.12.3 Ethernet management interface This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces. EMI1 is the PHY management interface controlled by the MDIO controller associated with Frame Manager 1 1GMAC-1. EMI2 is the XAUI PHY management interface controlled by the MDIO controller associated with Frame Manager 1 10GMAC-0. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 81 Electrical characteristics 2.12.3.1 Ethernet management interface 1 DC electrical characteristics The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for the Ethernet management interface is provided in this table. Table 37. Ethernet management Interface 1 DC electrical characteristics (LVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Note Input high voltage VIH 2.0 — V 2 Input low voltage VIL — 0.9 V 2 Input high current (LVDD = Max, VIN = 2.1 V) IIH — 40 μA 1 Input low current (LVDD = Max, VIN = 0.5 V) IIL –600 — μA 1 Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.4 — V — Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL — 0.4 V — Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3. 2. The min VIL and max VIH values are based on the respective LVIN values found in Table 3. The Ethernet management interface 1 is defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for the Ethernet management interface 1 is provided in Table 37. Table 38. Ethernet management interface 1 DC electrical characteristics (LVDD = 2.5 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Note Input high voltage VIH 1.7 — V 1 Input low voltage VIL — 0.7 V 1 Input current (LVIN = 0 V or LVIN = LVDD) IIH — ±40 μA 2 Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.4 — V — Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL — 0.4 V — Note: 1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3. 2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” 2.12.3.2 Ethernet management interface 2 DC electrical characteristics Ethernet management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels. LVDD must be powered to use this interface. The DC electrical characteristics for EMI2_MDIO and EMI2_MDC are provided in this section. Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Note Input high voltage VIH 0.84 — V — Input low voltage VIL — 0.36 V — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 82 Freescale Semiconductor Electrical characteristics Table 39. Ethernet management interface 2 DC electrical characteristics (1.2 V) (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Note Output low voltage (IOL = 100 μA) VOL — 0.2 V — Output low current (VOL = 0.2 V) IOL 4 — mA — Input capacitance CIN — 10 pF — 2.12.3.3 Ethernet management interface 1 AC timing specifications This table provides the Ethernet management interface 1 AC timing specifications. Table 40. Ethernet management interface 1 AC timing specifications For recommended operating conditions, see Table 3. Symbol1 Min Typ Max Unit Note MDC frequency fMDC — — 2.5 MHz 2 MDC clock pulse width high tMDCH 160 — — ns — MDC to MDIO delay tMDKHDX (16 × tplb_clk) – 6 — (16 × tplb_clk) + 6 ns 3, 4 MDIO to MDC setup time tMDDVKH 8 — — ns — MDIO to MDC hold time tMDDXKH 0 — — ns — Parameter Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reaching the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the platform clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of the MgmtClk Clock EC_MDC). 3. This parameter is dependent on the frame manager clock frequency. The delay is equal to 16 frame manager clock periods ±6 ns. For example, with a frame manager clock of 333 MHz, the min/max delay is 48 ns ± 6 ns. Similarly, if the frame manager clock is 400 MHz, the min/max delay is 40 ns ± 6 ns. 4. tplb_clk is the frame manager clock period. 2.12.3.4 Ethernet management interface 2 AC electrical characteristics This table provides the Ethernet management interface 2 AC timing specifications. Table 41. Ethernet management interface 2 AC timing specifications For recommended operating conditions, see Table 3. Symbol1 Min Typ Max Unit Note MDC frequency fMDC — — 2.5 MHz 2 MDC clock pulse width high tMDCH 160 — — ns — MDC to MDIO delay tMDKHDX (0.5 ×(1/fMDC)) – 6 — (0.5 ×(1/fMDC)) + 6 ns 3 MDIO to MDC setup time tMDDVKH 8 — — ns — Parameter/Condition P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 83 Electrical characteristics Table 41. Ethernet management interface 2 AC timing specifications (continued) For recommended operating conditions, see Table 3. Parameter/Condition MDIO to MDC hold time Symbol1 Min Typ Max Unit Note tMDDXKH 0 — — ns — Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. 2. This parameter is dependent on the frame manager clock frequency (MIIMCFG [MgmtClk] field determines the clock frequency of the MgmtClk Clock EC_MDC). 3. This parameter is dependent on the management data clock frequency, fMDC. The delay is equal to 0.5 management data clock period ±6 ns. For example, with a management data clock of 2.5 MHz, the min/max delay is 200 ns ± 6 ns. This figure shows the Ethernet management interface timing diagram. tMDCR tMDC MDC tMDCF tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX Figure 19. Ethernet management interface timing diagram 2.12.4 eTSEC IEEE Std 1588 timing specifications This section discusses the electrical characteristics for the eTSEC IEEE Std 1588 interfaces. 2.12.4.1 eTSEC IEEE Std 1588 DC electrical characteristics This table shows eTSEC IEEE Std 1588 DC electrical characteristics when operating at LVDD = 3.3 V supply. Table 42. eTSEC IEEE 1588 DC electrical characteristics (LVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 2 Input low voltage VIL — 0.9 V 2 Input high current (LVDD = Max, VIN = 2.1 V) IIH — 40 μA 1 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 84 Freescale Semiconductor Electrical characteristics Table 42. eTSEC IEEE 1588 DC electrical characteristics (LVDD = 3.3 V) (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes IIL –600 — μA 1 Output high voltage (LVDD = Min, IOH = –1.0 mA) VOH 2.4 — V — Output low voltage (LVDD = Min, IOL = 1.0 mA) VOL — 0.4 V — Input low current (LVDD = Max, VIN = 0.5 V) Note: 1. Note that the symbol VIN, in this case, represents the LVIN symbol referenced in Table 2 and Table 3. 2. The min VIL and max VIH values are based on the respective LVIN values found in Table 3. 2.12.4.2 eTSEC IEEE Std 1588 AC specifications This table provides the IEEE 1588 AC timing specifications. Table 43. eTSEC IEEE 1588 AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit Notes tT1588CLK 3.3 — TRX_CLK × 7 ns 1, 2 TSEC_1588_CLK duty cycle tT1588CLKH/ tT1588CLK 40 50 60 % 3 TSEC_1588_CLK peak-to-peak jitter tT1588CLKINJ — — 250 ps — Rise time eTSEC_1588_CLK (20%–80%) tT1588CLKINR 1.0 — 2.0 ns — Fall time eTSEC_1588_CLK (80%–20%) tT1588CLKINF 1.0 — 2.0 ns — TSEC_1588_CLK_OUT clock period tT1588CLKOUT 2 × tT1588CLK — — ns — TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/ tT1588CLKOUT 30 50 70 % — tT1588OV 0.5 — 3.0 ns — tT1588TRIGH 2 × tT1588CLK_MAX — — ns 2 TSEC_1588_CLK clock period TSEC_1588_PULSE_OUT TSEC_1588_TRIG_IN pulse width Notes: 1.TRX_CLK is the maximum clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the QorIQ Integrated Processor Reference Manual for a description of TMR_CTRL registers. 2. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK be 2800, 280, and 56 ns, respectively. 3. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the QorIQ Integrated Processor Reference Manual for a description of TMR_CTRL registers. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 85 Electrical characteristics This figure shows the data and command output AC timing diagram. tT1588CLKOUT tT1588CLKOUTH TSEC_1588_CLK_OUT tT1588OV TSEC_1588_PULSE_OUT TSEC_1588_TRIG_OUT Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is counted starting at the falling edge. Figure 20. eTSEC IEEE 1588 output AC timing This figure shows the data and command input AC timing diagram. tT1588CLK tT1588CLKH TSEC_1588_CLK TSEC_1588_TRIG_IN tT1588TRIGH Figure 21. eTSEC IEEE 1588 input AC timing 2.13 USB This section provides the AC and DC electrical specifications for the USB interface. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 86 Freescale Semiconductor Electrical characteristics 2.13.1 USB DC electrical characteristics This table provides the DC electrical characteristics for the USB interface at USB_VDD_3P3 = 3.3 V. Table 44. USB DC electrical characteristics (USB_VDD_3P3 = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage1 VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Input current (USB_VIN_3P3 = 0 V or USB_VIN_3P3 = USB_VDD_3P3) IIN — ±40 μA 2 Output high voltage (USB_VDD_3P3 = min, IOH = –2 mA) VOH 2.8 — V — Output low voltage (USB_VDD_3P3 = min, IOL = 2 mA) VOL — 0.3 V — Notes: 1. The min VILand max VIH values are based on the respective min and max USB_VIN_3P3 values found in Table 3. 2. The symbol USB_VIN_3P3, in this case, represents the USB_VIN_3P3 symbol referenced in Section 2.1.2, “Recommended operating conditions.” 2.13.2 USB AC electrical specifications This table provides the USB clock input (USBn_CLKIN) AC timing specifications. Table 45. USBn_CLKIN AC timing specifications For recommended operating conditions, see Table 3. Parameter/Condition Conditions Symbol Min Typ Max Unit Frequency range — fUSB_CLK_IN — 24 — MHz Clock frequency tolerance — tCLK_TOL –0.005 0 0.005 % tCLK_DUTY 40 50 60 % tCLK_PJ — — 5 ps Reference clock duty cycle Measured at 1.6 V Total input jitter/time interval error Peak-to-peak value measured with a second-order high-pass filter of 500 kHz bandwidth This figure provides the USB AC test load. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 22. USB AC test load 2.14 Enhanced local bus interface (eLBC) This section describes the DC and AC electrical specifications for the enhanced local bus interface. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 87 Electrical characteristics 2.14.1 Enhanced local bus DC electrical characteristics This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 3.3 V. Table 46. Enhanced local bus DC electrical characteristics (BVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Input current (VIN = 0 V or VIN = BVDD) IIN — ±40 μA 2 Output high voltage (BVDD = min, IOH = –2 mA) VOH 2.4 — V — Output low voltage (BVDD = min, IOL = 2 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3. 2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 2.5 V. Table 47. Enhanced local bus DC electrical characteristics (BVDD = 2.5 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.7 — V 1 Input low voltage VIL — 0.7 V 1 Input current (VIN = 0 V or VIN = BVDD) IIN — ±40 μA 2 Output high voltage (BVDD = min, IOH = –1 mA) VOH 2.0 — V — Output low voltage (BVDD = min, IOL = 1 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3 2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” This table provides the DC electrical characteristics for the enhanced local bus interface operating at BVDD = 1.8 V. Table 48. Enhanced local bus DC electrical characteristics (BVDD = 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.25 — V 1 Input low voltage VIL — 0.6 V 1 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 88 Freescale Semiconductor Electrical characteristics Table 48. Enhanced local bus DC electrical characteristics (BVDD = 1.8 V) (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes IIN — ±40 μA 2 Output high voltage (BVDD = min, IOH = –0.5 mA) VOH 1.35 — V — Output low voltage (BVDD = min, IOL = 0.5 mA) VOL — 0.4 V — Input current (VIN = 0 V or VIN = BVDD) Notes: 1. The min VILand max VIH values are based on the respective min and max BVIN values found in Table 3. 2. The symbol VIN, in this case, represents the BVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” 2.14.2 Enhanced local bus AC timing specifications This section describes the AC timing specifications for the enhanced local bus interface. 2.14.2.1 Test condition This figure provides the AC test load for the enhanced local bus. Z0 = 50 Ω Output RL = 50 Ω BVDD/2 Figure 23. Enhanced local bus AC test load 2.14.2.2 Local bus AC timing specification All output signal timings are relative to the falling edge of any LCLKs. The external circuit must use the rising edge of the LCLKs to latch the data. All input timings except LGTA/LUPWAIT/LFRB are relative to the rising edge of LCLKs. LGTA/LUPWAIT/LFRB are relative to the falling edge of LCLKs. This table describes the timing specifications of the local bus interface. Table 49. Enhanced local bus timing specifications For recommended operating conditions, see Table 3. Symbol1 Min Max Unit Notes Local bus cycle time tLBK 10 — ns — Local bus duty cycle tLBKH/tLBK 45 55 % — LCLK[n] skew to LCLK[m] tLBKSKEW — 150 ps 2 Input setup (except LGTA/LUPWAIT/LFRB) tLBIVKH 6 — ns — Input hold (except LGTA/LUPWAIT/LFRB) tLBIXKH 1 — ns — Parameter P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 89 Electrical characteristics Table 49. Enhanced local bus timing specifications (continued) For recommended operating conditions, see Table 3. Symbol1 Min Max Unit Notes Input setup (for LGTA/LUPWAIT/LFRB) tLBIVKL 6 — ns — Input hold (for LGTA/LUPWAIT/LFRB) tLBIXKL 1 — ns — Output delay (Except LALE) tLBKLOV — 1.5 ns — Output hold (Except LALE) tLBKLOX -3.5 — ns 5 Local bus clock to output high impedance for LAD/LDP tLBKLOZ — 2 ns 3 LALE output negation to LAD/LDP output transition (LATCH hold time) tLBONOT 2 platform clock cycles—1ns (LBCR[AHD]=1) — ns 4 4 platform clock cycles—1ns (LBCR[AHD]=0) — Parameter Notes: 1. All signals are measured from BVDD/2 of rising/falling edge of LCLK to BVDD/2 of the signal in question. 2. Skew measured between different LCLKs at BVDD/2. 3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. tLBONOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBONOT is determined by LBCR[AHD]. The unit is the eLBC controller clock cycle, which is the internal clock that runs the local bus controller, not the external LCLK. LCLK cycle = eLBC controller clock cycle X LCRR[CLKDIV]. After power on reset, LBCR[AHD] defaults to 0 and eLBC runs at maximum hold time. 5. Output hold is negative. This means that output transition happens earlier than the falling edge of LCLK. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 90 Freescale Semiconductor Electrical characteristics This figure shows the AC timing diagram of the local bus interface. LCLK[m] tLBIXKH tLBIVKH Input Signals (Except LGTA/LUPWAIT/LFRB) tLBIVKL Input Signal (LGTA/LUPWAIT/LFRB) tLBIXKL tLBKLOV tLBKLOX Output Signals (Except LALE) LAD (address phase) tLBONOT LALE tLBKLOZ LAD/LDP (data phase) Figure 24. Enhanced local bus signals Figure 25 applies to all three controllers that eLBC supports: GPCM, UPM, and FCM. For input signals, the local bus AC timing data is used directly for all three controllers. For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed to delay by tacs (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is tacs + tLBKLOV. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 91 Electrical characteristics This figure shows how the local bus AC timing diagram applies to GPCM. The same principle applies to UPM and FCM. LCLK taddr LAD[0:31] taddr address read data write data address tLBONOT tLBONOT LALE LCS_B tarcs + tLBKLOV tawcs + tLBKLOV tLBKLOX LGPL2/LOE_B taoe + tLBKLOV LWE_B twen tawe + tLBKLOV trc toen twc LBCTL read 1 2 write taddr is programmable and determined by LCRR[EADC] and ORx[EAD]. tarcs, tawcs, taoe, trc, toen, tawe, twc, twen are determined by ORx. See the applicable chip reference manual. Figure 25. GPCM Output timing diagram 2.15 Enhanced secure digital host controller (eSDHC) This section describes the DC and AC electrical specifications for the eSDHC interface. 2.15.1 eSDHC DC electrical characteristics This table provides the DC electrical characteristics for the eSDHC interface. Table 50. eSDHC interface DC electrical characteristics For recommended operating conditions, see Table 3. Characteristic Symbol Condition Min Max Unit Notes Input high voltage VIH — 0.625 × CVDD — V 1 Input low voltage VIL — — 0.25 × CVDD V 1 IIN/IOZ — –50 50 μA — VOH IOH = –100 μA at CVDD min 0.75 × CVDD — V — Input/output leakage current Output high voltage P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 92 Freescale Semiconductor Electrical characteristics Table 50. eSDHC interface DC electrical characteristics (continued) For recommended operating conditions, see Table 3. Characteristic Symbol Condition Min Max Unit Notes Output low voltage VOL IOL = 100μA at CVDD min — 0.125 × CVDD V — Output high voltage VOH IOH = –100 μA at CVDD min CVDD – 0.2 — V 2 Output low voltage VOL IOL = 2 mA at CVDD min — 0.3 V 2 Notes: 1. The min VILand max VIH values are based on the respective min and max CVIN values found in Table 3. 2. Open drain mode for MMC cards only. 2.15.2 eSDHC AC timing specifications This table provides the eSDHC AC timing specifications as defined in Figure 26 and Figure 27. Table 51. eSDHC AC timing specifications For recommended operating conditions, see Table 3. Parameter SD_CLK clock frequency: Symbol1 Min Max 0 25/50 20/52 fSHSCK SD Full speed/high speed mode MMC Full speed/high speed mode Unit Notes MHz 2, 4 SD_CLK clock low time—Full-speed/High-speed mode tSHSCKL 10/7 — ns 4 SD_CLK clock high time—Full-speed/High-speed mode tSHSCKH 10/7 — ns 4 SD_CLK clock rise and fall times tSHSCKR/ tSHSCKF — 3 ns 4 Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIVKH 5 — ns 3, 4, 5 Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIXKH 2.5 — ns 4, 5 Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV –3 3 ns 4, 5 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. In full-speed mode, the clock frequency value can be 0–25 MHz for an SD card and 0–20 MHz for an MMC card. In high-speed mode, the clock frequency value can be 0–50 MHz for an SD card and 0–52 MHz for an MMC card. 3. To satisfy setup timing, one way board routing delay between Host and Card, on SD_CLK, SD_CMD and SD_DATx should not exceed 1 ns. For any high speed or default speed mode SD card, the oneway routing delay between Host and Card on SD_CLK, SD_CMD and SD_DATx should not exceed 1.5 ns. 4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF 5. The parameter values apply to both full speed and high speed modes. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 93 Electrical characteristics This figure provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode VM VM VM tSHSCKL tSHSCKH tSHSCK VM = Midpoint Voltage (OVDD/2) tSHSCKR tSHSCKF Figure 26. eSDHC clock input timing diagram This figure provides the data and command input/output timing diagram. VM SD_CK External Clock VM VM VM tSHSIXKH tSHSIVKH SD_DAT/CMD Inputs SD_DAT/CMD Outputs tSHSKHOV VM = Midpoint Voltage (OVDD/2) Figure 27. eSDHC data and command input/output timing diagram referenced to clock 2.16 Multicore programmable interrupt controller (MPIC) specifications This section describes the DC and AC electrical specifications for the multicore programmable interrupt controller. 2.16.1 MPIC DC specifications This table provides the DC electrical characteristics for the MPIC interface. Table 52. MPIC DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA 2 VOH 2.4 — V — Output high voltage (OVDD = min, IOH = –2 mA) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 94 Freescale Semiconductor Electrical characteristics Table 52. MPIC DC electrical characteristics (OVDD = 3.3 V) (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes VOL — 0.4 V — Output low voltage (OVDD = min, IOL = 2 mA) Notes: 1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3 2.16.2 MPIC AC timing specifications This table provides the MPIC input and output AC timing specifications. Table 53. MPIC Input AC timing specifications For recommended operating conditions, see Table 3. Characteristic MPIC inputs—minimum pulse width Symbol Min Max Unit Notes tPIWID 3 — SYSCLKs 1 Notes: 1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs should be synchronized before use by any external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode 2.17 JTAG controller This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface. 2.17.1 JTAG DC electrical characteristics This table provides the JTAG DC electrical characteristics. Table 54. JTAG DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA 2 Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V — Output low voltage (OVDD = min, IOL = 2 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3. 2. The symbol VIN, in this case, represents the OVIN symbol found in Table 3. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 95 Electrical characteristics 2.17.2 JTAG AC timing specifications This table provides the JTAG AC timing specifications as defined in Figure 28 through Figure 31. Table 55. JTAG AC timing specifications For recommended operating conditions, see Table 3. Symbol1 Min Max Unit Notes JTAG external clock frequency of operation fJTG 0 33.3 MHz — JTAG external clock cycle time tJTG 30 — ns — tJTKHKL 15 — ns — tJTGR/tJTGF 0 2 ns — TRST assert time tTRST 25 — ns 2 Input setup times tJTDVKH — ns — — ns — Boundary-scan data 15 ns 3 TDO 10 ns — — ns 3 Parameter JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times Boundary-scan USB only 14 Boundary-scan except USB 4 TMS 4 TDI 5 Input hold times tJTDXKH 10 Output valid times tJTKLDV — Output hold times tJTKLDX 0 Notes: 1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. This figure provides the AC test load for TDO and the boundary-scan outputs of the device. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 28. AC test load for the JTAG interface P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 96 Freescale Semiconductor Electrical characteristics This figure provides the JTAG clock input timing diagram. JTAG External Clock VM VM VM tJTGR tJTKHKL tJTGF tJTG VM = Midpoint Voltage (OVDD/2) Figure 29. JTAG clock input timing diagram This figure provides the TRST timing diagram. TRST VM VM tTRST VM = Midpoint Voltage (OVDD/2) Figure 30. TRST timing diagram This figure provides the boundary-scan timing diagram. JTAG External Clock VM VM tJTDVKH tJTDXKH Boundary Data Inputs Input Data Valid tJTKLDV tJTKLDX Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Figure 31. Boundary-scan timing diagram 2.18 I2C This section describes the DC and AC electrical characteristics for the I2C interface. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 97 Electrical characteristics 2.18.1 I2C DC electrical characteristics This table provides the DC electrical characteristics for the I2C interfaces. Table 56. I2C DC electrical characteristics (OVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Output low voltage (OVDD = min, IOL = 2 mA) VOL 0 0.4 V 2 tI2KHKL 0 50 ns 3 Input current each I/O pin (input voltage is between 0.1 × OVDD and 0.9 × OVDD(max) II –40 40 μA 4 Capacitance for each I/O pin CI 0 10 pF — Pulse width of spikes which must be suppressed by the input filter Notes: 1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3. 2. Output voltage (open drain or open collector) condition = 3 mA sink current. 3. See the applicable chip reference manual for information about the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off. 2.18.2 I2C AC electrical specifications This table provides the AC timing parameters for the I2C interfaces. Table 57. I2C AC timing specifications For recommended operating conditions, see Table 3. Symbol1 Min Max Unit Notes SCL clock frequency fI2C 0 400 kHz 2 Low period of the SCL clock tI2CL 1.3 — μs — High period of the SCL clock tI2CH 0.6 — μs — Setup time for a repeated START condition tI2SVKH 0.6 — μs — Hold time (repeated) START condition (after this period, the first clock pulse is generated) tI2SXKL 0.6 — μs — Data setup time tI2DVKH 100 — ns — μs 3 — 0 — — Parameter tI2DXKL Data input hold time: CBUS compatible masters I2C bus devices Data output delay time tI2OVKL — 0.9 μs 4 Setup time for STOP condition tI2PVKH 0.6 — μs — Bus free time between a STOP and START condition tI2KHDX 1.3 — μs — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 98 Freescale Semiconductor Electrical characteristics Table 57. I2C AC timing specifications (continued) For recommended operating conditions, see Table 3. Symbol1 Min Max Unit Notes Noise margin at the LOW level for each connected device (including hysteresis) VNL 0.1 × OVDD — V — Noise margin at the HIGH level for each connected device (including hysteresis) VNH 0.2 × OVDD — V — Capacitive load for each bus line Cb — 400 pF — Parameter Notes: 1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. 2. The requirements for I2C frequency calculation must be followed. See Freescale application note AN2919, “Determining the I2C Frequency Divider Ratio for SCL.” 3. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter, application note AN2919 referred to in note 2 above is recommended. 4. The maximum tI2OVKL must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal. This figure provides the AC test load for the I2C. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 32. I2C AC test load This figure shows the AC timing diagram for the I2C bus. SDA tI2DVKH tI2KHKL tI2KHDX tI2SXKL tI2CL SCL tI2SXKL S tI2CH tI2DXKL,tI2OVKL tI2SVKH tI2PVKH Sr P S 2 Figure 33. I C bus AC timing diagram P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 99 Electrical characteristics 2.19 GPIO This section describes the DC and AC electrical characteristics for the GPIO interface. 2.19.1 GPIO DC electrical characteristics This table provides the DC electrical characteristics for GPIO pins operating at 3.3 V. Table 58. GPIO DC electrical characteristics (LVDD or OVDD = 3.3 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 2.0 — V 1 Input low voltage VIL — 0.8 V 1 Input current (OVIN = 0 V or OVIN = OVDD) IIN — ±40 μA 2 Output high voltage (OVDD = min, IOH = –2 mA) VOH 2.4 — V — Output low voltage (OVDD = min, IOL = 2 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the min and max L/OVIN respective values found in Table 3. 2. The symbol VIN, in this case, represents the L/OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” This table provides the DC electrical characteristics for GPIO pins operating at LVDD = 2.5 V. Table 59. GPIO DC electrical characteristics (LVDD = 2.5 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Max Unit Notes Input high voltage VIH 1.7 — V 1 Input low voltage VIL — 0.7 V 1 Input current (VIN = 0 V or VIN = LVDD) IIN — ±40 μA 2 Output high voltage (LVDD = min, IOH = –2 mA) VOH 2.0 — V — Output low voltage (LVDD = min, IOH = 2 mA) VOL — 0.4 V — Notes: 1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3. 2. The symbol VIN, in this case, represents the LVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 100 Freescale Semiconductor Electrical characteristics 2.19.2 GPIO AC timing specifications This table provides the GPIO input and output AC timing specifications. Table 60. GPIO Input AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Unit Notes GPIO inputs—minimum pulse width tPIWID 20 ns 1 Trust inputs—minimum pulse width tTIWID 3 SYSCLK 2 Note: 1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation. 2. Trust inputs are asynchronous to any visible clock. Trust inputs are required to be valid for at least tTIWID to ensure proper operation. For low power trust input pin LP_TMP_DETECT, the voltage is VDD_LP and see Table 3.for the voltage requirement. This figure provides the AC test load for the GPIO. Output Z0 = 50 Ω RL = 50 Ω OVDD/2 Figure 34. GPIO AC test load 2.20 High-speed serial interfaces (HSSI) The chip features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The SerDes interface can be used for PCI Express, XAUI, Aurora and SGMII data transfers. This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown. 2.20.1 Signal terms definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 101 Electrical characteristics This figure shows how the signals are defined. For illustration purposes only, one SerDes lane is used in the description. This figure shows the waveform for either a transmitter output (SD_TXn and SD_TXn) or a receiver input (SD_RXn and SD_RXn). Each signal swings between A volts and B volts where A > B. SD_TXn SD_RXn or SD_TXn SD_RXn or A Volts Vcm = (A + B)/2 B Volts Differential Swing, VID or VOD = A – B Differential Peak Voltage, VDIFFp = |A – B| Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown) Figure 35. Differential voltage definitions for transmitter or receiver Using this waveform, the definitions are as shown in the following list. To simplify the illustration, the definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment: Single-Ended Swing The transmitter output signals and the receiver input signals SD_TXn, SD_TXn, SD_RXn and SD_RXn each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s single-ended swing. Differential Output Voltage, VOD (or Differential Output Swing): The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complementary output voltages: VSD_TXn – VSD_TXn. The VOD value can be either positive or negative. Differential Input Voltage, VID (or Differential Input Swing): The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two complementary input voltages: VSD_RXn – VSD_RXn. The VID value can be either positive or negative. Differential Peak Voltage, VDIFFp The peak value of the differential transmitter output signal or the differential receiver input signal is defined as the differential peak voltage, VDIFFp = |A – B| volts. Differential Peak-to-Peak, VDIFFp-p Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, VDIFFp-p = 2 × VDIFFp = 2 × |(A – B)| volts, which is twice the differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as VTX-DIFFp-p = 2 × |VOD|. Differential Waveform The differential waveform is constructed by subtracting the inverting signal (SD_TXn, for example) from the non-inverting signal (SD_TXn, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 102 Freescale Semiconductor Electrical characteristics waveform is not referenced to ground. See Figure 40, “Differential measurement points for rise and fall time,” as an example for differential waveform. Common Mode Voltage, Vcm The common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, Vcm_out = (VSD_TXn + VSD_TXn) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complementary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. It may be different between the receiver input and driver output circuits within the same component. It is also referred to as the DC offset on some occasions. To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV. In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p. 2.20.2 SerDes reference clocks The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK1 and SD_REF_CLK1 for SerDes bank1, SD_REF_CLK2 and SD_REF_CLK2 for SerDes bank2, SD_REF_CLK3 and SD_REF_CLK3 for SerDes bank3, and SD_REF_CLK4 and SD_REF_CLK4 for SerDes bank4. SerDes banks 1–4 may be used for various combinations of the following IP blocks based on the RCW Configuration field SRDS_PRTCL: • • • • SerDes bank 1: PEX1/2/3, SGMII (1.25 Gbps only) or Aurora. SerDes bank 2: SGMII (1.25 or 3.125 GBaud) or XAUI. SerDes bank 3: SATA, or XAUI. SerDes bank 4: SATA The following sections describe the SerDes reference clock requirements and provide application information. 2.20.2.1 SerDes reference clock receiver characteristics This figure shows a receiver reference diagram of the SerDes reference clocks. 50 Ω SD_REF_CLKn Input Amp SD_REF_CLKn 50 Ω Figure 36. Receiver of SerDes reference clocks P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 103 Electrical characteristics The characteristics of the clock signals are as follows: • • • • The SerDes transceivers core power supply voltage requirements (SVDD) are as specified in Section 2.1.2, “Recommended operating conditions.” The SerDes reference clock receiver reference circuit structure is as follows: — The SD_REF_CLKn and SD_REF_CLKn are internally AC-coupled differential inputs as shown in Figure 36. Each differential clock input (SD_REF_CLKn or SD_REF_CLKn) has on-chip 50-Ω termination to SGND followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. — The SerDes reference clock input can be either differential or single-ended. See the differential mode and single-ended mode descriptions below for detailed requirements. The maximum average current requirement also determines the common mode voltage range. — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV. — If the device driving the SD_REF_CLKn and SD_REF_CLKn inputs cannot drive 50 Ω to SGND DC or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip. The input amplitude requirement is described in detail in the following sections. 2.20.2.2 DC-level requirement for SerDes reference clocks The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs, as described below: • Differential Mode — The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For an external DC-coupled connection, as described in Section 2.20.2.1, “SerDes reference clock receiver characteristics,” the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 37 shows the SerDes reference clock input requirement for DC-coupled connection scheme. SD_REF_CLKn 200 mV < Input Amplitude or Differential Peak < 800 mV Vmax 100 mV < Vcm < 400 mV Vmin SD_REF_CLKn < 800 mV >0V Figure 37. Differential reference clock input DC requirements (external DC-coupled) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 104 Freescale Semiconductor Electrical characteristics — For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Because the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different common mode voltages. The SerDes reference clock receiver in this connection scheme has its common mode voltage set to SGND. Each signal wire of the differential inputs is allowed to swing below and above the common mode voltage (SGND). Figure 38 shows the SerDes reference clock input requirement for AC-coupled connection scheme. 200 mV < Input Amplitude or Differential Peak < 800 mV SD_REF_CLKn Vmax < Vcm + 400 mV Vcm Vmin SD_REF_CLKn > Vcm – 400 mV Figure 38. Differential reference clock input DC requirements (external AC-coupled) • Single-Ended Mode — The reference clock can also be single-ended. The SD_REF_CLKn input amplitude (single-ended swing) must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SD_REF_CLKn either left unconnected or tied to ground. — The SD_REF_CLKn input average voltage must be between 200 and 400 mV. Figure 39 shows the SerDes reference clock input requirement for single-ended signaling mode. — To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused phase (SD_REF_CLKn) through the same source impedance as the clock input (SD_REF_CLKn) in use. 400 mV < SD_REF_CLKn Input Amplitude < 800 mV SD_REF_CLKn 0V SD_REF_CLKn Figure 39. Single-ended reference clock input DC requirements P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 105 Electrical characteristics 2.20.2.3 AC requirements for SerDes reference clocks This table lists AC requirements for the PCI Express, SGMII, Serial RapidIO and Aurora SerDes reference clocks to be guaranteed by the customer’s application design. Table 61. SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit Notes SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF — 100/125 — MHz 1 SD_REF_CLK/SD_REF_CLK clock frequency tolerance tCLK_TOL –350 — 350 ppm — tCLK_DUTY 40 50 60 % 4 SD_REF_CLK/SD_REF_CLK max deterministic peak-peak jitter at 10-6 BER tCLK_DJ — — 42 ps — SD_REF_CLK/SD_REF_CLK total reference clock jitter at 10-6 BER (peak-to-peak jitter at refClk input) tCLK_TJ — — 86 ps 2 SD_REF_CLK/SD_REF_CLK rising/falling edge rate tCLKRR/tCLKFR 1 — 4 V/ns 3 Differential input high voltage VIH 200 — — mV 4 Differential input low voltage VIL — — –200 mV 4 Rise-Fall Matching — — 20 % 5, 6 SD_REF_CLK/SD_REF_CLK reference clock duty cycle Rising edge rate (SD_REF_CLKn) to falling edge rate (SD_REF_CLKn) matching Notes: 1. Caution: Only 100 and 125 have been tested. In-between values not work correctly with the rest of the system. 2. Limits from PCI Express CEM Rev 2.0 3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 40. 4. Measurement taken from differential waveform 5. Measurement taken from single-ended waveform 6. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 41. Rise Edge Rate Fall Edge Rate VIH = +200 mV 0.0 V VIL = –200 mV SD_REF_CLKn – SD_REF_CLKn Figure 40. Differential measurement points for rise and fall time P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 106 Freescale Semiconductor Electrical characteristics SDn_REF_CLK SDn_REF_CLK TFALL TRISE VCROSS MEDIAN + 100 mV VCROSS MEDIAN VCROSS MEDIAN VCROSS MEDIAN – 100 mV SDn_REF_CLK SDn_REF_CLK Figure 41. Single-ended measurement points for rise and fall time matching 2.20.2.4 Spread-spectrum clock SD_REF_CLK1/SD_REF_CLK1 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results, a source without significant unintended modulation should be used. SD_REF_CLK2/SD_REF_CLK2 were designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock and the industry protocol specifications supports it. For better results, a source without significant unintended modulation should be used. SD_REF_CLK3/SD_REF_CLK3 are not intended to be used with, and should not be clocked by, a spread spectrum clock source. SD_REF_CLK4/SD_REF_CLK4 are not intended to be used with, and should not be clocked by, a spread spectrum clock source. 2.20.3 SerDes transmitter and receiver reference circuits This figure shows the reference circuits for SerDes data lane’s transmitter and receiver. SD_TXn SD_RXn 50 Ω 50 Ω Transmitter Receiver 50 Ω SD_TXn SD_RXn 50 Ω Figure 42. SerDes transmitter and receiver reference circuits The DC and AC specification of SerDes data lanes are defined in each interface protocol section below based on the application usage: • • • • • Section 2.20.4, “PCI Express” Section 2.20.5, “XAUI” Section 2.20.6, “Aurora” Section 2.20.7, “Serial ATA (SATA) Section 2.20.8, “SGMII interface” Note that external AC-coupling capacitor is required for the above serial transmission protocols per the protocol’s standard requirements. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 107 Electrical characteristics 2.20.4 PCI Express This section describes the clocking dependencies, DC and AC electrical specifications for the PCI Express bus. 2.20.4.1 Clocking dependencies The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance. 2.20.4.2 PCI Express clocking requirements for SD_REF_CLKn and SD_REF_CLKn SerDes banks 1–2 (SD_REF_CLK[1:2] and SD_REF_CLK[1:2]) may be used for various SerDes PCI Express configurations based on the RCW Configuration field SRDS_PRTCL. PCI Express is not supported on SerDes bank 3. For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.” 2.20.4.3 PCI Express DC physical layer specifications This section contains the DC specifications for the physical layer of PCI Express on this device. 2.20.4.3.1 PCI Express DC physical layer transmitter specifications This section discusses the PCI Express DC physical layer transmitter specifications for 2.5 GT/s and 5 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 62. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Units VTX-DIFFp-p 800 — 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1. De-emphasized differential VTX-DE-RATIO output voltage (ratio) 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 1. DC differential transmitter impedance 80 100 120 Ω Transmitter DC differential mode low Impedance 40 50 60 Ω Required transmitter D+ as well as D– DC Impedance during all states Differential peak-to-peak output voltage ZTX-DIFF-DC Transmitter DC impedance ZTX-DC Notes Note: 1. Measured at the package pins with a test load of 50Ω to GND on each pin. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 108 Freescale Semiconductor Electrical characteristics This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 63. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Min Typical Max Units Notes 800 — 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1. Low Power differential VTX-DIFFp-p_low peak-to-peak output voltage 400 500 1200 mV VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D-| See Note 1. De-emphasized differential VTX-DE-RATIO-3.5dB output voltage (ratio) 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 1. De-emphasized differential VTX-DE-RATIO-6.0dB output voltage (ratio) 5.5 6.0 6.5 dB Ratio of the VTX-DIFFp-p of the second and following bits after a transition divided by the VTX-DIFFp-p of the first bit after a transition. See Note 1. DC differential transmitter impedance 80 100 120 Ω Transmitter DC differential mode low impedance 40 50 60 Ω Required transmitter D+ as well as D– DC impedance during all states Differential peak-to-peak output voltage Symbol VTX-DIFFp-p ZTX-DIFF-DC Transmitter DC Impedance ZTX-DC Note: 1. Measured at the package pins with a test load of 50Ω to GND on each pin. 2.20.4.4 PCI Express DC physical layer receiver specifications This section discusses the PCI Express DC physical layer receiver specifications 2.5 GT/s, and 5 GT/s. This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins. Table 64. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Differential input peak-to-peak voltage VRX-DIFFp-p 120 — 1200 mV DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode impedance. See Note 2 ZRX-DC 40 50 60 Ω Required receiver D+ as well as D– DC Impedance (50 ±20% tolerance). See Notes 1 and 2. DC input impedance Max Units Notes VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| See Note 1. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 109 Electrical characteristics Table 64. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (XVDD = 1.5 V or 1.8 V) (continued) Parameter Powered down DC input impedance Electrical idle detect threshold Symbol Min Typ Max Units Notes ZRX-HIGH-IMP-DC 50 k — — Ω Required receiver D+ as well as D– DC Impedance when the receiver terminations do not have power. See Note 3. VRX-IDLE-DET-DIFFp-p 65 — 175 mV VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–| Measured at the package pins of the receiver Notes: 1. Measured at the package pins with a test load of 50 Ω to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers. The parameters are specified at the component pins. Table 65. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Differential input peak-to-peak voltage VRX-DIFFp-p 120 — 1200 V VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–| See Note 1. DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC Differential mode impedance. See Note 2 ZRX-DC 40 50 60 Ω Required receiver D+ as well as D– DC Impedance (50 ±20% tolerance). See Notes 1 and 2. ZRX-HIGH-IMP-DC 50 — — kΩ Required receiver D+ as well as D– DC Impedance when the receiver terminations do not have power. See Note 3. VRX-IDLE-DET-DIFFp-p 65 — 175 mV VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–| Measured at the package pins of the receiver DC input impedance Powered down DC input impedance Electrical idle detect threshold Max Units Notes Notes: 1. Measured at the package pins with a test load of 50Ω to GND on each pin. 2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the receiver ground. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 110 Freescale Semiconductor Electrical characteristics 2.20.4.5 PCI Express AC physical layer specifications This section contains the DC specifications for the physical layer of PCI Express on this device. 2.20.4.5.1 PCI Express AC physical layer transmitter specifications This section discusses the PCI Express AC physical layer transmitter specifications 2.5 GT/s, and 5 GT/s. This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 66. PCI Express 2.0 (2.5 GT/s) differential transmitter Output AC specifications For recommended operating conditions, see Table 3. Parameter Unit interval Minimum transmitter eye width Maximum time between the jitter median and maximum deviation from the median AC coupling capacitor Symbol Min Typ Max Units UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. TTX-EYE 0.75 — — UI The maximum transmitter jitter can be derived as TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI. Does not include spread spectrum or RefCLK jitter. Includes device random jitter at 10-12. See Notes 2 and 3. TTX-EYE-MEDIAN- — — 0.125 UI Jitter is defined as the measurement variation of the crossing points (VTX-DIFFp-p = 0 V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI. See Notes 2 and 3. 75 — 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 4. toMAX-JITTER CTX Notes Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250 consecutive transmitter UIs. 3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 111 Electrical characteristics This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential output at all transmitters. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 67. PCI Express 2.0 (5 GT/s) differential transmitter Output AC specifications For recommended operating conditions, see Table 3. Parameter Unit Interval Symbol UI Min Typ Max 199.94 200.00 200.06 Units Notes ps Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. The maximum transmitter jitter can be derived as: TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI. See Notes 2 and 3. Minimum transmitter eye width TTX-EYE 0.75 — — UI Transmitter RMS deterministic jitter > 1.5 MHz TTX-HF-DJ-DD — — 0.15 ps — Transmitter RMS deterministic jitter < 1.5 MHz TTX-LF-RMS — 3.0 — ps Reference input clock RMS jitter (< 1.5 MHz) at pin < 1 ps CTX 75 — 200 nF All transmitters must be AC coupled. The AC coupling is required either within the media or within the transmitting component itself. See Note 4. AC coupling capacitor Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage test load as shown in Figure 43 and measured over any 250 consecutive transmitter UIs. 3. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. The chip’s SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required. 2.20.4.5.2 PCI Express AC physical layer receiver specifications This section discusses the PCI Express AC physical layer receiver specifications 2.5 GT/s, and 5 GT/s. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 112 Freescale Semiconductor Electrical characteristics This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential input at all receivers. The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 68. PCI Express 2.0 (2.5 GT/s) differential receiver Input AC specifications For recommended operating conditions, see Table 3. Parameter Unit Interval Symbol UI Min Typ Max 399.88 400.00 400.12 Units Notes ps Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. Minimum receiver eye width TRX-EYE 0.4 — — UI The maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as TRX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI. See Notes 2 and 3. Maximum time between the jitter median and maximum deviation from the median. TRX-EYE-MEDIAN- — — 0.3 UI Jitter is defined as the measurement variation of the crossing points (VRX-DIFFp-p = 0 V) in relation to a recovered transmitter UI. A recovered transmitter UI is calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the transmitter UI. See Notes 2, 3 and 4. to-MAX-JITTER Notes: 1. No test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive transmitter UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 4. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 113 Electrical characteristics This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential input at all receivers (RXs). The parameters are specified at the component pins. The AC timing specifications do not include RefClk jitter. Table 69. PCI Express 2.0 (5 GT/s) differential receiver Input AC specifications For recommended operating conditions, see Table 3. Parameter Unit Interval Symbol UI Min Typ Max 199.94 200.00 200.06 Units Notes ps Each UI is 400 ps ±300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. Max receiver inherent timing error TRX-TJ-CC — — 0.4 UI The maximum inherent total timing error for common RefClk receiver architecture Maximum time between the jitter median and maximum deviation from the median TRX-TJ-DC — — 0.34 UI Max receiver inherent total timing error Max receiver inherent deterministic timing error TRX-DJ-DD-CC — — 0.30 UI The maximum inherent deterministic timing error for common RefClk receiver architecture Max receiver inherent deterministic timing error TRX-DJ-DD-DC — — 0.24 UI The maximum inherent deterministic timing error for common RefClk receiver architecture Note: 1. No test load is necessarily associated with this value. 2.20.4.6 Test and measurement load The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be connected to the test/measurement load within 0.2 inches of that load, as shown in Figure 43. NOTE The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the D+ and D– package pins. D+ package pin C = CTX Transmitter silicon + package C = CTX D– package pin R = 50 Ω R = 50 Ω Figure 43. Test/Measurement load P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 114 Freescale Semiconductor Electrical characteristics 2.20.5 XAUI This section describes the DC and AC electrical specifications for the XAUI bus. 2.20.5.1 XAUI DC electrical characteristics This section discusses the XAUI DC electrical characteristics for the clocking signals, transmitter, and receiver. 2.20.5.1.1 DC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn Only SerDes banks 2–3 (SD_REF_CLK[2:3] and SD_REF_CLK[2:3]) may be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1. For more information on these specifications, see Section 2.20.2.2, “DC-level requirement for SerDes reference clocks.” 2.20.5.1.2 XAUI transmitter DC electrical characteristics This table defines the XAUI transmitter DC electrical characteristics. Table 70. XAUI transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Output voltage Differential output voltage Symbol Min Typical Max Unit Notes VO –0.40 — 2.30 V 1 VDIFFPP 800 — 1600 mV p-p — Note: 1. Absolute output voltage limit 2.20.5.1.3 XAUI receiver DC electrical characteristics This table defines the XAUI receiver DC electrical characteristics. Table 71. XAUI receiver DC timing specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Differential input voltage Symbol Min Typical Max Unit Notes VIN 200 900 1600 mV p-p 1 Note: 1. Measured at the receiver. 2.20.5.2 XAUI AC timing specifications This section discusses the XAUI AC timing specifications for the clocking signals, transmitter, and receiver. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 115 Electrical characteristics 2.20.5.2.1 AC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn This table specifies AC requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [2:3]. Only SerDes banks 2–3 may be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported on SerDes bank 1. Table 72. XAUI AC SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit Notes SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF — 125/ 156.25 — MHz — SD_REF_CLK/SD_REF_CLK clock frequency tolerance tCLK_TOL –100 — 100 ppm — tCLK_DUTY 40 50 60 % 2 SD_REF_CLK/SD_REF_CLK cycle to cycle jitter (period jitter at refClk input) tCLK_CJ — — 100 ps — SD_REF_CLK/SD_REF_CLK total reference clock jitter (peak-to-peak phase jitter at refClk input) tCLK_PJ -50 — 50 ps — tCLKRR/tCLKFR 1 — 4 V/ns 1 Differential input high voltage VIH 200 — — mV 2 Differential input low voltage VIL — — –200 mV 2 Rise-Fall Matching — — 20 % 3, 4 SD_REF_CLK/SD_REF_CLK reference clock duty cycle SD_REF_CLK/SD_REF_CLK rising/falling edge rate Rising edge rate (SD_REF_CLKn) to falling edge rate (SD_REF_CLKn) matching Notes: 1. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn – SD_REF_CLKn). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See Figure 40. 2. Measurement taken from differential waveform 3. Measurement taken from single-ended waveform 4. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 41. 2.20.5.2.2 XAUI transmitter AC timing specifications This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not included. Table 73. XAUI transmitter AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Unit Notes Deterministic jitter JD — — 0.17 UI p-p — Total jitter JT — — 0.35 UI p-p — Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps — P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 116 Freescale Semiconductor Electrical characteristics 2.20.5.2.3 XAUI receiver AC timing specifications This table defines the receiver AC specifications for XAUI. RefClk jitter is not included. Table 74. XAUI receiver AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Unit Notes Deterministic jitter tolerance JD 0.37 — — UI p-p 1 Combined deterministic and random jitter tolerance JDR 0.55 — — UI p-p 1 JT 0.65 — — UI p-p 1, 2 — — ps — Total jitter tolerance Bit error rate Unit Interval: 3.125 GBaud BER — — 10–12 UI 320 – 100 ppm 320 320 + 100 ppm Notes: 1. Measured at receiver 2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects. This figure shows the single-frequency sinusoidal jitter limits. 8.5 UI p-p Sinusoidal jitter amplitude 0.10 UI p-p 22.1 kHz Frequency 1.875 MHz 20 MHz Figure 44. Single-Frequency Sinusoidal Jitter Limits P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 117 Electrical characteristics 2.20.6 Aurora This section describes the Aurora clocking requirements and AC and DC electrical characteristics. 2.20.6.1 Aurora DC electrical characteristics This section describes the DC electrical characteristics for Aurora. 2.20.6.1.1 Aurora DC clocking requirements for SD_REF_CLKn and SD_REF_CLKn Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2-3. For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.” 2.20.6.1.2 Aurora transmitter DC electrical characteristics This table defines the Aurora transmitter DC electrical characteristics. Table 75. Aurora transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Differential output voltage 2.20.6.1.3 Symbol Min Typical Max Unit VDIFFPP 800 — 1600 mV p-p Aurora receiver DC electrical characteristics This table defines the Aurora receiver DC electrical characteristics for Aurora. Table 76. Aurora receiver DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Differential input voltage Symbol Min Typical Max Unit Notes VIN 120 900 1200 mV p-p 1 Note: 1. Measured at receiver 2.20.6.2 Aurora AC timing specifications This section describes the AC timing specifications for Aurora. 2.20.6.2.1 Aurora AC clocking requirements for SD_REF_CLKn and SD_REF_CLKn Only SerDes bank 1 (SD_REF_CLK1 and SD_REF_CLK1) may be used for SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL. Aurora is not supported on SerDes banks 2–3. Please note that the XAUI clock requirements for SD_REF_CLKn and SD_REF_CLKn are intended to be used within the clocking guidelines specified by either Section 2.20.2.3, “AC requirements for SerDes reference clocks” or Section 2.20.7.2.1, “AC requirements for SATA REF_CLK.” P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 118 Freescale Semiconductor Electrical characteristics 2.20.6.2.2 Aurora transmitter AC timing specifications This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not included. Table 77. Aurora transmitter AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Unit Deterministic jitter JD — — 0.17 UI p-p Total jitter JT — — 0.35 UI p-p Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps 2.20.6.2.3 Aurora receiver AC timing specifications This table defines the Aurora receiver AC timing specifications. RefClk jitter is not included. Table 78. Aurora receiver AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Unit Notes Deterministic jitter tolerance JD 0.37 — — UI p-p 1 Combined deterministic and random jitter tolerance JDR 0.55 — — UI p-p 1 JT 0.65 — — UI p-p 1,2 — — Total jitter tolerance BER — — 10–12 Unit Interval: 2.5 GBaud UI 400 – 100 ppm 400 400 + 100 ppm ps — Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps — Unit Interval: 5.0 GBaud UI 200 – 100 ppm 200 200 + 100 ppm ps — Bit error rate Note: 1. Measured at receiver 2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. 2.20.7 Serial ATA (SATA) This section describes the DC and AC electrical specifications for the serial ATA (SATA) interface. 2.20.7.1 SATA DC electrical characteristics This section describes the DC electrical characteristics for SATA. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 119 Electrical characteristics 2.20.7.1.1 SATA DC transmitter Output Characteristics This table provides the DC differential transmitter output DC characteristics for the transmission. Table 79. Gen1i/1.5G transmitter DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Transmitter differential output voltage Transmitter differential pair impedance Symbol Min Typ Max Units Notes VSATA_TXDIFF 400 — 600 mV p-p 1 ZSATA_TXDIFFIM 85 100 115 Ω 2 Notes: 1. Terminated by 50 Ω load 2. DC impedance This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. Table 80. Gen 2i/3G transmitter DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Transmitter diff output voltage Transmitter differential pair impedance Symbol Min Typ Max Units Notes VSATA_TXDIFF 400 — 700 mV p-p 1 ZSATA_TXDIFFIM 85 100 115 Ω — Note: 1. Terminated by 50 Ω load 2.20.7.1.2 SATA DC receiver Input Characteristics This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 81. Gen1i/1.5 G receiver Input DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Units Notes Differential input voltage VSATA_RXDIFF 240 — 600 mV p-p 1 Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2 VSATA_OOB 50 120 240 mV p-p 2 OOB signal detection threshold Notes: 1. Voltage relative to common of either signal comprising a differential pair 2. DC impedance P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 120 Freescale Semiconductor Electrical characteristics This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 82. Gen2i/3 G receiver Input DC specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Units Notes Differential input voltage VSATA_RXDIFF 275 — 750 mV p-p 1 Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2 VSATA_OOB 75 120 240 mV p-p 2 OOB signal detection threshold Notes: 1. Voltage relative to common of either signal comprising a differential pair 2. DC impedance 2.20.7.2 SATA AC timing specifications This section discusses the SATA AC timing specifications. 2.20.7.2.1 AC requirements for SATA REF_CLK The AC requirements for the SATA reference clock are listed in this table to be guaranteed by the customer’s application design. Table 83. SATA reference clock input requirements For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit Notes SD_REF_CLK/SD_REF_CLK frequency range tCLK_REF — 100/125 — MHz 1 SD_REF_CLK/SD_REF_CLK clock frequency tolerance tCLK_TOL –350 — +350 ppm — SD_REF_CLK/SD_REF_CLK reference clock duty cycle tCLK_DUTY 40 50 60 % 5 SD_REF_CLK/SD_REF_CLK cycle-to-cycle clock jitter (period jitter) tCLK_CJ — — 100 ps 2 SD_REF_CLK/SD_REF_CLK total reference clock jitter, phase jitter (peak-peak) tCLK_PJ –50 — +50 ps 2, 3, 4 Notes: 1. Caution: Only 100, and 125 MHz have been tested. In-between values do not work correctly with the rest of the system. 2. At RefClk input 3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12 4. Total peak-to-peak deterministic jitter should be less than or equal to 50 ps. 5. Measurement taken from differential waveform P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 121 Electrical characteristics This figure shows the reference clock timing waveform. TH Ref_CLK TL Figure 45. Reference clock timing waveform 2.20.7.3 AC transmitter Output Characteristics This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Table 84. Gen1i/1.5 G transmitter AC specifications For recommended operating conditions, see Table 3. Parameter Channel speed Symbol Min Typ Max Units Notes tCH_SPEED — 1.5 — Gbps — TUI 666.4333 666.6667 670.2333 ps — USATA_TXTJ5UI — — 0.355 UI p-p 1 USATA_TXTJ250UI — — 0.47 UI p-p 1 USATA_TXDJ5UI — — 0.175 UI p-p 1 USATA_TXDJ250UI — — 0.22 UI p-p 1 Unit Interval Total jitter data-data 5 UI Total jitter, data-data 250 UI Deterministic jitter, data-data 5 UI Deterministic jitter, data-data 250 UI Note: 1. Measured at transmitter output pins peak to peak phase variation, random data pattern This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Table 85. Gen 2i/3 G transmitter AC specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Units Notes tCH_SPEED — 3.0 — Gbps — TUI 333.2167 333.3333 335.1167 ps — Total jitter fC3dB = fBAUD ÷ 10 USATA_TXTJfB/10 — — 0.3 UI p-p 1 Total jitter fC3dB = fBAUD ÷ 500 USATA_TXTJfB/500 — — 0.37 UI p-p 1 Total jitter fC3dB = fBAUD ÷ 1667 USATA_TXTJfB/1667 — — 0.55 UI p-p 1 Channel speed Unit Interval P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 122 Freescale Semiconductor Electrical characteristics Table 85. Gen 2i/3 G transmitter AC specifications (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Units Notes Deterministic jitter, fC3dB = fBAUD ÷ 10 USATA_TXDJfB/10 — — 0.17 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_TXDJfB/500 — — 0.19 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_TXDJfB/1667 — — 0.35 UI p-p 1 Note: 1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern 2.20.7.4 AC differential receiver Input characteristics This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface. The AC timing specifications do not include RefClk jitter. Table 86. Gen 1i/1.5G receiver AC specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Units Notes TUI 666.4333 666.6667 670.2333 ps — USATA_TXTJ5UI — — 0.43 UI p-p 1 USATA_TXTJ250UI — — 0.60 UI p-p 1 USATA_TXDJ5UI — — 0.25 UI p-p 1 USATA_TXDJ250UI — — 0.35 UI p-p 1 Unit Interval Total jitter data-data 5 UI Total jitter, data-data 250 UI Deterministic jitter, data-data 5 UI Deterministic jitter, data-data 250 UI Note: 1. Measured at receiver This table provides the differential receiver input AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission. The AC timing specifications do not include RefClk jitter. Table 87. Gen 2i/3G receiver AC specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Units Notes TUI 333.2167 333.3333 335.1167 ps — Total jitter fC3dB = fBAUD ÷ 10 USATA_TXTJfB/10 — — 0.46 UI p-p 1 Total jitter fC3dB = fBAUD ÷ 500 USATA_TXTJfB/500 — — 0.60 UI p-p 1 Total jitter fC3dB = fBAUD ÷ 1667 USATA_TXTJfB/1667 — — 0.65 UI p-p 1 Unit Interval P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 123 Electrical characteristics Table 87. Gen 2i/3G receiver AC specifications (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Typical Max Units Notes Deterministic jitter, fC3dB = fBAUD ÷ 10 USATA_TXDJfB/10 — — 0.35 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_TXDJfB/500 — — 0.42 UI p-p 1 Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_TXDJfB/1667 — — 0.35 UI p-p 1 Note: 1. Measured at receiver 2.20.8 SGMII interface Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of the chip, as shown in Figure 46, where CTX is the external (on board) AC-coupled capacitor. Each output pin of the SerDes transmitter differential pair features 50-Ω output impedance. Each input of the SerDes receiver differential pair features 50-Ω on-die termination to XGND. The reference circuit of the SerDes transmitter and receiver is shown in Figure 42. 2.20.8.0.1 SGMII clocking requirements for SD_REF_CLKn and SD_REF_CLKn When operating in SGMII mode, the EC_GTX_CLK125 clock is not required for this port. Instead, a SerDes reference clock is required on SD_REF_CLK[1:3] and SD_REF_CLK[1:3] pins. SerDes banks 1-3 may be used for SerDes SGMII configurations based on the RCW Configuration field SRDS_PRTCL. For more information on these specifications, see Section 2.20.2, “SerDes reference clocks.” 2.20.8.1 SGMII DC electrical characteristics This section discusses the electrical characteristics for the SGMII interface. 2.20.8.1.1 SGMII transmit DC timing specifications This table describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical characteristics for 1.25 GBaud. Transmitter DC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) as shown in Figure 47. Table 88. SGMII DC transmitter electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit Notes Output high voltage VOH — — 1.5 x |VOD|-max mV 1 Output low voltage VOL |VOD|-min/2 — — mV 1 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 124 Freescale Semiconductor Electrical characteristics Table 88. SGMII DC transmitter electrical characteristics (XVDD = 1.5 V or 1.8 V) (continued) For recommended operating conditions, see Table 3. Parameter voltage2, 3, 4 Output differential (XVDD-Typ at 1.5 V and 1.8 V) Output impedance (single-ended) Symbol Min Typ Max Unit Notes |VOD| 320 500.0 725.0 mV B(1-3)TECR(lane)0[AMP_RED] =0b000000 293.8 459.0 665.6 B(1-3)TECR(lane)0[AMP_RED] =0b000010 266.9 417.0 604.7 B(1-3)TECR(lane)0[AMP_RED] =0b000101 240.6 376.0 545.2 B(1-3)TECR(lane)0[AMP_RED] =0b001000 213.1 333.0 482.9 B(1-3)TECR(lane)0[AMP_RED] =0b001100 186.9 292.0 423.4 B(1-3)TECR(lane)0[AMP_RED] =0b001111 160.0 250.0 362.5 B(1-3)TECR(lane)0[AMP_RED] =0b010011 40 50 60 RO Ω — Notes: 1. This does not align to DC-coupled SGMII. 2. |VOD| = |VSD_TXn– VSD_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|. 3. Example amplitude reduction setting for SGMII on SerDes bank 1 lane E: B1TECRE0[AMP_RED] = 0b000010 for an output differential voltage of 459 mV typical. 4. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.5 V or 1.8 V, no common mode offset variation. SerDes transmitter is terminated with 100-Ω differential load between SD_TXn and SD_TXn. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 125 Electrical characteristics This figure shows an example of a 4-wire AC-coupled SGMII serial link connection. 50 Ω SD_TXn CTX SD_RXn 50 Ω Transmitter Receiver 50 Ω SD_TXn SGMII SerDes interface Receiver CTX SD_RXn SD_RXn CTX SD_TXn 50 Ω 50 Ω 50 Ω Transmitter 50 Ω 50 Ω SD_RXn CTX SD_TXn Figure 46. 4-wire, AC-coupled, SGMII serial link connection example This figure shows the SGMII transmitter DC measurement circuit. SGMII SerDes interface 50 Ω SD_TXn 50 Ω Transmitter VOD 50 Ω SD_TXn 50 Ω Figure 47. SGMII transmitter DC measurement circuit P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 126 Freescale Semiconductor Electrical characteristics This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125 GBaud. Table 89. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Output voltage Differential output voltage Symbol Min Typical Max Unit Notes VO –0.40 — 2.30 V 1 VDIFFPP 800 — 1600 mV p-p — Note: 1. Absolute output voltage limit 2.20.8.1.2 SGMII DC receiver electrical characteristics This table lists the SGMII DC receiver electrical characteristics for 1.25 GBaud. Source synchronous clocking is not supported. Clock is recovered from the data. Table 90. SGMII DC receiver electrical characteristics (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Symbol DC Input voltage range Input differential voltage — REIDL_CTL = 001xx VRX_DIFFp-p REIDL_CTL = 100xx Loss of signal threshold Min REIDL_CTL = 001xx VLOS REIDL_CTL = 100xx Receiver differential input impedance ZRX_DIFF Typ Max Unit Notes — 1 1200 mV 2, 4 mV 3, 4 Ω — N/A 100 — 175 — 30 — 100 65 — 175 80 — 120 Notes: 1. Input must be externally AC coupled. 2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage. 3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See Section 2.20.4.4, “PCI Express DC physical layer receiver specifications,” and Section 2.20.4.5.2, “PCI Express AC physical layer receiver specifications,” for further explanation. 4. The REIDL_CTL shown in the table refers to the chip’s SerDes control register B(1-3)GCR(lane)1[REIDL_CTL] bit field. This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud. Table 91. SGMII 2.5x receiver DC timing specifications (XVDD = 1.5 V or 1.8 V) For recommended operating conditions, see Table 3. Parameter Differential input voltage Symbol Min Typical Max Unit Notes VIN 200 900 1600 mV p-p 1 Note: 1. Measured at the receiver. 2.20.8.2 SGMII AC timing specifications This section discusses the AC timing specifications for the SGMII interface. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 127 Electrical characteristics 2.20.8.2.1 SGMII transmit AC timing specifications This table provides the SGMII transmit AC timing specifications. A source synchronous clock is not supported. The AC timing specifications do not include RefClk jitter. Table 92. SGMII transmit AC timing specifications For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit Notes Deterministic jitter JD — — 0.17 UI p-p — Total jitter JT — — 0.35 UI p-p 1 Unit Interval: 1.25 GBaud UI 800 – 100 ppm 800 800 + 100 ppm ps — Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps — CTX 10 — 200 nF 2 AC coupling capacitor Notes: 1. See Figure 44 for single frequency sinusoidal jitter measurements. 2. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs. 2.20.8.2.2 SGMII AC measurement details Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_TXn and SD_TXn) or at the receiver inputs (SD_RXn and SD_RXn) respectively, as depicted in this figure. D+ package pin C = CTX Transmitter silicon + package C = CTX R = 50 Ω D– package pin R = 50 Ω Figure 48. SGMII AC test/measurement load 2.20.8.2.3 SGMII receiver AC timing specification This table provides the SGMII receiver AC timing specifications. The AC timing specifications do not include RefClk jitter. Source synchronous clocking is not supported. Clock is recovered from the data. Table 93. SGMII receive AC timing specifications For recommended operating conditions, see Table 3. Parameter Deterministic jitter tolerance Combined deterministic and random jitter tolerance Total jitter tolerance Symbol Min Typ Max Unit Notes JD 0.37 — — UI p-p 1, 2 JDR 0.55 — — UI p-p 1, 2 JT 0.65 — — UI p-p 1,2, 3 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 128 Freescale Semiconductor Hardware design considerations Table 93. SGMII receive AC timing specifications (continued) For recommended operating conditions, see Table 3. Parameter Symbol Min Typ Max Unit Notes — — BER — — 10-12 Unit Interval: 1.25 GBaud UI 800 – 100 ppm 800 800 + 100 ppm ps 1 Unit Interval: 3.125 GBaud UI 320 – 100 ppm 320 320 + 100 ppm ps 1 Bit error ratio Notes: 1. Measured at receiver 2. See the RapidIOTM 1×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications. 3. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 44. 3 Hardware design considerations 3.1 System clocking This section describes the PLL configuration of the chip. This device includes nine PLLs, as follows: • • • • • There are two selectable core cluster PLLs which generate a core clock from the externally supplied SYSCLK input. Core complex 0–1 can select from either CC1 PLL or CC2 PLL. The frequency ratio between the core cluster PLLs and SYSCLK is selected using the configuration bits as described in Section 3.1.3, “e5500-64 core complex/ FMan to SYSCLK PLL ratio.” The frequency for each core complex 0–1 is selected using the configuration bits as described in Table 97. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 3.1.2, “Platform to SYSCLK PLL ratio.” The DDR block PLL generates the DDR clock from the externally supplied SYSCLK input (asynchronous mode) or from the platform clock (synchronous mode). The frequency ratio is selected using the Memory Controller Complex PLL multiplier/ratio configuration bits as described in Section 3.1.5, “DDR controller PLL ratios.” The FMan PLL generates the FMan clock from the platform PLL when operating synchronously, or from CC3 PLL when operating asynchronously. Described in Section 3.1.8, “Frame Manager (FMan) clock select.” Each of the four SerDes blocks has a PLL which generate a core clock from their respective externally supplied SD_REF_CLKn/SD_REF_CLKn inputs. The frequency ratio is selected using the SerDes PLL ratio configuration bits as described in Section 3.1.6, “Frequency options.” P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 129 Hardware design considerations 3.1.1 Clock ranges This table provides the clocking specifications for the processor core, platform, memory, and local bus. Table 94. Processor clocking specifications Maximum Processor Core Frequency Characteristic 1800 MHz 2000 MHz 2200 MHz Unit Notes Min Max Min Max Min Max Core PLL frequency 1000 1800 1000 2000 1000 2200 MHz 1,4 Core frequency 667 1800 667 2000 667 2200 MHz 4 Platform clock frequency 600 600 600 700 600 800 MHz 1 Memory bus clock frequency 400 600 400 667 400 800 MHz 1,2,5,6 — 75 — 87.5 — 100 MHz 3 300 450 300 600 300 600 MHz 7 Local bus clock frequency FMan frequency Notes: 1. Caution: The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum operating frequencies. 2. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/DDR3L memory bus clock frequency is limited to min = 400 MHz. 3. The local bus clock speed on LCLK[0:1] is determined by the platform clock divided by the local bus ratio programmed in LCRR[CLKDIV]. See the applicable chip reference manual for more information. 4.The core can run at core complex PLL/1 or PLL/2. With a core complex PLL frequency of 1333 MHz, this results in the minimum allowable core frequency of 667MHz for PLL/2. 5. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is the same as the platform frequency. If the desired DDR data rate is higher than the platform frequency, asynchronous mode must be used. 6. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. 7. The minimum frequencies for the FMan to support the specified interfaces are: 300 MHz for a 1G interface, 450 MHz for a 10 G interface, 500 MHz for a 10 G interface with PCD and 600 MHz for a 10 G and two 1 G interfaces. The FMAN PLL frequency range is the same as the Core PLL frequency range. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 130 Freescale Semiconductor Hardware design considerations 3.1.2 Platform to SYSCLK PLL ratio The allowed platform clock to SYSCLK ratios are shown in this table. Note that in synchronous DDR mode, the DDR data rate is the determining factor for selecting the platform bus frequency because the platform frequency must equal the DDR data rate. In asynchronous DDR mode, the memory bus clock frequency is decoupled from the platform bus frequency. Table 95. Platform to SYSCLK PLL ratios 3.1.3 Binary value of SYS_PLL_RAT Platform:SYSCLK ratio 0_0101 5:1 0_0110 6:1 0_0111 7:1 0_1000 8:1 All Others Reserved e5500-64 core complex/ FMan to SYSCLK PLL ratio The clock ratio between SYSCLK and each of the two core complex PLLs and FMan PLL is determined at power up by the binary value of the RCW field CCn_PLL_RAT. (Note: n=1 or 2 are the core complex PLLs, n=3 is the FMan PLL). This table describes the supported ratios. Note that a core complex/ FMan PLL setting targeting 1 GHz and above must set RCW field CCn_PLL_CFG = 0b10, for setting targeting below 1 GHz CCn_PLL_CFG=0b00. This table lists the supported core complex/ FMan to SYSCLK ratios. Table 96. Core complex/ FMan PLL to SYSCLK ratios Binary value of CCn_PLL_RAT Core cluster:SYSCLK ratio 0_1000 8:1 0_1001 9:1 0_1010 10:1 0_1011 11:1 0_1100 12:1 0_1110 14:1 0_1111 15:1 1_0000 16:1 1_0001 17:1 1_0010 18:1 1_0100 20:1 1_0110 22:1 All Others Reserved P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 131 Hardware design considerations 3.1.4 Core complex PLL select The clock frequency of each of the core 0–1 complex is determined by the binary value of the RCW field Cn_PLL_SEL. This table describes the supported ratios for each core complex 0-1, where each individual core complex can select a frequency from the table. Table 97. Core complex [0,1] PLL select Binary value of Cn_PLL_SEL Core cluster ratio 0000 CC1 PLL /1 0001 CC1 PLL /2 0100 CC2 PLL /1 0101 CC2 PLL/2 All Others Reserved Note: If CC2 PLL is used by core0 or core1, then CC2 PLL must be operated at a lower frequency than the CC1 PLL, and its maximum allowed frequency is 80% of the maximum rated frequency of the core at nominal voltage. 3.1.5 DDR controller PLL ratios The dual DDR memory controller complexes can be synchronous with or asynchronous to the platform, depending on configuration. Both DDR controllers operate at the same frequency configuration. Table 98 describes the clock ratio between the DDR memory controller PLLs and the externally supplied SYSCLK input (asynchronous mode) or from the platform clock (synchronous mode). In asynchronous DDR mode, the DDR data rate to SYSCLK ratios supported are listed in Table 98. This ratio is determined by the binary value of the RCW Configuration field MEM_PLL_RAT[10:14]. The corresponding setting for MEM_PLL_CFG[0:1] is listed in Table 99. NOTE The RCW Configuration field DDR_SYNC (bit 184) must be set to b’0 for asynchronous mode, and b’1 for synchronous mode. The RCW Configuration field DDR_RATE (bit 232) must be set to b’0 for asynchronous mode, and b’1 for synchronous mode. The RCW Configuration field DDR_RSV0 (bit 234) must be set to b’0 for all ratios. Table 98. Asynchronous DDR clock ratio Binary value of MEM_PLL_RAT[10:14] DDR:SYSCLK ratio 0_0101 5:1 0_0110 6:1 0_1000 8:1 0_1001 9:1 0_1010 10:1 P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 132 Freescale Semiconductor Hardware design considerations Table 98. Asynchronous DDR clock ratio (continued) Binary value of MEM_PLL_RAT[10:14] DDR:SYSCLK ratio 0_1100 12:1 0_1101 13:1 1_0000 16:1 1_0010 18:1 1_0011 19:1 1_0100 20:1 1_1000 24:1 All Others Reserved Note: 1. RCW[MEM_PLL_CFG] is set dependant on the DDR clock ratio used. See Table 99 for valid setttings of DDR clock ratio and MEM_PLL_CFG. Table 99. Supported DDR ratios and RCW MEM_PLL_CFG settings SYSCLK (MHz) MEM:SYSCLK Ratio 100 125 133.3 150 DDR Rate (MT/s)/MEM_PLL_CFG 1 (Sync Mode) Platform Clock/01 6 Reserved 800/11 900/113 8 800/101 1000/011 1067/01 1200/01 9 900/10 2 1125/012 1200/01 1350/01 10 1000/01 1250/01 1333/01 1500/01 12 1200/11 1500/11 1600/11 Reserved 13 1300/11 Reserved 16 1600/11 Reserved Notes: 1. For MEM SYSYCLK RATIO = 8, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is greater than or equal to 120.9MHz 2. For MEM SYSYCLK RATIO = 9, MEM_PLL_CFG changes from 10 to 01 when SYSCLK is greater than or equal to 107.4MHz 3. Maximum SYSCLK is 161.2MHz when MEM:SYSCLK ratio = 6 In synchronous mode, the DDR data rate to platform clock ratios supported are listed in this table. This ratio is determined by the binary value of the RCW Configuration field MEM_PLL_RAT[10:14]. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 133 Hardware design considerations Table 100. Synchronous DDR clock ratio Binary Value of MEM_PLL_RAT[10:14] DDR:Platform CLK ratio Set MEM_PLL_CFG=01 for platform CLK freq1 0_0001 1:1 >600 MHz All Others Reserved — Note: 1. Set RCW field MEM_PLL_CFG=0b01 3.1.6 Frequency options This section discusses interface frequency options. 3.1.6.1 SYSCLK and platform frequency options This table shows the expected frequency options for SYSCLK and platform frequencies. Table 101. SYSCLK and platform frequency options SYSCLK (MHz) Platform: SYSCLK ratio 100 3.1.6.2 133.3 150 Platform frequency (MHz)1 5:1 1 125 6:1 600 7:1 700 8:1 800 625 666 750 800 750 Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed) Minimum platform frequency requirements for high-speed interfaces The platform clock frequency must be considered for proper operation of high-speed interfaces as described below. For proper PCI Express operation, the platform clock frequency must be greater than or equal to the values shown in these figures. 527 MHz × ( PCI Express link width ) -------------------------------------------------------------------------------16 Figure 49. Gen 1 PEX minimum platform frequency 527 MHz × ( PCI Express link width ) -------------------------------------------------------------------------------8 Figure 50. Gen 2 PEX minimum platform frequency P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 134 Freescale Semiconductor Hardware design considerations Note that “PCI Express link width” in the above equation refers to the negotiated link width as the result of PCI Express link training, which may or may not be the same as the link width POR selection. 3.1.7 SerDes PLL ratio The clock ratio between each of the four SerDes PLLs and their respective externally supplied SD_REF_CLKn/SD_REF_CLKn inputs is determined by the binary value of the RCW Configuration field SRDS_RATIO_Bn as shown in this table. Furthermore, each SerDes lane grouping can be run at a SerDes PLL frequency divider determined by the binary value of the RCW field SRDS_DIV_Bn as shown in Table 103 and Table 104. This table lists the supported SerDes PLL Bank n to SD_REF_CLKn ratios. Table 102. SerDes PLL bank n to SD_REF_CLKn ratios Binary value of SRDS_RATIO_Bn SRDS_PLL_n:SD_REF_CLKn ratio n = 1 (bank 1) n = 2 (bank 2) n = 3 (bank 3) n = 4(bank 4) 001 Reserved 20:1 20:1 Reserved 010 25:1 25:1 25:1 Reserved 011 40:1 40:1 40:1 Reserved 100 50:1 50:1 50:1 Reserved 101 Reserved Reserved 24:1 24:1 110 Reserved Reserved 30:1 30:1 All Others Reserved Reserved Reserved Reserved This table shows the PLL divider support for each pair of lanes on SerDes Bank 1. Table 103. SerDes bank 1 PLL dividers Binary value of SRDS_DIV_B1[0:4] SerDes bank 1 PLL divider 0b0 Divide by 1 off Bank 1 PLL 0b1 Divide by 2 off Bank 1 PLL Note: 1. 1 bit (of 5 total SRDS_DIV_B1 bits) controls each pair of lanes, where the first bit controls configuration of lanes A/B (or 0/1) and the last bit controls configuration of lanes I/J (or 8/9). This table shows the PLL dividers supported for each 4 lane group for SerDes Banks 2, 3, and 4. Table 104. SerDes banks 2, 3, and 4 PLL dividers Binary value of SRDS_DIV_Bn SerDes Bank n PLL divider 0b0 Divide by 1 off Bank n PLL 0b1 Divide by 2 off Bank n PLL Notes: 1. One bit controls all 4 lanes of each bank. 2. n = 2 or 3 (SerDes bank 2 or bank 3) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 135 Hardware design considerations 3.1.8 Frame Manager (FMan) clock select The Frame Managers (FM) can each be synchronous with or asynchronous to the platform, depending on configuration. This table describes the clocking options that may be applied to each FM. The clock selection is determined by the binary value of the RCW Clocking Configuration fields FM1_CLK_SEL and FM2_CLK_SEL. Table 105. Frame Manager (FMan) clock select Binary value of FMn_CLK_SEL FM frequency 0b0 Platform Clock Frequency /2 0b1 FMan PLL Frequency /2 1,2 Notes: 1. For asynchronous mode, max frequency see Table 94. 2. For PLL settings, see Table 96. 3.2 Supply power default setting This chip is capable of supporting multiple power supply levels on its I/O supplies. The I/O voltage select inputs, shown in the following table, properly configure the receivers and drivers of the I/Os associated with the BVDD, CVDD, and LVDD power planes, respectively. WARNING Incorrect voltage select settings can lead to irreversible device damage. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 136 Freescale Semiconductor Hardware design considerations Table 106. I/O voltage selection Signals IO_VSEL[0:4] Default (0_0000) BVDD CVDD LVDD 0_0000 3.3 V 3.3 V 3.3 V 0_0001 3.3 V 3.3 V 2.5 V 0_0011 3.3 V 2.5 V 3.3 V 0_0100 3.3 V 2.5 V 2.5 V 0_0110 3.3 V 1.8 V 3.3 V 0_0111 3.3 V 1.8 V 2.5 V 0_1001 2.5 V 3.3 V 3.3 V 0_1010 2.5 V 3.3 V 2.5 V 0_1100 2.5 V 2.5 V 3.3 V 0_1101 2.5 V 2.5 V 2.5 V 0_1111 2.5 V 1.8 V 3.3 V 1_0000 2.5 V 1.8 V 2.5 V 1_0010 1.8 V 3.3 V 3.3 V 1_0011 1.8 V 3.3 V 2.5 V 1_0101 1.8 V 2.5 V 3.3 V 1_0110 1.8 V 2.5 V 2.5 V 1_1000 1.8 V 1.8 V 3.3 V 1_1001 1.8 V 1.8 V 2.5 V 1_1011 3.3 V 3.3 V 3.3 V 1_1100 3.3 V 3.3 V 3.3 V 1_1101 3.3 V 3.3 V 3.3 V 1_1110 3.3 V 3.3 V 3.3 V 1_1111 3.3 V 3.3 V 3.3 V All Others 3.3 3.3.1 VDD voltage selection Value (binary) Reserved Power supply design PLL power supply filtering Each of the PLLs described in Section 3.1, “System clocking,” is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CCn, AVDD_DDR, AVDD_FM, and AVDD_SRDSn). AVDD_PLAT, AVDD_CCn, AVDD_FM, and AVDD_DDR voltages must be derived directly from the VDD_PL source through a low frequency filter scheme. AVDD_SRDSn voltages must be derived directly from the SVDD source through a low frequency filter scheme. The recommended solution for PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated in Figure 51, one for each of the AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLL’s resonant frequency range from a 500-kHz to 10-MHz range. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 137 Hardware design considerations Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the footprint, without the inductance of vias. Figure 51 shows the PLL power supply filter circuit. Where: R = 5 Ω ± 5% C1 = 10μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH NOTE A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH). Voltage for AVDD is defined at the PLL supply filter and not the pin of AVDD. R VDD_PL C1 C2 GND AVDD_PLAT, AVDD_CCn, AVDD_DDR AVDD_FM Low ESL Surface Mount Capacitors Figure 51. PLL power supply filter circuit The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 52. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed by two 2.2-µF capacitors, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept short, wide, and direct. SVDD 1.0 Ω AVDD_SRDSn 2.2 µF1 2.2 µF1 0.003 µF GND Figure 52. SerDes PLL power supply filter circuit Note the following: • • • • 3.3.2 AVDD_SRDSn should be a filtered version of SVDD. Signals on the SerDes interface are fed from the XVDD power plane. Voltage for AVDD_SRDSn is defined at the PLL supply filter and not the pin of AVDD_SRDSn. An 0805 sized capacitor is recommended for system initial bring-up. XVDD power supply filtering XVDD may be supplied by a linear regulator or sourced by a filtered 1.5 V or 1.8 V voltage source. Systems may design in both options to allow flexibility to address system noise dependencies. An example solution for XVDD filtering, where 1.5 V or 1.8 V is sourced from voltage source (for example, GVDD at 1.5 V when using DDR3, or CVDD at 1.8 V), is illustrated in Figure 53. The component values in this example filter is system P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 138 Freescale Semiconductor Hardware design considerations dependent and are still under characterization, component values may need adjustment based on the system or environment noise. Where: C1 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH C2 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH F1 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite F2 = 120 Ω at 100-MHz 2A 25% 0603 Ferrite Bulk and decoupling capacitors are added, as needed, per power supply design. Bulk and Decoupling Capacitors XVDD F1 1.5 V or 1.8V source C1 C2 F2 GND Figure 53. XVDD power supply filter circuit 3.3.3 USB_VDD_1P0 power supply filtering USB_VDD_1P0 should be sourced by a filtered VDD_PL using a star connection. An example solution for USB_VDD_1P0 filtering, where USB_VDD_1P0 is sourced from VDD_PL, is illustrated in Figure 54. The component values in this example filter is system dependent and are still under characterization, component values may need adjustment based on the system or environment noise. Where: C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M) F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1) Bulk and decoupling capacitors are added, as needed, per power supply design. USB_VDD_1P0 Bulk and Decoupling Capacitors F1 VDD_PL C1 C1 GND Figure 54. USB_VDD_1P0 power supply filter circuit 3.4 Decoupling recommendations Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the chip’s system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, BVDD, OVDD, CVDD, GVDD, and LVDD pin of the chip. These decoupling capacitors should receive their power from separate VDD, BVDD, OVDD, CVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 μF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, BVDD, OVDD, CVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 139 Hardware design considerations have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON). 3.5 SerDes block power supply decoupling recommendations The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. • • • 3.6 First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the chip as close to the supply and ground connections as possible. Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies. Third, between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies. Connection recommendations To ensure reliable operation, it is recommended the user consider the following: • • • • • • • 3.6.1 Connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to VDD, BVDD, CVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, BVDD, CVDD, OVDD, GVDD, LVDD, and GND pins of the chip. The Ethernet controllers 1 and/or 2 input pins may be disabled by setting their respective RCW Configuration field EC1 (bits 360–361), and EC2 (bits 363–364), to 0b11 = No parallel mode Ethernet. When disabled, these inputs do not need to be externally pulled to an appropriate signal level. ECn_GTX_CLK125 is a 125-MHz input clock on the dTSEC ports. If the dTSEC ports are not used for RGMII, the ECn_GTX_CLK125 input can be tied off to GND. If RCW field DMA1=0b1 (RCW bit 384), the DMA1 external interface is not enabled and this pin should be left as a no connect. If RCW field I2C = 0b100 or 0b101 (RCW bits 355–357), the SDHC_WP and SDHC_CD input signals are enabled for external use. If SDHC_WP and SDHC_CD are selected and not used, they must be externally pulled low such that SDHC_WP = 0 (write enabled) and SDHC_CD = 0 (card detected). If RCW field I2C != 0b100 or 0b101, thereby selecting either I2C3 or GPIO functionality, SDHC_WP and SDHC_CD are internally driven such that SDHC_WP = write enabled and SDHC_CD = card detected and the selected I2C3 or GPIO external pin functionality may be used. .For P5021 (SVR = 0x8205_00XX) or P5021E (SVR = 0x820D_00XX), TEST_SEL must be connected to GND. The TMP_DETECT pin is an active low input to the Security Monitor (see Chapter “Secure Boot and Trust Architecture” in the applicable chip reference manual). When using Trust Architecture functionality, external logic must ramp TMP_DETECT with OVDD. If not using Trust Architecture functionality, TMP_DETECT must be tied to OVDD to prevent the input from going low. Legacy JTAG configuration signals Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 56. Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most have asynchronous behavior and spurious assertion gives unpredictable results. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 140 Freescale Semiconductor Hardware design considerations Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors built on Power Architecture technology. The device requires TRST to be asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal device operation. While the TAP controller can be forced to the reset state using only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply tying TRST to PORESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP), which implements the debug interface to the chip. The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert PORESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 56 allows the COP port to independently assert PORESET or TRST, while ensuring that the target can drive PORESET as well. The COP interface has a standard header, shown in Figure 55, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header; so emulator vendors have issued many different pin numbering schemes. Some COP headers are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 55 is common to all known emulators. 3.6.1.1 Termination of unused signals If the JTAG interface and COP header is not used, Freescale recommends the following connections: • • TRST should be tied to PORESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal (PORESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 56. If this is not possible, the isolation resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. No pull-up/pull-down is required for TDI, TMS, or TDO. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 141 Hardware design considerations COP_TDO 1 2 NC COP_TDI 3 4 COP_TRST NC 5 6 COP_VDD_SENSE COP_TCK 7 8 COP_CHKSTP_IN COP_TMS 9 10 NC COP_SRESET 11 12 NC COP_HRESET 13 COP_CHKSTP_OUT 15 KEY No pin 16 GND Figure 55. Legacy COP connector physical pinout P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 142 Freescale Semiconductor Hardware design considerations OVDD HRESET From Target Board Sources (if any) PORESET 13 11 10 kΩ HRESET 6 10 kΩ PORESET1 COP_HRESET 10 kΩ COP_SRESET B 10 kΩ A 5 10 kΩ 10 kΩ 2 3 4 5 6 7 8 9 10 11 12 KEY 13 No pin 15 6 5 COP Header 1 4 15 14 COP_TRST COP_VDD_SENSE2 10 Ω NC COP_CHKSTP_OUT CKSTP_OUT 3 10 kΩ 10 kΩ COP_CHKSTP_IN 8 System logic COP_TMS 16 9 COP Connector Physical Pinout TRST1 1 3 TMS COP_TDO COP_TDI TDO TDI COP_TCK 7 2 TCK NC 10 NC 12 4 Chip 16 Notes: 1. The COP port and target board should be able to independently assert PORESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection. 3. The KEY location (pin 14) is not physically present on the COP header. 4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity. 5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 6. Asserting HRESET causes a hard reset on the device. Figure 56. Legacy JTAG interface connection P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 143 Hardware design considerations 3.6.2 Aurora configuration signals Correct operation of the Aurora interface requires configuration of a group of system control pins as demonstrated in Figure 57 and Figure 58. Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most have asynchronous behavior and spurious assertion gives unpredictable results. Freescale recommends that the Aurora 22 pin duplex connector be designed into the system as shown in Figure 59 or the 70 pin duplex connector be designed into the system as shown in Figure 60. If the Aurora interface is not used, Freescale recommends the legacy COP header be designed into the system as described in Section 3.6.1.1, “Termination of unused signals.” TX0+ 1 2 VIO (VSense) TX0- 3 4 TCK GND 5 6 TMS TX1+ 7 8 TDI TX1- 9 10 TDO GND 11 12 TRST RX0+ 13 14 Vendor I/O 0 RX0- 15 16 Vendor I/O 1 GND 17 18 Vendor I/O 2 RX1+ 19 20 Vendor I/O 3 RX1- 21 22 RESET Figure 57. Aurora 22 pin connector duplex pinout P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 144 Freescale Semiconductor Hardware design considerations TX0+ 1 2 VIO (VSense) TX0- 3 4 TCK GND 5 6 TMS TX1+ 7 8 TDI TX1- 9 10 TDO GND 11 12 TRST RX0+ 13 14 Vendor I/O 0 RX0- 15 16 Vendor I/O 1 GND 17 18 Vendor I/O 2 RX1+ 19 20 Vendor I/O 3 RX1- 21 22 RESET GND 23 24 GND TX2+ 25 26 CLK+ TX2- 27 28 CLK- GND 29 30 GND TX3+ 31 32 Vendor I/O 4 TX3- 33 34 Vendor I/O 5 GND 35 36 GND RX2+ 37 38 N/C RX2- 39 40 N/C GND 41 42 GND RX3+ 43 44 N/C RX3- 45 46 N/C GND 47 48 GND TX4+ 49 50 N/C TX4- 51 52 N/C GND 53 54 GND TX5+ 55 56 N/C TX5- 57 58 N/C GND 59 60 GND TX6+ 61 62 N/C TX6- 63 64 N/C GND 65 66 GND TX7+ 67 68 N/C TX7- 69 70 N/C Figure 58. Aurora 70 pin connector duplex pinout P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 145 Hardware design considerations OVDD From Target Board Sources (if any) 10 kΩ HRESET 4 10 kΩ PORESET1 HRESET PORESET 22 RESET 10 kΩ B 10 kΩ A 3 1 2 3 4 10 kΩ 10 kΩ 5 6 7 8 9 10 12 2 TRST VIO VSense2 1 kΩ COP_TMS 12 13 14 15 16 17 18 19 20 21 22 COP Header 6 11 10 8 TMS COP_TDO COP_TDI TDO TDI COP_TCK 4 20 18 16 Duplex 22 Connector Physical Pinout TRST1 14 1 TCK Vendor I/O 3 N/C Vendor I/O 2 (Aurora Event Out) Vendor I/O 1 (Aurora Event In) Vendor I/O 0 (Aurora HALT) TX0_P TX0_N 3 7 TX1_P 9 13 RX0_P 15 19 21 5 11 17 TX1_N RX0_N RX1_P RX1_N EVT[4] EVT[1] EVT[0] SD_TX09_P SD_TX09_N SD_TX08_P SD_TX08_N SD_RX09_P SD_RX09_N SD_RX08_P SD_RX08_N Chip Notes: 1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection. 3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 4. Asserting HRESET causes a hard reset on the device. HRESET is not used by the Aurora 22 pin connector. Figure 59. Aurora 22 pin connector duplex interface connection P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 146 Freescale Semiconductor Hardware design considerations OVDD From Target Board Sources (if any) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Duplex 70 Connector Physical Pinout 10 kΩ HRESET 4 PORESET 10 kΩ PORESET1 22 25,26,27,28, 31,33,37,38, 39,40,43,44, 45,46,49,50, 51,52,55,56, 57,58,61,62, 63,64,67,68, 69,70 RESET 10 kΩ B 10 kΩ A N/C 3 10 kΩ 10 kΩ TRST TRST1 12 2 VIO VSense2 1 kΩ COP_TMS 6 COP Header 1 HRESET 10 8 TMS COP_TDO TDO COP_TDI TDI COP_TCK TCK 4 34 32 20 18 16 14 1 Vendor I/O 5 (Aurora HRESET) Vendor I/O 4 N/C Vendor I/O 3 N/C Vendor I/O 2 (Aurora Event Out) Vendor I/O 1 (Aurora Event In) Vendor I/O 0 (Aurora HALT) TX0_P TX0_N 3 7 TX1_P 9 13 RX0_P 15 19 21 5,11,17,23,24, 29,30,35,36,41, 42,47,48,53,54, 59,60,65,66 10 kΩ TX1_N RX0_N RX1_P RX1_N EVT[4] EVT[4] EVT[1] EVT[0] SD_TX09_P SD_TX09_N SD_TX08_P SD_TX08_N SD_RX09_P SD_RX09_N SD_RX08_P SD_RX08_N Chip Notes: 1. The Aurora port and target board should be able to independently assert PORESET and TRST to the processor in order to fully control the processor as shown here. 2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection. 3.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed to position B. 4. Asserting HRESET causes a hard reset on the device. Figure 60. Aurora 70 pin connector duplex interface connection P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 147 Hardware design considerations 3.6.3 Guidelines for high-speed interface termination This section provides the guidelines for high-speed interface termination when the SerDes interface is entirely unused or when it is partly unused. 3.6.3.1 SerDes interface entirely unused If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section. The following pins must be left unconnected: • • • • • • SD_TX[19:0] SD_TX[19:0] SD_IMP_CAL_RX SD_IMP_CAL_TX SD1_IMP_CAL_RX SD1_IMP_CAL_TX The following pins must be connected to SGND: • • • • SD_RX[19:0] SD_RX[19:0] SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4 SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4 The RCW configuration fields SRDS_LPD_B1, SRDS_LPD_B2, SRDS_LPD_B3, and SRDS_LPD_B4, all bits must be set to power down all the lanes in each bank. The RCW configuration field SRDS_EN may be cleared to power down the SerDes block for power saving. Setting RCW[SRDS_EN_S1] = 0 powers down the PLLs of banks 1 to 3; RCW[SRDS_EN_S2]=0 powers down the PLL of bank 4. Additionally, software may configure SRDSBnRSTCTL[SDRD] = 1 for the unused banks to power down the SerDes bank PLLs to save power. Note that both SVDD and XVDD must remain powered. 3.6.3.2 SerDes interface partly unused If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as described in this section. The following pins must be left unconnected: • • SD_TX[n] SD_TX[n] The following unused pins must be connected to SGND: • • • • • • SD_RX[n] SD_RX[n] SD_REF_CLK1, SD_REF_CLK1 (If entire SerDes bank 1 unused) SD_REF_CLK2, SD_REF_CLK2 (If entire SerDes bank 2 unused) SD_REF_CLK3, SD_REF_CLK3 (If entire SerDes bank 3 unused) SD_REF_CLK4, SD_REF_CLK4 (If entire SerDes bank 4 unused) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 148 Freescale Semiconductor Hardware design considerations In the RCW configuration field for each bank SRDS_LPD_Bn with unused lanes, the respective bit for each unused lane must be set to power down the lane. 3.6.4 USB controller connections This section details the hardware connections required for the USB controllers. 3.6.4.1 USB divider network This figure shows the required divider network for the VBUS interface for the chip. Additional requirements for the external components are as follows: • • • Both resistors require 0.1% accuracy and a current capability of up to 1 mA. They must both have the same temperature coefficient and accuracy. The zener diode must have a value of 5 V−5.25 V. The 0.6 V diode requires an IF = 10 mA, IR < 500 nA and VF(Max) = 0.8 V. VBUS Charge Pump VBUS (USB Connector) 51.2 kΩ USBn_DRVVBUS USBn_PWRFAULT 0.6 VF 5 VZ USBn_VBUS_CLMP 18.1 kΩ Chip Figure 61. Divider network at VBUS USB1_DRVVBUS and USB1_PWRFAULT are muxed on GPIO[4:5] pins, respectively. USB2_DRVVBUS and USB2_PWRFAULT are muxed on GPIO[6:7] pins, respectively. Setting the RCW[GPIO] bit selects USB functionality on the GPIO pins. 3.6.4.2 USBn_VDD_1P8_DECAP capacitor options The USBn_VDD_1P8_DECAP pins require a capacitor connected to GND. This table list the recommended capacitors for the USBn_VDD_1P8_DECAP signal. Table 107. Recommended capacitor parts for USBn_VDD_1P8_DECAP Manufacturer Part Number Value ESR Package Kemet T494B105(1)025A(2) 1 μF, 25 V 2Ω B(3528) T494B155(1)025A(2) 1.5 μF, 25 V 1.5 Ω — NIC NMC0603X7R106KTRPF 1 μF, 10 V Low ESR 0603 TDK Corporation CERB2CX5R0G105M 1 μF, 4 V 200 m-Ω 0603 Vishay TR3B105(1)035(2)1500 1 μF, 35 V 1.5 Ω B(3528) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 149 Hardware design considerations 3.7 Recommended thermal model Information about Flotherm models of the package or thermal data not available in this document can be obtained from your local Freescale sales office. 3.8 Thermal management information This section provides thermal management information for the flip-chip, plastic-ball, grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment method to the heat sink is illustrated in this figure. The heat sink should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force (45 Newton). Heat sink FC-PBGA package (small lid) Heat sink clip Adhesive or thermal interface material Die lid Die Printed-circuit board Figure 62. Exploded cross-sectional view—FC-PBGA (with lid) package The system board designer can choose between several types of heat sinks to place on the device. There are several commercially-available thermal interfaces to choose from in the industry. Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 3.8.1 Internal package conduction resistance For the package, the intrinsic internal conduction thermal resistance paths are as follows: • • • The die junction-to-case thermal resistance The die junction-to-lid-top thermal resistance The die junction-to-board thermal resistance P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 150 Freescale Semiconductor Package information This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External resistance Radiation Convection Junction to case top Thermal interface material Heat sink Junction to lid top Die/Package Die junction Package/solder balls Internal resistance Printed-circuit board External resistance Radiation Convection (Note the internal versus external package resistance) Figure 63. Package with heat sink mounted to a printed-circuit board The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. 3.8.2 Thermal interface materials A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. The performance of thermal interface materials improves with increasing contact pressure; this performance characteristic chart is generally provided by the thermal interface vendor. The recommended method of mounting heat sinks on the package is by means of a spring clip attachment to the printed-circuit board (see Figure 62). The system board designer can choose among several types of commercially-available thermal interface materials. 4 Package information The following section describes the detailed content and mechanical description of the package. 4.1 Package parameters for the FC-PBGA The package parameters are as provided in the following list. The package type is 37.5 mm × 37.5 mm, 1295 flip-chip, plastic-ball, grid array (FC-PBGA). Package outline Interconnects Ball Pitch Ball Diameter (typical) Solder Balls Module height (typical) 37.5 mm × 37.5 mm 1295 1.0 mm 0.60 mm 96.5% Sn, 3% Ag, 0.5% Cu 2.88 mm to 3.53 mm (Maximum) P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 151 Package information 4.2 Mechanical dimensions of the FC-PBGA This figure shows the mechanical dimensions and bottom surface nomenclature of the chip. Figure 64. Mechanical dimensions of the FC-PBGA with full lid NOTES: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. All dimensions are symmetric across the package center lines unless dimensioned otherwise. 4. Maximum solder ball diameter measured parallel to datum A. 5. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 6. Parallelism measurement shall exclude any effect of mark on top surface of package. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 152 Freescale Semiconductor Security fuse processor 5 Security fuse processor This chip implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure boot. Use of the Trust Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP can be found in the applicable chip reference manual. To program SFP fuses, the user is required to supply 1.5 V to the POVDD pin per Section 2.2, “Power-up sequencing.” POVDD should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles. All other times, connect POVDD to GND. The sequencing requirements for raising and lowering POVDD are shown in Figure 8. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature range per Table 3. Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect POVDD to GND. 6 Ordering information Please contact your local Freescale sales office or regional marketing team for ordering information. 6.1 Part numbering nomenclature This table provides the Freescale QorIQ platform part numbering nomenclature. Table 108. Part Numbering Nomenclature p n Generation Platform P = 45 nm 5 nn n x Number of Cores Derivative Qual Status • 01 = 1 core • 02 = 2 cores • 04 = 4 cores 0–9 t e Temperature Encryption Range P= • S = Std temp Prototype N= (0 °C to Qualified 105 °C • X = Ext temp (–40 °C to 105 °C) n c d r Package Type CPU Speed DDR Speed Die Revision • M= 1200 MHz • N= 1333 MHz • Q= 1600 MHz A = Rev 1.0 B = Rev 2.0 C = Rev 2.1 • E= 1= • T= SEC FC-PBGA 1800 MHz present lead-free • V = • N= 7= 2000 MHz SEC FC-PBGA • 2 = not C4/C5 2200 MHz present lead-free P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 153 Revision history 6.2 Orderable part numbers addressed by this document This table provides the Freescale orderable part numbers addressed by this document for the chip. Contact your Freescale Sales Representative for more information on orderable parts as not all combinations of orderable part numbers are available. Table 109. Orderable part numbers addressed by this document Part number p n P5021 P 5 7 nn n 02 = 2 cores 1 x t P= Prototype N= Qualified • S = Std temp (0 °C to 105 °C • X = Ext temp (–40 °C to 105 °C) e n cd • E = SEC 1= • TM = present FC-PBGA 1800 MHz/ • N = SEC lead-free 1200 MHz not 7= • VN = present FC-PBGA 2000 MHz/ C4/C5 1333 MHz lead-free • 2Q = 2200 MHz/ 1600 MHz r B = Rev 2.0 C = Rev 2.1 Revision history This table provides a revision history for this document. Table 110. Revision history Rev. Number Date 1 05/2014 • • • • 0 12/2013 • Initial public release. Description Includes two SATA controllers Updated block diagram In Table 1 “Pins listed by bus,” updated footnote 42. In Table 9 “VDD_LP power dissipation,” updated footnote 2. P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 154 Freescale Semiconductor How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. CoreNet is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2013-2014 Freescale Semiconductor, Inc. Document Number: P5021 Rev. 1 05/2014