SGTL5000 Evaluation Platform User’s Guide v2.0.0 SGTL5000 Evaluation Platform 1. SCOPE .......................................................................................................................................3 2. GETTING STARTED .................................................................................................................. 4 2.1. Software Installation ...........................................................................................................................4 2.2. USB Driver Installation .......................................................................................................................4 3. BOARD SETUP PROCEDURE .................................................................................................9 3.1. Jumper Options ..................................................................................................................................9 3.2. Board Connections ............................................................................................................................9 3.3. Example Setup .................................................................................................................................10 4. HARDWARE ............................................................................................................................11 4.1. Evaluation Board Features ..............................................................................................................11 4.2. Evaluation Board Layout ..................................................................................................................11 4.3. Power linear regulators ....................................................................................................................12 5. SOFTWARE .............................................................................................................................13 5.1. Initialization ......................................................................................................................................13 5.2. Routing .............................................................................................................................................14 5.3. I2S ....................................................................................................................................................15 5.4. Inputs ...............................................................................................................................................16 5.5. Outputs ............................................................................................................................................17 5.6. Digital Audio Processing (DAP) .......................................................................................................18 5.6.1. DAP Mixer ..........................................................................................................................18 5.6.2. SGTL5000 Surround ..........................................................................................................18 5.6.3. SGTL5000 Bass Enhance ..................................................................................................18 5.6.4. PEQ/GEQ/Tone Control .....................................................................................................18 5.6.5. AVC ....................................................................................................................................19 5.7. Direct Register Access .....................................................................................................................19 2 Freescale Semiconductor Inc. SGTL5000 Evaluation Platform 1. SCOPE The evaluation platform is designed to allow the user to test the features and performance of the SGTL5000 audio codec. The evaluation board can be used as a demo or development platform. SGTL5000 is an audio codec that utilizes two analog inputs (LINEIN and MIC IN), two analog outputs (LINEOUT and HPOUT), one digital input (I2S IN) and one digital output (I2S OUT). Communication to the chip is performed through either I2C or SPI. SGTL5000 comes in 2 packages: 3x3mm 20-pin QFN, and 5x5mm 32-pin QFN. The information in this document applies to both packages. Freescale Semiconductor Inc. 3 SGTL5000 Evaluation Platform 2. GETTING STARTED 2.1. 2.2. 4 Software Installation • Copy the following from the CD to any location on your hard drive: • StereoCodecControlSoftware.exe • FTC Drivers folder • Copy SGTL5000_CA1_Init_Script.txt from the CD to C:\ drive (directly to C:). USB Driver Installation • Make sure that the evaluation board jumpers are configured correctly (refer to section 3.1). The jumpers are pre-configured before shipping so that the board is ready to be used. • Connect the USB cable from the PC to the board. • Connect the 5V power supply to the board and turn on the board. • Windows will detect the new device and automatically launch the “Add Hardware Wizard” • Select option “Install from a list or Specific Location (Advanced)” and click Next. Freescale Semiconductor Inc. SGTL5000 Evaluation Platform • Select option “Search for the best driver in these locations” and select “Don’t Search. I will choose the driver to install”. Click on Next. Freescale Semiconductor Inc. 5 SGTL5000 Evaluation Platform 6 • Select “Universal Serial Bus Controllers” from the list. • Select on “Have Disk”. Freescale Semiconductor Inc. SGTL5000 Evaluation Platform • Browse to “FTC Drivers” folder unzipped from the SGTV58XXControl.zip and select “ftd2xxx.inf” file. Click “Open”. Click “Next” in the next window. • Windows will now detect the device FT2232C Channel A. Windows logo testing window will pop-up. Click Continue Anyway. Freescale Semiconductor Inc. 7 SGTL5000 Evaluation Platform 8 • FT2232C Channel B will be detected next. Windows logo testing window will pop-up. Click Continue Anyway. • Now your eval board is ready to be used. Freescale Semiconductor Inc. SGTL5000 Evaluation Platform 3. BOARD SETUP PROCEDURE 3.1. Jumper Options SGTL5000 Evaluation Board provides users with various stuffing options in order to use different features of the board. • External power (JP3, JP4, JP5): Jumper pins 1, 2 to use external voltage source using banana plugs for each rail. Jumper pins 2, 3 to use internal regulators • MCLK Source (JP2): Jumper pins 1, 4 to use onboard oscillator. Jumper pins 2, 5 to use external MCLK via SMB connector (J10). Jumper pins 3, 6 to use MCLK provided by an Audio Precision PSIA via I2S Headre (J2) • MIC select (JP1): Jumper pins 1, 2 for onboard microphone (X1). Jumper pins 2, 3 to use microphone jack (J6) 3.2. Board Connections The following connection may be used as a guide. USB to PC AP Headers 5V SGTL5000 Evaluation Board connection Diagram Audio out VDDD SGTL5000 VDDA Audio in VDDIO MCLK Freescale Semiconductor Inc. GND 9 SGTL5000 Evaluation Platform 3.3. 10 Example Setup • Connect power and input/outputs according to the aforementioned connections jumper settings and connection diagram • Open Audio Precision software • Set up digital i/o for PSIA, and configure for I2S frame clock and bit clock output, and MCLK out • Open SGTL5000 control software • Select I2C connection type, hit Connect • Select 256*Fs, 48kHz, Slave mode. Hit initialize • Configure an I2S input to DAC and I2S outputs • Select Program Route • Unmute DAC output • Perform any necessary testing Freescale Semiconductor Inc. SGTL5000 Evaluation Platform 4. HARDWARE 4.1. 4.2. Evaluation Board Features • SGTL5000 Audio Codec • LINEIN RCA analog input jack • LINEOUT RCA analog output jack • Selectable mini-jack or onboard microphone input • Stereo headphone mini-jack analog output, with optional capless design cir cuitry • Two-row headers for buffered I2S digital input/output • Support for onboard or external MCLK source • USB to I2C/SPI communication port • 5V input voltage through either internal LDO regulators, or external individual supplies Evaluation Board Layout The following shows the physical layout and placement of components of the SGTL5000 evaluation board. (Please note that the picture shown below is for SGTL5000 32QFN evaluation board. SGTL5000 20QFN evaluation board is blue in color. The information in this document applies to both SGTL5000 packages) Figure 1. SGTL5000 Evaluation Board with Components Identified Freescale Semiconductor Inc. 11 SGTL5000 Evaluation Platform 4.3. • Inputs include one RCA connector for LINEIN, and one mono microphone input 3.5mm mini-jack for external MIC. The board also has anan be either 3.5mm mini-jack or on-board microphone. • Outputs include one RCA connector for LINEOUT, and one stereo 3.5mm mini-jack for HP OUT. • AP I2S headers are a 2x8 pin array for Audio Precision PSIA connectors. These headers are provided to connect Audio Precision’s frame clk, bit clk, master clk and data to the chip. • USB jack to connect the board to the PC via a USB cable. The software sends commands to the board via USB and the FTDI chip on the board converts it to I2C/SPI to talk to the chip. The FTDI chip is powered by the USB and a green LED indicates that. • 5V power is a 2.1mm positive-center connector for the 5V wall-wart supply provided with the kit. When the power switch is turned on, a blue LED indicates that the board is powered on. • Individual external power can be supplied to the board via either bare wires, or banana-type connectors • MCLK is supplied via I2S header, onboard oscillator, or SMB connector. Power linear regulators If only a 5V board power supply is connected, the supplies for VDDD, VDDA, and VDDIO must be switched to use the onboard regulators. These regulators are Analog Devices ADP1712AUJZ. By default, the regulator outputs are as follows: Power Rail Output Voltage (V) VDDD 1.8 VDDA 1.8 VDDIO 3.3 Table 1. Linear regulator output voltages The output for each regulator is determined by the formula VOUT = 0.8 V (1 + R1/R2) where: R1 is the resistor from OUT to ADJ. R2 is the resistor from ADJ to GND. 12 Freescale Semiconductor Inc. SGTL5000 Evaluation Platform 5. SOFTWARE The SGTL5000 Control Software allows a user access to all of the features within SGTL5000. 5.1. Initialization • From the Initialization tab, the user selects the communication protocol to interface with the SGTL5000 chip - I2C or Ethernet. Click ‘Connect’ to connect to the board. • Click on ‘Chip Initialize’. This will power up the analog and digital blocks, setup the default clocks (as shown in the clocks section of the Initialization page), and unmute the ADC and outputs. • Clock configuration can be done on this page as well. The ‘Chip Initialize’ already sets it up in the default state. So additional configuraiton is required unless the parameters need to be changed. From the SYS_MCLK menu, PLL can be chosen if needed. If used, the PLL must be powered up by direct write under Direct Register Access page and the INT_DIVISOR/FRAC_DIVISOR divisors need to be programmed correctly. Please refer to the datasheet on how to Freescale Semiconductor Inc. 13 SGTL5000 Evaluation Platform configure the PLL. Please note that the divisors must be calculated based on the external MCLK rate. 5.2. Routing From the Routing page, various signal paths are set from input to output. • Inputs include: LINEIN, MIC, I2S_DIN • LINEIN or MICIN may be configured through the ADC or directly pass-through to HP_OUT. • Outputs include: LINEOUT, Headphone (HP), I2S_DOUT • Routes may or may not include the use of the Digital Audio Processor (DAP). Please note that when DAP is routed, it must also be enabled under the Digital Audio Processor page. Otherwise, no audio will pass through DAP. Routes may also be edited once programmed. To do so, select the route that is to be edited, press the "Edit Route" button, make the route changes, and select "Program Route." 14 Freescale Semiconductor Inc. SGTL5000 Evaluation Platform 5.3. I2S From the I2S tab, specifics to the digital I2S communication are programmed. The SCLK frequency, word length, and data alignment are options that are programmable. Freescale Semiconductor Inc. 15 SGTL5000 Evaluation Platform 5.4. 16 Inputs • The input screen has the volume and gain controls for the two analog inputs Line In and Microphone. • The software configures the left and right volume together to the same value. When ‘Independent L/R Volume Control’ is checked, left and right volumes can be controlled indepndently. The left and right channels also have independent mutes. • The microphone has two sliders for Gain and Bias, the latter is dependent on on-board settings of the Mic Bias circuitry. Freescale Semiconductor Inc. SGTL5000 Evaluation Platform 5.5. Outputs • The output tab has controls for DAC digital volume, HP OUT analog volume/ mute and LINEOUT mute/unmute. Freescale Semiconductor Inc. 17 SGTL5000 Evaluation Platform 5.6. Digital Audio Processing (DAP) DAP Mixer 5.6.1. SGTL5000 Surround SGTL5000 Bass PEQ/GEQ Tone Control AWC DAP Mixer The DAP Mixer allows a second audio signal to be mixed in with the main audio stream. Both can be mixed as a percentage of total signal. The Mixer can be configured to route from the ADC or I2S_DIN. 5.6.2. SGTL5000 Surround SGTL5000 Surround widens the soundscape, and has width settings from 1-7, for varying amounts of processing. 5.6.3. SGTL5000Bass Enhance SGTL5000 Bass Enhance boosts bass levels. Programmable settings include the low pass filter cutoff frequency, high pass filter cutoff frequency, Bass Level, Left/Right level, and a multiplier that can dramatically increase the effect. 5.6.4. PEQ/GEQ/Tone Control SGTL5000 includes a 7-band parametric equalizer (PEQ) that can be programmed through the software's presets. Custom PEQ curves can be created, as well. The 5-band graphic equalizer (GEQ) is fully programmable, with bands of 115Hz, 330Hz, 990Hz, 3000Hz, and 9900Hz. Each can be adjusted up to +/-12dB. 18 Freescale Semiconductor Inc. SGTL5000 Evaluation Platform Tone Control allows the user to adjust the Bass and Treble levels, up to +/-12dB. 5.6.5. AVC The Automatic Volume Control (AVC) helps prevent clipping or speaker damage by allowing the user to set a threshold from which SGTL5000 will attenuate or gain the signal to reach the specified value. Attack and decay rates are fully programmable. 5.7. Direct Register Access • From the Direct Register Access tab, users can read and write directly to registers without the use of the GUI. • The Register Write Monitor shows all read and written-to registers from the current session. Scripts can be saved and run from here as well. • Support for SPI register writes is on this tab. Freescale Semiconductor Inc. 19 5 4 3 Block Diagram I2C/SPI Mode Select I2C ADR0 Select 2 1 MCLK Source D D Communication PG.6 USB to I2C/SPI I2S Signals PG.7 I2S0 Interface Analog Inputs PG.4 Digital Header Line-In / Microphone C SGTL5000 PG. 3 Analog Outputs PG.5 AP PSIA HEADER Headphone C Master/Slave Lineout Power PG. 8 B B External Power Jacks Onboard Power LDO External 5VDC in 6501 William Cannon Drive West Austin, TX 78735-8598 ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE A A Page Title: Block Diagram - 32-Pin QFN, 5x5 Package 5 4 3 Size A Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 2 Sheet 1 of 1 9 5 4 3 Feature Set D 2 1 Revision: A) 1. JP1 to select SYS_MCLK 2. JP2 to select on-board MIC or external MIC_IN 3. JP3~JP5 to setect between external and on-board power supply - Initial Release D C C B B 6501 William Cannon Drive West Austin, TX 78735-8598 ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE A A Page Title: Feature Set 5 4 3 Size A Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 2 Sheet 2 of 1 9 5 4 3 2 1 D D VDDD C47 is used when connecting an external VDDD, otherwise it is a nopop C42 0.1uF 7,9 CTRL_ADR0_CS 6,9 CTRL_MODE C HP_R 5 HP_VGND 5 HP_L VDDA GND HP_R GND HP_VGND VDDA HP_L AGND NC NC VAG LINEOUT_R LINEOUT_L LINEIN_R LINEIN_L MIC MIC_BIAS 5 1 2 3 4 5 6 7 8 C43 SGTL5000_32QFN 9 10 11 12 13 14 15 16 0.1uF CTRL_MODE CTRL_ADR0_CS VDDD CTRL_CLK NC CTRL_DATA I2S_DIN I2S_DOUT 32 31 30 29 28 27 26 25 U1 C46 CTRL_CLK CTRL_DATA 7 6,7 I2S_DIN I2S_DOUT I2S_SCLK I2S_LRCLK 7 7 7 7 SYS_MCLK 9 C I2S_SCLK I2S_LRCLK NC SYS_MCLK VDDIO NC CPFILT NC GND 24 23 22 21 20 19 18 17 VDDIO TP28 C45 33 C44 0.1uF 0.1uF NOPOP Solder Pad to GND TP27 MIC_BIAS MIC 0.1uF B C34 Notes: 5 - Star the ground pins of the chip, the ground connection for the VAG cap, and the grounds for the line-in’s, line-out’s, HP, and mic to a single point and then to the ground plane. - Use short and fat traces for the HP_VGND TP39 TP41 1uF B C29 1uF LINE_OUT_R TP40 C38 5 4 4 LINE_IN_L 4 LINE_IN_R 4 TP42 1uF C27 LINE_OUT_L 1uF 6501 William Cannon Drive West Austin, TX 78735-8598 A A ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE Page Title: SGTL5000 5 4 3 2 Size B Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 Sheet 1 3 of 9 5 4 Line-In TP25 3 LINE_IN_R 3 LINE_IN_L 2 1 RCJ-2223 RCA1X2 D 2 D 3 3 1 J8 TP30 MIC C Microphone input with MIC_BIAS derived internally. C X1 1 2 TP22 JP1 C25 3 1 2 3 0.1uF MIC MIC 1 2 3 HEADER 3X1 3 MIC_BIAS R30 C24 B R39 2.2k 0 NOPOP 1uF 1 2 R33 0 3 5 4 2 1 J6 B Audio Jack 3.5mm Audio Jack 6501 William Cannon Drive West Austin, TX 78735-8598 ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE A A Page Title: Analog Inputs 5 4 3 Size A Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 2 Sheet 4 of 1 9 5 4 3 Line-Out LINE_OUT_R RCJ-2223 RCA1X2 2 1 3 2 TP32 LINE_OUT_L 3 1 3 D D TP35 J11 R48 100k C37 220pF R46 100k C36 220pF Headphone Out TP19 R5 C J5 3 5 4 2 1 R56 100 R4 0 NOPOP R12 100 NOPOP NOPOP Audio Jack HP_JACK_GROUND B R19 R57 100 0 NOPOP R14 100 NOPOP C HP_R 3 HP_L 3 C7 220uF NOPOP R20 Headphone output with population option for CAPLESS design with virtual ground or output using series CAP and board ground. Test filters shown on output. 100 Ohm resistors to HP_JACK_GROUND can be used to minimize input to output coupling without power applied. 0 TP20 0 C11 220uF NOPOP NOPOP HP_JACK_GROUND R11 0 HP_JACK_GROUND HP_VGND 3 R3 0 NOPOP B 6501 William Cannon Drive West Austin, TX 78735-8598 A A ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE Page Title: Analog Inputs 5 4 3 2 Size B Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 Sheet 1 5 of 9 5 4 3 2 1 USB Jack 2A/220 USBDM USBDP 3V3_USB D R21 470 USB_5V R8 27 C5 C4 8 7 1.5k 47pF C17 NOPOP 27pF R17 1 47pF NOPOP R2 4.7K Y1 5 43 44 14 31 USBDM USBDP RSTOUT# XTIN XTOUT 6MHz XTAL C14 27pF FTDI_RST# 4 RESET# U5 47 10k ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 PWREN# R13 2.2k 45 R7 TEST 0.1uF BCBUS0 BCBUS1 BCBUS2 BCBUS3 SI/WUB EECS EESK EEDATA GND GND GND GND 48 1 2 AGND AT93C56A EECS EESK EEDATA R29 4.7K R28 4.7K 24 23 22 21 20 19 17 16 R26 R24 R23 27 27 0 R22 27 FTDI_CLK FTDI_DATA CTRL_DATA FTDI_CS 7 7 3,7 7 VDDIO_3_3 15 13 12 11 10 C 3V3_USB R16 40 39 38 37 36 35 33 32 10k R25 4.7K R34 4.7K MASTER SLAVE CTRL_MODE BUF_DIR 7 7 3,9 7 R27 4.7K 30 29 28 27 26 B R31 10k 41 FT2232D 9 18 25 34 B 1 2 3 4 VCC CS NC SK ORG DIN GND DOUT 0.1uF BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 3V3_USB 8 7 6 5 C21 ACBUS0 ACBUS1 ACBUS2 ACBUS3 SI/WUA 2 GREEN LED 27 R9 D2 3V3OUT C18 U6 VCCIOA VCCIOB 6 VCC 3V3_USB 0.1 uF 42 C19 0.1uF C6 10uF 3 C16 0.1uF VCC 6 C3 0.1uF C91 C C20 0.1uF USB_5V_L 46 6 D L1 AVCC 5 5 USB_5V J3 USB-TYPE-B 1 VBUS 2 D- 3 D+ 4 GND 3V3_USB FTDI Reset 6501 William Cannon Drive West Austin, TX 78735-8598 U2 ICAP Classification: Drawing Title: C9 FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE 0.1uF A Page Title: 3 A RST GND VCC FTDI_RST# 1 2 MCP100 Communication 5 4 3 Size A Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 2 Sheet 6 of 1 9 5 4 Digital Header 3 AP PSIA Header Jumper settings 2 - I2C_CLK 4 - I2C_DATA 8 - I2S_DOUT 10 - I2S_LRCLK 12 - I2S_SCLK 14 - I2S_DIN 16 - I2S_MCLK TP9 TP8 TP7 TP13TP5 TP4 TP17TP10 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 TP3 J2 1 3 5 7 9 11 13 15 J1 2 4 6 8 10 12 14 16 1 TP16 TP15 TP2 D 1 3 5 7 9 11 13 15 2 CTRL_CLK 3 CTRL_DATA 3,6 CTRL_ADR0_CS 3,9 I2S_DOUT 3 I2S_LRCLK 3 I2S_SCLK 3 I2S_DIN 3 I2S_MCLK 9 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 Jumper settings 2 - AP_TX_DATA 3 4 - AP_TX_LRCLK 6 - AP_TX_SCLK 8 - AP_TX_MCLK 9 10 - AP_RX_DATA 3 12 - AP_RX_LRCLK 14 - AP_RX_SCLK 16 - AP_RX_MCLK 9 I2S_DIN AP_TX_LRCLK AP_TX_SCLK I2S_MCLK I2S_DOUT AP_RX_LRCLK AP_RX_SCLK I2S_MCLK D HEADER_8X2 TP6 TP12 TP11 TP14 HEADER_8X2 Master/Slave modes AP PSIA level must match VDDIO_3_3 setting C C VDDIO_3_3 VDDIO_3_3 VDDIO_3_3 VDDIO_3_3 VDDIO_3_3 1 3 AP_RX_LRCLK 2 I2S_LRCLK 4 6 FTDI_DATA 6 8 AP_RX_SCLK 6 FTDI_CLK AP_RX_SCLK 9 OSC_MCLK 9 6 BUF_DIR 13 8 6 FTDI_CS 12 13 11 12 I2S_SCLK NOPOP U4 SN74LVC125APWR 11 7 7 12 R55 0 R54 0 AP_RX_SCLK 5 AP_TX_SCLK CTRL_DATA 3,6 6 CTRL_CLK 3 8 OSC_MCLK_BUF NOPOP U3 SN74LVC125APWR 11 7 13 3 10 9 I2S_SCLK 2 AP_TX_LRCLK 10 9 C41 0.1uF 1 6 AP_RX_LRCLK R32 4.7K 4 5 I2S_LRCLK 10 AP_TX_SCLK 3 C13 0.1uF 4 5 B C12 0.1uF 1 2 AP_TX_LRCLK VDDIO_3_3 MASTER 14 6 14 SLAVE 14 6 CTRL_ADR0_CS B 9 3,9 U8 SN74LVC125APWR I2S_SCLK I2S_LRCLK 6501 William Cannon Drive West Austin, TX 78735-8598 AP_RX_LRCLK A A ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE Page Title: I2S Signals 5 4 3 2 Size B Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 Sheet 1 7 of 9 5 4 3 EXTERNAL POWER: +5VDC TP18 1 6 5 4 2 R10 1k 15A D1 D3 6 5 4 VDDA TP34 C35 1uF 35V C1 47uF 35V + TP33 1 2 3 R47 Select either External Power by tying Pins 1 and 2 together, or Internal Power by tying Pins 2 and 3 together on JP3, 4, 5. R1 5.1k JP4 1 3 2 1 XF1 J4 D EXT_POWER_JACK +5V FUSE 4amp BLUE LED 2.1mm Power Jack 1 VCC_IN 1 J9 POWER_JACK 3 2 1 F1 SW1 2 1 2 3 0 D HEADER 3X1 C32 47uF 10V + RED LED VDDA_1_8 Replace Fuse LED 3 2 IN OUT GND ADJ 4 R45 10k ADP1712AUJZ-R7 IN 5 OUT VDDIO TP37 EN 2 C33 2.2uF VDDD_1_8 U10 1 3 EN C2 2.2uF +5V 5 1 VDDA_1_8 U11 1 GND ADJ C23 2.2uF R42 10k 4 TP36 1 2 3 R51 ADP1712AUJZ-R7 1 2 3 0 C28 2.2uF HEADER 3X1 C C39 47uF 10V + R44 8k JP5 1 +5V J12 POWER_JACK LDO Regulator for 1.8V VDDD(1.2 - 2.0V) LDO Regulator for 1.8V VDDA(1.62 - 3.6V) R41 8k C VDDIO_3_3 1 J7 POWER_JACK +5V VDDIO_3_3 U12 1 3 2 B C31 2.2uF IN OUT +5V 5 1 3 EN GND ADJ 4 R50 10k 2 C40 2.2uF ADP1712AUJZ-R7 VDD_OSC U13 IN OUT 5 GND ADJ C48 2.2uF To use internal regulator, jumper pins 1, 2, and do NOT supply power to J13 1 2 3 HEADER 3X1 C30 47uF 10V VDDD_1_8 B C47 2.2uF ADP1712AUJZ-R7 J13 POWER_JACK TP1 R53 3.2k TP31 TP23 TP24 TP38 1 1 R49 3.2k 1 2 3 0 R52 10k 4 TP26 R43 + EN JP3 1 VDDD TP29 LDO Regulator for OSC (3.3V Constant) LDO Regulator for 3.3V VDDIO(1.62 - 3.6V) SCREW1 SCREW2 STANDOFF1 H708-ND SCREW3 H708-ND SCREW4 2210K-ND STANDOFF2 H708-ND SCREW5 H708-ND SCREW6 2210K-ND STANDOFF3 H708-ND SCREW7 H708-ND SCREW8 2210K-ND STANDOFF4 MH1 2.9mmIDx5mmOD MH2 2.9mmIDx5mmOD MH3 2.9mmIDx5mmOD MH4 2.9mmIDx5mmOD 6501 William Cannon Drive West Austin, TX 78735-8598 A ICAP Classification: Drawing Title: H708-ND 5 FIUO: X PUBI: ___ Page Title: Power GND H708-ND FCP: ___ KITSGTL5000EVBE 1 A 1 1 1 A A A A Size B Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 2210K-ND 4 3 2 Sheet 1 8 of 9 5 4 3 2 1 1 e Kc Lr u Co Ms 1 2 U7 D 4 NC VCC VDD_OSC C26 0.1uF D R58 0 NOPOP 2 3 GND OUT 2 1 OSC_MCLK_BUF 7 Jumpers to select SYS_MCLK Default Pin1&Pin2 connected CON SMB 1 EXT_MCLK GND GND 1 1 3 5 JP2 1 3 5 2 4 6 2 4 6 SYS_MCLK 3 HEADER 3X2 C 4 5 GND GND 2 3 C 7 R40 30 12.288M J10 OSC_MCLK 7 I2S_MCLK VDDIO_3_3 VDDIO_3_3 B When CTRL_MODE = GND (I2C), CTRL_ADR0 can be pulled up or down to set the LSB of the I2C address. When CTRL_MODE = VDDIO (SPI), CTRIL_ADR0_CS is the SPI chip select. R37 4.7K NOPOP R36 0 NOPOP B CTRL_MODE 3,6 CTRL_ADR0_CS 3,7 R38 4.7K R35 0 6501 William Cannon Drive West Austin, TX 78735-8598 ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ KITSGTL5000EVBE A A Page Title: Clocks, Addressing 5 4 3 Size A Document Number Date: Thursday, April 05, 2012 Rev C SCH-26510 PDF: SPF-26510 2 Sheet 9 of 1 9