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STEVAL-ISA113V1
Wide range single-output demonstration board based on the
VIPER06HS
Data brief
Features
■
Universal input mains range:
– input voltage 90 - 265 VAC
– frequency 45 - 65 Hz
■
Single-output voltage: 12 V at 0.35 A
continuous operation
■
Standby mains consumption: < 30 mW at
230 VAC
■
Average efficiency: > 74%
■
Fully protected against faults (overload,
feedback disconnection and overheating)
■
EMI: according to EN55022-Class-B
■
RoHS compliant
STEVAL-ISA113V1
Description
The STEVAL-ISA113V1 demonstration board is a
12 V-0.35 A power supply set in non-isolated
flyback topology using the new VIPER06HS
offline high-voltage converter by
STMicroelectronics.
The features of the device include an 800 V
avalanche rugged power section, PWM operation
at 115 kHz with frequency jittering for lower EMI,
current limiting with adjustable set point, onboard
soft-start, a safe auto-restart after a fault condition
and a low standby power.
The protection features available include a
thermal shutdown with hysteresis, delayed
overload protection, and open loop failure
protection.
January 2013
Doc ID 024140 Rev 1
For further information contact your local STMicroelectronics sales office.
1/11
www.st.com
11
Adapter features
1
STEVAL-ISA113V1
Adapter features
The electrical specifications are given in Table 1, the schematic in Figure 1, and the bill of
material in Table 2.
Table 1.
Electrical specifications
Parameter
Symbol
Value
VIN
[90 VAC; 265 VAC]
Output voltage
VOUT
12 V
Max. output current
IOUT
0.35 A
Precision of output regulation
ΔVOUT_LF
±5%
High frequency output voltage ripple
ΔVOUT_HF
50 mV
Max. ambient operating temperature
TAMB
60 ° C
Input voltage range
Table 2.
Ref.
Part
Description
Cin1
2.2 µF, 400 V NHG series electrolytic
capacitor
Cin2
4.7 µF, 400 V AX series electrolytic capacitor
Package
1 µF, 50 V electrolytic capacitor
1206
Cfilt1
100 nF, 50 V ceramic capacitor
0805
Cc
10 nF, 50 V ceramic capacitor
1206
Cp
1 nF, 50 V ceramic capacitor
1206
Cfb
1 nF, 50 V ceramic capacitor
0805
Cout
330 µF, 16 V ZL series ultra-low ESR
electrolytic cap.
Murata
Not mounted
D0
MB6S
D2
STPS2H100
Daux
1N4148W
R0
Manufacturer
Saxon
CVDD
Cfilt2
2/11
Bill of material
600 V, 1 A diode bridge
Rubycon
TO-269AA
Vishay
100 V, 2 A power Schottky rectifier
SMA
ST
Surface mount fast switching diode
SOD-123
Zetex
4.7 Ω 3/4 W resistor
RLIM
15 kΩ 5% 1/4 W resistor
0805
Rc
47 kΩ 5% 1/4 W resistor
0805
RfbH1
33 kΩ 1% 1/4 W resistor
0805
RfbH2
0Ω
1206
RfbL1
12 kΩ 1% 1/4 W resistor
1206
RfbL2
0.47 kΩ 1% 1/4 W resistor
0805
Doc ID 024140 Rev 1
STEVAL-ISA113V1
Adapter features
Table 2.
Bill of material (continued)
Ref.
Part
IC1
VIPer06HS
Offline high-voltage PWM controller
T1
1921.0040
Transformer
Lin
Description
B82144A2105J 1 mH inductor LBC series
Package
Manufacturer
SSO-10
ST
Magnetica
Epcos
The transformer core is a standard E13. The output voltage value is set in a simple way
through the RfbH-RfbL voltage divider between the output terminal and the FB pin,
according to the following formula:
Equation 1
⎛
RfbH ⎞
⎟
V OUT = 3 .3V ⋅ ⎜⎜1 +
RfbL ⎟⎠
⎝
In the schematic, RfbH has been split into RfbH1 and RfbH2; and RfbL into RfbL1 and
RfbL2 in order to allow a better tuning of the output voltage value.
If the jumper J1 is not selected, the IC is biased through the internal HV-startup current
generator (“self-biasing”).
If low standby consumption and good efficiency performance are required, the HV-startup
current generator must be excluded. This can be done selecting the jumper J1, which
connects the output terminal to the VDD pin through a small signal diode. The IC biasing
through the output is referred to as “external biasing”.
Doc ID 024140 Rev 1
3/11
R0
4/11
-
D0
+
Cin1
+
Cin2 +
Lin
Doc ID 024140 Rev 1
CVDD
+
GND
Cf ilt1
VDD
Cf b
RLIM
LIM
VIper06SH
FB
Cp
COMP
DRAIN DRAIN DRAIN DRAIN DRAIN
J1
Cc
Rc
T1
+
Daux
Cout
D2
Cf ilt2
Rf bL2
Rf bL1
Rf bH2
Rf bH1
-
VOUT
Figure 1.
AC IN
AC IN
Adapter features
STEVAL-ISA113V1
Application schematic
AM13328v1
STEVAL-ISA113V1
Measurements
Measurements
Figure 2.
Line regulation at different loads:
IC externally biased (J1 selected)
Figure 3.
12.2
12.2
12.1
12.1
VOUT [V]
VOUT [V]
2
12
0
11.9
25%
50%
11.8
75%
Line regulation at different loads:
IC self-biased (J1 not selected)
12
90
11.9
115
11.8
230
265
100%
11.7
11.7
80
105
130
155
180
205
230
VIN[V AC ]
Efficiency vs. VIN IC externally
biased (J1 selected)
Figure 5.
85
85
80
80
75
75
70
70
65
25%
60
0.1
0.15
0.2 0.25
IOUT [A]
0.3
0.35
0.4
AM11691v1
Efficiency vs. VIN IC self-biased
(J1 not selected)
65
25%
50%
60
75%
55
0.05
AM11688v1
eff [%]
eff [%]
Figure 4.
0
255
50%
75%
55
100%
100%
50
50
80
110
140
170
VIN[V AC ]
Figure 6.
200
230
260
80
110
140
170
200
230
260
VIN[V AC ]
AM11696v1
Efficiency at different input
voltages: IC externally biased
(J1 selected)
AM11537v1
Figure 7.
AM11632v1
Doc ID 024140 Rev 1
Efficiency at different input
voltages: IC self-biased
(J1 not selected)
AM11633v1
5/11
Measurements
Active mode efficiency vs. VIN IC
externally biased (J1selected)
Figure 9.
85
85
80
80
75
75
eff [%]
eff [%]
Figure 8.
STEVAL-ISA113V1
70
70
65
65
Active mode efficiency vs. VIN IC
self-biased (J1 not selected)
60
60
80
110
140
170
200
230
80
260
110
140
VIN[V AC ]
170
200
230
AM11538v1
Figure 10. Input voltage averaged efficiency
vs. load IC externally biased
(J1 selected)
AM11539v1
Figure 11. Input voltage averaged efficiency
vs. load IC self-biased
(J1 not selected)
85
85
80
80
75
75
eff [%]
eff [%]
260
VIN[V AC ]
70
65
70
65
60
0.05
0.1
0.15
0.2
0.25
0.3
0.35
60
0.05
0.4
0.1
0.15
IOUT [A]
0.2
0.25
0.3
0.35
0.4
IOUT [A ]
AM11540v1
AM11541v1
Figure 12. PIN vs. VIN at no load and light load: Figure 13. PIN vs. VIN at no load and light load:
IC externally biased (J1 selected)
IC self-biased (J1 not selected)
400
200
0
350
25mW
150
50mW
300
PIN [mW]
PIN [mW]
250
100
200
150
50
0
100
25mW
50
0
80
105
130
155
180
VIN [V AC ]
6/11
205
230
255
50mW
0
80
AM11543v1
Doc ID 024140 Rev 1
105
130
155
180
VIN [V AC ]
205
230
255
AM11544v1
STEVAL-ISA113V1
Measurements
Figure 14. Efficiency at PIN = 1 W: IC externally Figure 15. Efficiency at PIN = 1 W: IC selfbiased (J1 selected)
biased (J1 not selected)
80
80
75
75
70
70
65
eff [%]
eff [%]
65
60
55
60
55
50
50
45
45
40
40
35
80
110
140
170
200
230
260
80
110
140
VIN [V AC ]
170
200
230
260
VIN[V AC ]
AM11545v1
AM11546v1
Figure 16. PIN at POUT = 250 mW: IC externally Figure 17. PIN at POUT = 250 mW: IC selfbiased (J1 selected)
biased (J1 not selected)
0.8
0.5
0.75
0.7
0.45
0.6
0.4
PIN [W]
PIN [W]
0.65
0.35
0.55
0.5
0.45
0.4
0.3
0.35
0.25
0.25
0.3
80
110
140
170
200
230
260
80
VIN [V AC ]
AM13108v1
Doc ID 024140 Rev 1
110
140
170
200
VIN [V AC ]
230
260
AM13109v1
7/11
Board layout
3
STEVAL-ISA113V1
Board layout
Figure 18. Board layout - complete
AM13339v1
Figure 19. Board layout - top layer + top overlay
AM13340v1
8/11
Doc ID 024140 Rev 1
STEVAL-ISA113V1
Board layout
Figure 20. Board layout - bottom layer + top overlay
AM13341v1
Doc ID 024140 Rev 1
9/11
Revision history
4
STEVAL-ISA113V1
Revision history
Table 3.
10/11
Document revision history
Date
Revision
10-Jan-2013
1
Changes
Initial release.
Doc ID 024140 Rev 1
STEVAL-ISA113V1
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Doc ID 024140 Rev 1
11/11
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