AT93C46 Automotive - Mature

1. Features
• Medium-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
Three-wire Serial Interface
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead TSSOP and 8-lead JEDEC SOIC Packages
•
•
•
•
2. Description
The AT93C46 provides 1024 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each, when the ORG pin is
connected to VCC and 128 words of 8 bits each when it is tied to ground. The device
is optimized for use in many automotive applications where low power and low voltage
operations are essential. The AT93C46 is available in space-saving 8-lead TSSOP
and 8-lead JEDEC SOIC packages. The AT93C46 is enabled through the Chip Select
pin (CS), and accessed via a 3-wire serial interface consisting of Data Input (DI), Data
Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the
address is decoded and the data is clocked out serially on the data output pin DO. The
WRITE cycle is completely self-timed and no separate erase cycle is required before
write. The Write cycle is only enabled when it is in the Erase/Write Enable state. When
CS is brought “high” following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status.
Three-wire
Automotive
Temperature
Serial
EEPROMs
1K (128 x 8 or 64 x 16)
AT93C46
8-lead SOIC
Table 2-1.
Pin Configuration
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
CS
SK
DI
DO
1
2
3
4
VCC
DC
ORG
GND
8
7
6
5
8-lead TSSOP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
Rev. 5125C–SEEPR–11/07
3. Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability
DC Output Current........................................................ 5.0 mA
Figure 3-1.
Note:
2
Block Diagram
When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the “x 16” organization is selected.
For the AT93C46, if “x 16” organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends
using the AT93C46A device. For more details, see the AT93C46A datasheet.
AT93C46
5125C–SEEPR–11/07
AT93C46
Table 3-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
Output Capacitance (DO)
CIN
Note:
Max
Units
Conditions
5
pF
VOUT = 0V
5
pF
VIN = 0V
Input Capacitance (CS, SK, DI)
1. This parameter is characterized and is not 100% tested.
Table 3-2.
DC Characteristics
Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise
noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Supply Voltage
ICC
Supply Current
VCC = 5.0V
ISB1
Standby Current
ISB2
IIL
IOL
VIL1
(1)
Min
Typ
Max
Unit
2.7
5.5
V
4.5
5.5
V
READ at 1.0 MHz
0.5
2.0
mA
WRITE at 1.0 MHz
0.5
2.0
mA
VCC = 2.7V
CS = 0V
6.0
10.0
µA
Standby Current
VCC = 5.0V
CS = 0V
10.0
15.0
µA
Input Leakage
VIN = 0V to VCC
0.1
1.0
µA
Output Leakage
VIN = 0V to VCC
0.1
1.0
µA
Input Low Voltage
VIH1(1)
Input High Voltage
VOL1
Output Low Voltage
VOH1
Note:
Test Condition
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
−0.6
0.8
2.0
VCC + 1
V
0.4
V
IOL = 2.1 mA
Output High Voltage
IOH = −0.4 mA
1. VIL min and VIH max are reference only and are not tested.
2.4
V
3
5125C–SEEPR–11/07
Table 3-3.
AC Characteristics
Applicable over recommended operating range from TA = −40°C to + 125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
fSK
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
tSKH
SK High Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tSKL
SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tCS
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
ns
tDIS
DI Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
ns
tCSH
CS Hold Time
Relative to SK
0
ns
tDIH
DI Hold Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
ns
tPD1
Output Delay to ‘1’
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
ns
tPD0
Output Delay to ‘0’
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
ns
tSV
CS to Status Valid
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
150
ns
10
ms
tWP
Write Cycle Time
Endurance
Note:
4
(1)
Min
2.7V ≤ VCC ≤ 5.5V
5.0V, 25°C
Typ
3
1M
Max
Units
2
1
MHz
Write Cycles
1. This parameter is ensured by characterization only.
AT93C46
5125C–SEEPR–11/07
AT93C46
Table 3-4.
Instruction Set for the AT93C46
Address
Data
SB
Op
Code
x8
x 16
READ
1
10
A6 - A0
A5 - A0
EWEN
1
00
11XXXXX
11XXXX
Write enable must precede all
programming modes
ERASE
1
11
A6 - A0
A5 - A0
Erase memory location An - A0
WRITE
1
01
A6 - A0
A5 - A0
ERAL
1
00
10XXXXX
10XXXX
WRAL
1
00
01XXXXX
01XXXX
Instruction
x8
x 16
Reads data stored in memory, at
specified address
D7 - D0
D15 - D0
Writes memory location An - A0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
D7 - D0
D15 - D0
EWDS
1
00
00XXXXX
00XXXX
Note:
The Xs in the address field represent don’t care values and must be clocked.
Table 3-5.
Comments
Writes all memory locations. Valid
only at VCC = 4.5V to 5.5V
Disables all programming instructions
Instruction Set for the AT93C56(1) and AT93C66(2)
Address
Data
SB
Op
Code
x8
x 16
READ
1
10
A8 - A0
A7 - A0
EWEN
1
00
11XXXXXXX
11XXXXXX
Write enable must precede all
programming modes
ERASE
1
11
A8 - A0
A7 - A0
Erase memory location An - A0
WRITE
1
01
A8 - A0
A7 - A0
ERAL
1
00
10XXXXXXX
10XXXXXX
WRAL
1
00
01XXXXXXX
01XXXXXX
1
00
00XXXXXXX
00XXXXXX
Instruction
EWDS
Note:
x8
x 16
Comments
Reads data stored in memory, at
specified address
D7 - D0
D15 - D0
Writes memory location An - A0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V
D7 - D0
D15 - D0
Writes all memory locations. Valid
only at VCC = 5.0V ±10% and Disable
Register cleared
Disables all programming instructions
1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
3. The Xs in the address field represent don’t care values and must be clocked.
4. Functional Description
The AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid
instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the
appropriate Op Code and the desired memory Address location.
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory
5
5125C–SEEPR–11/07
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or
16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction
and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought
high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the
selected memory location has been erased, and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written
into the specified memory location. The self-timed programming cycle, tWP, starts after the last
bit of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of
the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO
indicates that programming is still in progress. A logic “1” indicates that the memory location at
the specified address has been written with the data pattern contained in the instruction and the
part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is
brought high after the end of the self-timed programming cycle, tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is
valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes and should be executed after all
programming operations. The operation of the Read instruction is independent of both the
EWEN and EWDS instructions and can be executed at any time.
6
AT93C46
5125C–SEEPR–11/07
AT93C46
5. Timing Diagrams
Figure 5-1.
Note:
Synchronous Data Timing
1. This is the minimum SK period.
Table 5-1.
Organization Key for Timing Diagrams
AT93C56 (2K)(1)
AT93C46 (1K)
I/O
Notes:
x8
x 16
AN
A6
A5
DN
D7
D15
x8
(3)
A8
D7
AT93C66 (4K)(2)
x 16
x8
x 16
(4)
A7
A8
A7
D15
D7
D15
1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
3. A8 is a don’t care value, but the extra clock is required.
4. A7 is a don’t care value, but the extra clock is required.
Figure 5-2.
READ Timing
tCS
High Impedance
7
5125C–SEEPR–11/07
Figure 5-3.
EWEN Timing
tCS
CS
SK
DI
Figure 5-4.
1
0
0
1
...
1
EWDS Timing
tCS
CS
SK
DI
Figure 5-5.
1
0
0
0
...
0
WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
HIGH IMPEDANCE
BUSY
READY
tWP
Figure 5-6.
WRAL Timing(1)
tCS
CS
SK
1
DI
DO
0
0
0
1
...
DN
...
D0
BUSY
HIGH IMPEDANCE
READY
tWP
8
AT93C46
5125C–SEEPR–11/07
AT93C46
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 5-7.
ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
1
AN
1
AN-1 AN-2
...
A0
tDF
tSV
DO
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
READY
tWP
Figure 5-8.
ERAL Timing(1)
tCS
CS
CHECK
STATUS
STANDBY
tSV
tDF
SK
DI
DO
1
0
0
1
0
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
5125C–SEEPR–11/07
6. AT93C46 Ordering Information
Ordering Code
Package
AT93C46-10SQ-2.7
AT93C46-10TQ-2.7
8S1
8A2
Operation Range
Lead-Free/Halogen Free
Automotive Temperature
(−40°C to 125°C)
Package Type
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
Options
−2.7
10
Low Voltage (2.7V to 5.5V)
AT93C46
5125C–SEEPR–11/07
AT93C46
Packaging Information
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
11
5125C–SEEPR–11/07
8A2 - TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
E
E1
e
D
A2
6.40 BSC
4.30
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
12
4
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
AT93C46
5125C–SEEPR–11/07
AT93C46
Revision History
Doc. Rev.
Date
Comments
5125C
11/2007
Updated to new template
Changed max value of Vil1, Vih1, and tDF
5125B
1/2007
Implemented revision history
Removed PDIP package offering
Removed Pb’d parts
13
5125C–SEEPR–11/07
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5125C–SEEPR–11/07
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