Features • Medium-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) • Automotive Temperature Range –40°C to 125°C • User-selectable Internal Organization • • • • • • • – 2K: 256 x 8 or 128 x 16 – 4K: 512 x 8 or 256 x 16 Three-wire Serial Interface Sequential Read Operation 2 MHz Clock Rate Self-timed Write Cycle (10 ms max) High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years Lead-free/Halogen-free Devices Available 8-lead JEDEC SOIC and 8-lead TSSOP Packages Description The AT93C56A/66A provides 2048/4096 bits of serial electrically-erasable programmable read-only memory (EEPROM). The EEPROM is organized as 128/256 words of 16 bits each when the ORG pin is connected to VCC and 256/512 words of 8 bits each when it is tied to ground. The device is optimized for use in many automotive applications where low-power and low-voltage operations are essential. The AT93C56A/66A is available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages. The AT93C56A/66A is enabled through the Chip Select (CS) pin and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The write cycle is completely self-timed and no separate erase cycle is required before write. The write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. Three-wire Automotive Temperature Serial EEPROMs 2K (256 x 8 or 128 x 16) 4K (512 x 8 or 256 x 16) AT93C56A AT93C66A The AT93C56A/66A is available in 2.7V to 5.5V versions. Table 1. Pin Configuration Pin Name Function CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground VCC Power Supply ORG Internal Organization DC Don’t Connect 8-lead SOIC CS SK DI DO 1 2 3 4 8 7 6 5 VCC DC ORG GND 8-lead TSSOP CS SK DI DO 1 2 3 4 8 7 6 5 VCC DC ORG GND Rev. 5091D–SEEPR–2/07 1 Absolute Maximum Ratings* Operating Temperature......................................−55°C to +125°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Figure 1. Block Diagram Note: 2 When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the “x 16” organization is selected. AT93C56A/66A 5091D–SEEPR–2/07 AT93C56A/66A Table 1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol Test Conditions COUT CIN Note: Max Units Conditions Output Capacitance (DO) 5 pF VOUT = 0V Input Capacitance (CS, SK, DI) 5 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 2. DC Characteristics Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted) Symbol Parameter Test Condition VCC1 Supply Voltage VCC2 Supply Voltage ICC Supply Current VCC = 5.0V ISB1 Standby Current ISB2 Min Typ Max Unit 2.7 5.5 V 4.5 5.5 V READ at 1.0 MHz 0.5 2.0 mA WRITE at 1.0 MHz 0.5 2.0 mA VCC = 2.7V CS = 0V 6.0 10.0 µA Standby Current VCC = 5.0V CS = 0V 17 30 µA IIL Input Leakage VIN = 0V to VCC 0.1 3.0 µA IOL Output Leakage VIN = 0V to VCC 0.1 3.0 µA VIL1(1) Input Low Voltage −0.6 0.8 V VIH1(1) Input High Voltage 2.0 VCC + 1 VOL1 Output Low Voltage VOH1 Output High Voltage Note: 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V IOL = 2.1 mA IOH = −0.4 mA 0.4 2.4 V V 1. VIL min and VIH max are reference only and are not tested. 3 5091D–SEEPR–2/07 Table 3. AC Characteristics Applicable over recommended operating range from TA = −40°C to + 125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter Test Condition Min fSK SK Clock Frequency 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 0 0 tSKH SK High Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tSKL SK Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tCS Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tCSS CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 50 50 ns tDIS DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 100 ns tCSH CS Hold Time Relative to SK 0 ns tDIH DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 100 ns tPD1 Output Delay to “1” AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 500 ns tPD0 Output Delay to “0” AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 500 ns tSV CS to Status Valid AC Test 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 250 250 ns tDF CS to DO in High Impedance AC Test CS = VIL 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 100 150 ns 10 ms tWP Write Cycle Time (1) Endurance Note: 4 2.7V ≤ VCC ≤ 5.5V 5.0V, 25°C 0.1 1M Typ 3 Max Units 2 1 MHz Write Cycles 1. This parameter is characterized and is not 100% tested. AT93C56A/66A 5091D–SEEPR–2/07 AT93C56A/66A Functional Description The AT93C56A/66A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location. Table 4. Instruction Set for the AT93C56A and AT93C66A Address Data SB Op Code x8 x 16 READ 1 10 A8 – A0 A7 − A0 EWEN 1 00 11XXXXXXX 11XXXXXX Write enable must precede all programming modes ERASE 1 11 A8 − A0 A7 − A0 Erase memory location An − A0 WRITE 1 01 A8 − A0 A7 − A0 ERAL 1 00 10XXXXXXX 10XXXXXX WRAL 1 00 01XXXXXXX 01XXXXXX EWDS 1 00 00XXXXXXX 00XXXXXX Instruction Note: x8 x 16 Comments Reads data stored in memory, at specified address D7 − D0 D15 − D0 Writes memory location An − A0 Erases all memory locations. Valid only at VCC = 4.5V to 5.5V D7 − D0 D15 − D0 Writes all memory locations. Valid only at VCC = 5.0V ±10% and Disable Register cleared Disables all programming instructions The X’s in the address field represent don’t care values and must be clocked. READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A supports sequential read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. 5 5091D–SEEPR–2/07 WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed programming cycle, tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. Timing Diagrams Figure 1. Synchronous Data Timing Note: This is the minimum SK period. Table 5. Organization Key for Timing Diagrams AT93C56A (2K) Notes: 6 AT93C66A (4K) I/O x8 x 16 x8 x 16 AN A8(1) A7(2) A8 A7 DN D7 D15 D7 D15 1. A8 is a don’t care value, but the extra clock is required. 2. A7 is a don’t care value, but the extra clock is required. AT93C56A/66A 5091D–SEEPR–2/07 AT93C56A/66A Figure 2. READ Timing tCS High Impedance Figure 3. EWEN Timing tCS CS SK DI 1 0 0 1 ... 1 Figure 4. EWDS Timing tCS CS SK DI 1 0 0 0 ... 0 Figure 5. WRITE Timing tCS CS SK DI DO 1 0 1 AN ... A0 DN ... D0 HIGH IMPEDANCE BUSY READY tWP 7 5091D–SEEPR–2/07 Figure 6. WRAL Timing tCS CS SK DI DO 1 0 0 0 1 ... DN ... D0 BUSY HIGH IMPEDANCE READY tWP Note: Valid only at VCC = 4.5V to 5.5V Figure 7. ERASE Timing tCS CS STANDBY CHECK STATUS SK 1 DI 1 1 AN AN-1 AN-2 ... A0 tDF tSV DO HIGH IMPEDANCE HIGH IMPEDANCE BUSY READY tWP Figure 8. ERAL Timing tCS CS CHECK STATUS STANDBY tSV tDF SK DI DO 1 0 0 1 0 BUSY HIGH IMPEDANCE HIGH IMPEDANCE READY tWP Note: 8 Valid only at VCC = 4.5V to 5.5V AT93C56A/66A 5091D–SEEPR–2/07 AT93C56A/66A AT93C56A Ordering Information Ordering Code Package Operation Range 8S1 8A2 Lead-free/Halogen-free/Automotive Temperature (−40°C to 125°C) AT93C56A-10SQ-2.7 AT93C56A-10TQ-2.7 Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V) 9 5091D–SEEPR–2/07 AT93C66A Ordering Information Ordering Code Package Operation Range 8S1 8A2 Lead-free/Halogen-free/Automotive Temperature (−40°C to 125°C) AT93C66A-10SQ-2.7 AT93C66A-10TQ-2.7 Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options −2.7 10 Low Voltage (2.7V to 5.5V) AT93C56A/66A 5091D–SEEPR–2/07 AT93C56A/66A 8S1 - JEDEC SOIC C 1 E E1 L N ∅ Top View End View e B COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D Side View MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e NOTE 1.27 BSC L 0.40 – 1.27 ∅ 0° – 8° Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 R 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B 11 5091D–SEEPR–2/07 8A2 − TSSOP 3 2 1 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A b D MIN NOM MAX NOTE 2.90 3.00 3.10 2, 5 4.40 4.50 3, 5 E E1 e A2 D 6.40 BSC 4.30 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 e Side View L 0.65 BSC 0.45 L1 Notes: 0.60 0.75 1.00 REF 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 12 4 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B AT93C56A/66A 5091D–SEEPR–2/07 AT93C56A/66A Revision History Doc. Rev. Date Comments 5091D 2/2007 Implemented revision history Removed PDIP package offering Removed Pb’d part numbers 13 5091D–SEEPR–2/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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