656C

 Model 656C Advanced PLL HCMOS Clock Features 
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Ceramic Surface Mount Package Low Phase Jitter Performance, 600fs Typical Advanced PLL Design w/ Low Fundamental Crystal Frequency Range 10 – 250MHz * +2.5V or +3.3V Operation Output Enable Standard Tape and Reel Packaging, EIA‐418 Part Dimensions: 7.0 × 5.0 × 2.0mm • 178.462mg Standard Frequencies ‐ 77.76MHz ‐ 100.00MHz Applications 
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Broadcast Video Systems Storage Area Networking Broadband Access PCI Express 
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Networking Equipment Ethernet/GbE/SyncE Fiber Channel Test and Measurement ‐ 106.25MHz ‐ 125.00MHz * Check with factory for availability. Description CTS Model 656C is a low cost, high performance PLL clock oscillator supporting HCMOS output. Employing the latest IC technology, M656C has excellent stability and low phase jitter performance. Ordering Information
Output
Type
C
Model
656
Frequency Stability
3
Frequency Code
[MHz]
X XX or XXX X
Code
Frequency
1
Output
HCMOS
Supply
Voltage
3
Code Temp. Range
‐20°C to +70°C
C
‐40°C to +85°C
I
Product Frequency Code Code
C
Temperature Range
I
Code
6
5
3
Stability
2
±20ppm ±25ppm
±50ppm
Packaging
T
Packing
Code
1k pcs./reel
T
Code
2
3
Voltage
+2.5Vdc
+3.3Vdc
Notes:
1] Refer to document 016‐1454‐0, Frequency Code Tables.
3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater.
2] Consult factory for availability of 6I Stability/Temperature combination.
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
DOC# 008‐0342‐1 Rev. B Page 1 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 656C Advanced PLL HCMOS Clock Electrical Specifications Operating Conditions
P ARAMETER
SYMBO L
CO NDITIO NS
MIN
TYP
MAX
UNIT
Maximum Supp ly Voltage
VCC
‐
‐0.5
‐
5.0
V
Sup ply Voltage
VCC
±5%
2.375
2.5
2.625
3.135
3.3
3.465
Sup ply Current
ICC
Maximum Load
‐
20
‐
O peratin g Temperature
TA
‐
TSTG
‐
‐55
SYMBO L
CO NDITIO NS
MIN
Sto rage Temperature
‐20
‐40
+25
+70
+85
V
mA
°C
‐
+125
°C
TYP
MAX
UNIT
Frequency Stability
P ARAMETER
Frequenc y Ran ge
Frequenc y Stability
[Note 1]
Aging
fO
‐
10 ‐ 250
Δf/fO
‐
20, 25 or 50
Δf/f25
First Year @ +25°C, nominal VCC
‐3
MHz
±ppm
‐
3
ppm
TYP
MAX
UNIT
1.] Inc lusive of initial tolerance at time of shipment, c hanges in supply voltage, load, temperature and 1st year aging.
Output Parameters
P ARAMETER
SYMBO L
CO NDITIO NS
O utput Ty pe
‐
‐
O utput Load
CL
‐
O utput Voltage Levels
VOH
VOL
MIN
HCMOS
‐
CMOS Load
‐
‐
15
0.9VCC
‐
‐
‐
‐
0.1VCC
pF
V
O utput Duty Cy c le
SYM
@ 50% Level
45
‐
55
Rise and Fall Time
TR, TF
@ 20%/80% Levels, CL = 15pF
‐
5
10
ns
TS
Application of VCC
‐
3
5
ms
Start Up Time
%
Enable Fu nc tion [Standby ]
En able Input Voltage
VIH
Pin 1 Logic '1', Output Enabled
0.7VCC
‐
‐
V
Disable Inp ut Voltage
VIL
Pin 1 Logic '0', Output Disabled
‐
‐
0.3VCC
V
Disable Current
IIL
Pin 1 Logic '0', Output Disabled
‐
‐
20
uA
En able Time
TPLZ
Pin 1 Logic '1', Output Enabled
‐
‐
5
ns
P hase Jitter, RMS
tjrms
Bandwidth 12 kHz ‐ 20 MHz
‐
600
<1000
fs
pjpk‐pk
‐
‐
3.0
‐
ps
pjrms
‐
‐
30
‐
ps
P eriod Jitter, p k‐p k
P eriod Jitter, RMS
DOC# 008‐0342‐1 Rev. B Page 2 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 656C Advanced PLL HCMOS Clock Electrical Specifications Enable Truth Table Pin 1 Pin 4 Logic ‘1’ Open Logic ‘0’ Output Output High Imp. Test Circuit HCMOS Output Waveform HCMOS DOC# 008‐0342‐1 Rev. B Page 3 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 656C Advanced PLL HCMOS Clock Electrical Specifications Performance Data Phase Noise [typical] 62.50MHz, HCMOS, VCC = 3.3V, TA = +25°C 100.00MHz, HCMOS, VCC = 3.3V, TA = +25°C 125.00MHz, HCMOS, VCC = 3.3V, TA = +25°C 250.00MHz, HCMOS, VCC = 3.3V, TA = +25°C DOC# 008‐0342‐1 Rev. B Page 4 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 656C Advanced PLL HCMOS Clock Electrical Specifications Performance Data Phase Noise Tabulated Typical, HCMOS, VCC = 3.3V, TA = +25°C P ARAMETER
SYMBO L
CO NDITIO NS
TYP
UNIT
P ARAMETER
HCMO S @ 6 2 .5 MHz
P h ase Noise
Single Side Band
‐
P h ase Jitter, RMS
P ARAMETER
CO NDITIO NS
TYP
UNIT
tjrms
P hase No ise
Single Side Band
@ 10Hz
‐80.50
@ 10Hz
‐82.60
@ 100Hz
‐105.40
@ 100Hz
‐101.40
@ 1kHz
‐121.40
@ 1kHz
‐111.50
@ 10kHz
‐130.50 dBc/Hz
@ 10kHz
‐125.10 dBc/Hz
@ 100kHz
‐134.50
@ 100kHz
‐130.10
@ 1MHz
‐150.10
@ 1MHz
‐143.40
@ 10MHz
‐154.30
@ 10MHz
‐154.20
@ 40MHz
‐154.40
@ 40MHz
‐156.60
Integration Bandwidth 12kHz ‐ 20MHz 632.41
SYMBO L
CO NDITIO NS
TYP
‐
fs
P hase Jitter, RMS
UNIT
P ARAMETER
HCMO S @ 1 2 5 .0 0 MHz
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 579.53
SYMBO L
CO NDITIO NS
TYP
fs
UNIT
HCMO S @ 2 5 0 .0 0 MHz
P h ase Noise
Single Side Band
‐
P h ase Jitter, RMS
SYMBO L
HCMO S @ 1 0 0 .0 0 MHz
tjrms
P hase No ise
Single Side Band
@ 10Hz
‐69.00
@ 10Hz
@ 100Hz
‐89.80
@ 100Hz
@ 1kHz
‐115.30
@ 10kHz
‐123.10 dBc/Hz
@ 100kHz
‐128.50
@ 1MHz
‐86.00
‐95.40
@ 1kHz
‐110.40
@ 10kHz
‐119.10 dBc/Hz
@ 100kHz
‐120.70
‐144.20
@ 1MHz
‐137.70
@ 10MHz
‐152.60
@ 10MHz
‐149.30
@ 40MHz
‐153.00
@ 40MHz
‐153.30
Integration Bandwidth 12kHz ‐ 20MHz 543.39
‐
fs
P hase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 560.64
fs
DOC# 008‐0342‐1 Rev. B Page 5 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 656C Advanced PLL HCMOS Clock Mechanical Specifications Package Drawing Marking Information 1. ** ‐ Manufacturing Site Code. 2. YYWW – Date Code; YY – year, WW – week. 3. O – Output Type; C = HCMOS. 4. ST – Frequency Stability/Temperature Code. [Refer to Ordering Information] 5. V – Voltage Code; 3 = 3.3V, 2 = 2.5V. 6. xxxx – Frequency Code. 3‐digits, frequencies below 100MHz 4‐digits, frequencies 100MHz or greater [See document 016‐1454‐0, Frequency Code Tables.] CTS**YYWW 656OSTV ● xxxx Recommended Pad Layout Notes 1. JEDEC termination code (e4). Barrier‐plating is nickel [Ni] with gold [Au] flash plate. 2. Reflow conditions per JEDEC J‐STD‐020; +260°C maximum, 20 seconds. 3. MSL = 1. Pin Assignments Pin Symbol Function 1 2 3 4 5 6 EOH N.C. GND Output N.C. VCC Enable No Connect Circuit & Package Ground RF Output No Connect Supply Voltage DOC# 008‐0342‐1 Rev. B Page 6 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 656C Advanced PLL HCMOS Clock Packaging ‐ Tape and Reel Tape Drawing Reel Drawing Notes 1. Device quantity is 1k pieces maximum per 180mm reel. 2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels. DOC# 008‐0342‐1 Rev. B Page 7 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. 
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