Data Sheet

 Model 635 Low Jitter LVPECL or LVDS Clock Features 
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Ceramic Surface Mount Package Low Phase Jitter Performance, 700fs Maximum Fundamental or 3rd Overtone Crystal Design Frequency Range 10 – 320MHz * +2.5V or +3.3V Operation Output Enable Standard Tape and Reel Packaging, EIA‐418 Part Dimensions: 7.0 × 5.0 × 2.0mm • 178.462mg Applications 
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SerDes Storage Area Networking Broadband Access SONET/SDH/DWDM 
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PON Ethernet/GbE/SyncE Fiber Channel Test and Measurement Standard Frequencies ‐ 25.00MHz ‐ 50.00MHz ‐ 100.00MHz ‐ 125.00MHz ‐ 155.52MHz ‐ 156.25MHz ‐ 161.1328MHz ‐ 187.50MHz ‐ 200.00MHz ‐ 212.50MHz ‐ 250.00MHz ‐ 312.50MHz * Check with factory for availability. Description CTS Model 635 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs. Employing the latest IC technology, M635 has excellent stability and low jitter/phase noise performance. Ordering Information
Model
Output Type
635
P
Code
P
L
E
V
Frequency Stability
3
Temperature Range
I
Supply
Voltage
3
Code Temp. Range
‐10°C to +60°C
A
‐20°C to +70°C
C
‐40°C to +85°C
I
Output
LVPECL ‐ Pin 1 Enable
LVDS ‐ Pin 1 Enable
LVPECL ‐ Pin 2 Enable
LVDS ‐ Pin 2 Enable
Code
6
5
3
2
Stability
[MHz]
XXXMXXXX
Code
2
Voltage
+2.5Vdc
+3.3Vdc
Notes:
1] Consult factory for availability of 6I Stability/Temperature combination.
2] Frequency is recorded with 3 significant digits before the 'M' and 4 significant digits after the 'M',
including zeros. See Table I for frequency codes that exceed 4 significant digits.
Table I
Nominal Freq uenc y
P art Nu mb er
[MHz]
Freq uenc y Cod e
025.000625
025M0006
074.175824
074M175B
101.575694
101M5756
125.009375
125M0093
148.351648
148M351A
153.600770
153M6007
156.253906
156M2539
178.018970
178M0189
Example: P/N Frequency = Actual Frequency.
148M351A = 148.351648MHz
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
DOC# 008‐0284‐0 Rev. F Frequency
Product Frequency Code Code
2
3
1
±20ppm ±25ppm
±50ppm
±100ppm
Frequency Code
Page 1 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 635 Low Jitter LVPECL or LVDS Clock Electrical Specifications Operating Conditions
P ARAMETER
SYMBO L
CO NDITIO NS
MIN
TYP
MAX
UNIT
Maximu m Supply Voltage
VCC
‐
‐0.5
‐
5.0
V
Supp ly Vo ltage
VCC
±5%
2.375
2.5
2.625
3.135
3.3
3.465
ICC
Maximum Load
‐
55
88
‐
45
66
V
Supp ly Cu rrent
LVP ECL
LVDS
O perating Temperatu re
Storage Temperature
‐20
+70
mA
TA
‐
TSTG
‐
‐40
‐
+125
°C
SYMBO L
CO NDITIO NS
MIN
TYP
MAX
UNIT
fO
‐
+25
‐40
+85
°C
Frequency Stability
P ARAMETER
Frequenc y Range
LVP ECL
10 ‐ 320
Frequenc y Stability
[Note 1]
Aging
MHz
80 ‐ 320
LVDS
20, 25, 50 or 100
Δf/fO
‐
Δf/f25
First Year @ +25°C, nominal VCC
±ppm
‐3
‐
3
ppm
MIN
TYP
MAX
UNIT
1.] Inc lusive of initial toleranc e at time of shipment, c hanges in supply voltage, load, temperature and 1st year aging.
Output Parameters
P ARAMETER
SYMBO L
CO NDITIO NS
O utp ut Ty pe
‐
‐
RL
Terminated to VCC ‐ 2.0V
O utp ut Lo ad
VOH
O utp ut Voltage Lev els
VOL
VOH
VOL
LVPECL
PECL Load, ‐20°C to +70°C
PECL Load, ‐40°C to +85°C
‐
‐
50
‐
VCC ‐ 1.025
‐
VCC ‐ 0.880
VCC ‐ 1.810
‐
VCC ‐ 1.620
VCC ‐ 1.085
‐
VCC ‐ 0.880
VCC ‐ 1.830
‐
VCC ‐ 1.555
Ohms
V
V
O utp ut Du ty Cy c le
SYM
@ VCC ‐ 1.3V
45
‐
55
%
Rise and Fall Time
TR, TF
@ 20%/80% Levels, RL = 50 Ohms
‐
0.3
0.7
ns
‐
‐
RL
Between Outputs
O utp ut Ty pe
O utp ut Lo ad
O utp ut Voltage Lev els
VOH
VOL
LVDS
LVDS Load
‐
‐
100
‐
‐
1.43
1.60
0.90
1.10
‐
Ohms
V
O utp ut Du ty Cy c le
SYM
@ 1.25V
45
‐
55
%
Differential O utpu t Voltage
VOD
RL = 100 Ohms
247
330
454
mV
O ffset Voltage
VOS
LVDS Load
1.125
1.25
1.375
V
TR, TF
@ 20%/80% Levels, RL = 100 Ohms
‐
0.4
0.7
ns
Rise and Fall Time
DOC# 008‐0284‐0 Rev. F Page 2 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 635 Low Jitter LVPECL or LVDS Clock Electrical Specifications Output Parameters
P ARAMETER
SYMBO L
CO NDITIO NS
MIN
TYP
MAX
UNIT
TS
Application of VCC
‐
2
5
ms
Start Up Time
Enable Func tion [Standby ]
Enable Input Voltage
VIH
Pin 1 or 2 Logic '1', Output Enabled
0.7VCC
‐
‐
V
Disable Input Voltage
VIL
Pin 1 or 2 Logic '0', Output Disabled
‐
‐
0.3VCC
V
Disable Time
TPLZ
Pin 1 or 2 Logic '0', Output Disabled
‐
‐
200
ns
Enable Time
TPLZ
Pin 1 or 2 Logic '1', Output Enabled
‐
‐
2
ms
P hase Jitter, RMS
tjrms
Bandwidth 12 kHz ‐ 20 MHz
‐
300
700
fs
pjpk‐pk
‐
‐
2.6
‐
ps
pjrms
‐
‐
25
‐
ps
P eriod Jitter, pk‐pk
P eriod Jitter, RMS
Enable Truth Table Pin 1 or Pin 2 Pin 4 & Pin 5 Logic ‘1’ Open Logic ‘0’ Output Output High Imp. Test Circuit LVDS LVPECL Output Waveform LVPECL or LVDS DOC# 008‐0284‐0 Rev. F Page 3 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 635 Low Jitter LVPECL or LVDS Clock Electrical Specifications Performance Data Phase Noise [typical] 25MHz, LVPECL, VCC = 3.3V, TA = +25°C 100MHz, LVPECL, VCC = 3.3V, TA = +25°C DOC# 008‐0284‐0 Rev. F Page 4 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 635 Low Jitter LVPECL or LVDS Clock Electrical Specifications Performance Data Phase Noise [typical] 155.52MHz, LVDS, VCC = 3.3V, TA = +25°C Phase Noise Tabulated Typical, VCC = 3.3V, TA = +25°C P ARAMETER
SYMBO L
CO NDITIO NS
TYP
UNIT
P ARAMETER
LVP ECL @ 2 5 .0 0 MHz
P h ase No ise
Single Side Band
‐
P h ase Jitter, RMS
P ARAMETER
SYMBO L
CO NDITIO NS
TYP
UNIT
LVP ECL @ 1 0 0 .0 0 MHz
tjrms
P hase Noise
Single Side Band
@ 10Hz
‐75.14
@ 10Hz
‐65.65
@ 100Hz
‐112.50
@ 100Hz
‐100.19
@ 1kHz
‐142.15
@ 10kHz
‐155.01
dBc/Hz
‐
@ 1kHz
‐131.02
@ 10kHz
‐145.49
‐150.36
@ 100kHz
‐159.99
@ 100kHz
@ 1MHz
‐161.83
@ 1MHz
‐151.37
@ 5MHz
‐161.61
@ 5MHz
‐152.11
Integration Bandwidth 12kHz ‐ 20MHz 179.24
SYMBO L
CO NDITIO NS
TYP
fs
P hase Jitter, RMS
tjrms
Integration Bandwidth 12kHz ‐ 20MHz 132.20
dBc/Hz
fs
UNIT
LVDS @ 1 5 5 .5 2 MHz
P h ase No ise
Single Side Band
‐
P h ase Jitter, RMS
tjrms
@ 10Hz
‐69.89
@ 100Hz
‐103.42
@ 1kHz
‐130.99
@ 10kHz
‐142.69
@ 100kHz
‐144.46
@ 1MHz
‐144.49
@ 20MHz
‐145.13
Integration Bandwidth 12kHz ‐ 20MHz 383.70
DOC# 008‐0284‐0 Rev. F dBc/Hz
fs
Page 5 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 635 Low Jitter LVPECL or LVDS Clock Mechanical Specifications Package Drawing Marking Information CTS**YYWW 635OSTV ● xxxMxxxxxx Recommended Pad Layout 1. 2. 3. 4. 5. 6. ** ‐ Manufacturing Site Code. YYWW – Date Code; YY – year, WW – week. O – Output Type; P or E = LVPECL, L or V = LVDS. ST – Frequency Stability/Temperature Code. [Refer to Ordering Information] V – Voltage Code; 3 = 3.3V, 2 = 2.5V. xxxMxxxxxx – Frequency is marked with only leading significant digits before the “M” and 4 – 6 digits after the “M” [including zeros]. Ex. Frequency 19.44MHz 153.60077MHz 148.351648 Marking 19M4400 153M60077 148M351648 Notes 1. JEDEC termination code (e4). Barrier‐plating is nickel [Ni] with gold [Au] flash plate. 2. Reflow conditions per JEDEC J‐STD‐020; +260°C maximum, 20 seconds. 3. MSL = 1. Pin Assignments Pin Symbol Function 1 2 3 4 5 6 EOH or N.C. N.C. or EOH GND Output Output VCC Enable [std] or No Connect No Connect or Enable [opt] Circuit & Package Ground RF Output Complimentary RF Output Supply Voltage Packaging ‐ Tape and Reel DOC# 008‐0284‐0 Rev. F Page 6 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 635 Low Jitter LVPECL or LVDS Clock Tape Drawing Reel Drawing Notes 1. Device quantity is 1k pieces maximum per 180mm reel. 2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels. DOC# 008‐0284‐0 Rev. F Page 7 of 7 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. 
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