Ultralow Power Boost Regulator with MPPT and Charge Management ADP5090 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT ADP5090 PIN PSYS SW VIN COLD-START CHARGE PUMP SYS MPPT BAT CBP MPPT CONTROL BOOST REGULATOR MINOP PGOOD + RECHARGEABLE BATTERY OR – SUPERCAP TO MCU REF DIS_SW FROM MCU OPTIONAL PRIMARY BATTERY BACK_UP CHARGE CONTROL AND POWER PATH MANAGEMENT SETSD SETPG + – TERM AGND PGND 12263-001 Boost regulator with maximum power point tracking (MPPT) Hysteretic controller for best ultralight load efficiency 320 nA ultralow quiescent current (CBP ≥ MINOP) 260 nA ultralow quiescent current (CBP < MINOP) Input voltage operation range from 80 mV to 3.3 V Cold start from 380 mV (typical) with charge pump Open circuit voltage (OCV) sensing for MPPT Programmable MPPT ratio for photovoltaic (PV) or thermoelectric generator (TEG) energy sources Programmable shutdown point on MINOP pin Energy storage management Programmable voltage monitor (2.2 V to 5.2 V) to support charging and prevent overcharging or overdischarging Power path management for an optional backup primary cell battery connected to the BACK_UP pin Radio frequency (RF) transmission friendly Temporary shutdown boost regulator via microcontroller (MCU) communication Figure 1. APPLICATIONS PV cell energy harvesting TEG energy harvesting Battery regulator powered by solar panel Industrial monitoring Self powered wireless sensor devices Portable and wearable devices with energy harvesting GENERAL DESCRIPTION The ADP5090 is an integrated boost regulator that converts dc power from PV cells or TEGs. The device charges storage elements such as rechargeable Li-Ion batteries, thin film batteries, super capacitors, and conventional capacitors, and powers up small electronic devices and battery-free systems. The ADP5090 provides efficient conversion of the harvested limited power from a 16 µW to 200 mW range with sub-µW operation losses. With the internal cold-start circuit, the regulator can start operating at an input voltage as low as 380 mV. After cold startup, the regulator is functional at an input voltage range of 80 mV to 3.3 V. By sensing the input voltage at the VIN pin, the control loop keeps the input voltage ripple in a fixed range to maintain stable dcto-dc boost conversion. The VIN OCV sensing and programmable regulation points of the input voltage allow extraction of the highest possible energy from the PV cell or TEG harvester. A programmable minimum operation threshold (MINOP) Rev. C enables boost shutdown during a low light condition. In addition, the DIS_SW pin can temporarily shut down the boost regulator and is RF transmission friendly. The charging control function of ADP5090 protects rechargeable energy storage, which is achieved by monitoring the battery voltage with programmable charging termination voltage and shutdown discharging voltage. In addition, a programmable PGOOD flag monitors the SYS voltage. An optional primary cell battery can be connected and managed by an integrated power path management control block that automatically switches the power source from the energy harvester, rechargeable battery, and primary cell battery. The ADP5090 is available in a 16-lead, 3 mm × 3 mm LFCSP and is rated for a −40°C to +125°C junction temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5090 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Disabling Boost........................................................................... 13 Applications ....................................................................................... 1 Battery Overcharging Protection ............................................. 13 Typical Application Circuit ............................................................. 1 Battery Discharging Protection ................................................ 13 General Description ......................................................................... 1 Power Good (PGOOD) ............................................................. 14 Revision History ............................................................................... 2 Power Path Working Flow......................................................... 15 Specifications..................................................................................... 3 Current Limit and Short-Circuit Protection .............................. 15 Absolute Maximum Ratings ............................................................ 4 Thermal Shutdown .................................................................... 15 Thermal Resistance ...................................................................... 4 Applications Information .............................................................. 16 ESD Caution .................................................................................. 4 Energy Harvester Selection ....................................................... 16 Pin Configuration and Function Descriptions ............................. 5 Energy Storage Element Selection ........................................... 16 Typical Performance Characteristics ............................................. 6 Inductor Selection ...................................................................... 16 Detailed Functional Block Diagram ............................................ 11 Capacitor Selection .................................................................... 16 Theory of Operation ...................................................................... 12 Layout and Assembly Considerations ..................................... 17 Cold Startup (VSYS < VSYS_TH, VIn > VIN_COLD) ........................... 12 Typical Application Circuits ......................................................... 18 Boost Regulator (VBAT_TERM > VSYS ≥ VSYS_TH) ........................... 12 Factory Programmable Options ................................................... 20 VIN Open Circuit and MPPT .................................................. 12 Outline Dimensions ....................................................................... 21 Energy Storage Charge Management....................................... 12 Ordering Guide .......................................................................... 21 Backup Storage Path ................................................................... 13 MINOP Function ....................................................................... 13 REVISION HISTORY 12/15—Rev. B to Rev. C Changes to Figure 10, Figure 12, and Figure 13 ........................... 7 Changes to Power Good (PGOOD) Section ............................... 14 Updated Outline Dimensions ....................................................... 21 8/15—Rev. A to Rev. B Changes to Input Peak Current Parameter and BACK_UP Current Capability Parameter, Table 1........................................... 3 Added Figure 10, Figure 12, Figure 13, and Figure 14; Renumbered Sequentially................................................................ 7 Changes to Backup Storage Path Section .................................... 13 Added Factory Programmable Options Section and Table 8; Renumbered Sequentially.............................................................. 20 Changes to Ordering Guide .......................................................... 21 11/14—Rev. 0 to Rev. A Changes to Figure 25 ...................................................................... 10 Changes to Battery Discharging Protection Section .................. 12 Changes to Power Good (PGOOD) Section and Table 5 Column Headings ........................................................................... 13 Changes to CBP Capacitor Section .............................................. 16 Change to Figure 32 ....................................................................... 18 9/14—Revision 0: Initial Version Rev. C | Page 2 of 21 Data Sheet ADP5090 SPECIFICATIONS VIN = 1.2 V, VSYS = VBAT = 3 V, TJ = −40°C to 125°C for minimum/maximum specifications and TA = 25°C for typical specifications, unless otherwise noted. External components and inductor (L) = 22 µH, CIN = 4.7 µF, CSYS = 4.7 µF. Table 1. Parameter COLD-START CIRCUIT Minimum Input Voltage for Cold-Start Minimum Input Power for Cold-Start End of Cold-Start Operation Threshold End of Cold-Start Operation Hysteresis BOOST REGULATOR Input Voltage Operation Range Input Power Operation Range Input Peak Current Low-Side Switch on Resistance High-Side Switch on Resistance SYS Switch on Resistance DIS_SW High Voltage DIS_SW Low Voltage DIS_SW Delay VIN CONTROL AND REGULATION VIN Open Circuit Voltage Sampling Cycle VIN Open Circuit Voltage Sampling Time MINOP Bias Current MINOP Operation Voltage Range ENERGY STORAGE MANAGEMENT Operating Quiescent Current of SYS Pin Sleeping Quiescent Current of SYS Pin Internal Reference Voltage Battery Stop Discharging Threshold Battery Stop Discharging Hysteresis Resistor Battery Terminal Charging Threshold Battery Terminal Charging Hysteresis PGOOD Falling Threshold at SYS Pin PGOOD Hysteresis Resistor at SYS Pin PGOOD Pull-Up Resistor PGOOD Pull-Down Resistor Battery Switch on Resistance Battery Current Capability Leakage Current at BAT Pin BACK_UP POWER PATH BACK_UP Switches on Resistance BACK_UP and BAT Comparator Offset BACK_UP and BAT Comparator Hysteresis BACK_UP Current Capability Leakage Current at BACK_UP Pin THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Symbol Test Conditions/Comments VIN_COLD PIN_COLD VSYS_TH VSYS_HYS VSYS = 0 V, 0°C < TA < 85°C VIN PIN IIN_PEAK Cold-start completed Cold-start completed, VIN = 0.5 V Factory trim, 1 bit (Option 0) Factory trim, 1 bit (Option 1) 1.8 RLS_DS_ON RHS_DS_ON RSYS_DS_ON DIS_SWHIGH DIS_SWLOW tDIS_DELAY RBKP_SW_ON VBKP_OFFSET VBAT_HYS IBKP IBKP_LEAK TSHDN THYS Max Unit 380 16 1.93 125 440 mV µW V mV 0.1 0.01 100 195 1.25 1.38 0.48 2.03 3.3 200 135 250 1.71 1.88 0.70 0.5 1 1.45 IQ_SYS IIQ_SLEEP_SYS VREF VBAT_SD RBAT_SD_HYS VBAT_TERM VBAT_TERM_HYS VSYS_PG RSYS_PG_HYS Typ 1 TVOC_CYCLE TVOC_SAMPL IMINOP VMINOP RBAT_SW_ON IBAT IBAT_LEAK Min VIN > VCBP ≥ VMINOP, VSYS > VBAT_SD VCBP < VMINOP, VSYS > VBAT_SD 1.14 2 65 2.2 19 296 2 320 260 1.21 103.5 3 VBAT_SD 65 VBAT = 2 V, VBAT_SD = 2.2 V, VSYS = 2 V VBAT = 3.3 V, VBAT_SD = 2.2 V, VSYS = 0 V VSYS = VBACK_UP = 3 V VSYS ≥ VSYS_TH VSYS ≥ VSYS_TH VSYS ≥ VSYS_TH Plug in the backup battery first VBACK_UP = VSYS = VBAT = 3 V VSYS ≥ VSYS_TH Rev. C | Page 3 of 21 103.5 11.8 11.8 0.55 15 0.5 135 55 1.18 185 75 400 250 6 125 15 V mW mA mA Ω Ω Ω V V μs 2.55 1 s ms μA V 580 480 1.28 VBAT_TERM 150 5.2 3.7 VBAT_TERM 150 17 17 0.73 800 50 20 nA nA V V kΩ V % V kΩ kΩ kΩ Ω mA nA nA 1.60 250 100 520 Ω mV mV mA µA nA 18 °C °C ADP5090 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter VIN, MPPT, CBP, MINOP DIS_SW, TERM, SETPG, SETSD, PGOOD, REF to AGND SW, SYS, BAT, BACK_UP to PGND PGND to GND Rating −0.3 V to +3.6 V −0.3 V to +6.0 V θJA is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. −2.0 V to +6.0 V −0.3 V to +0.3 V Package Type 16-Lead LFCSP Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 3. ESD CAUTION Rev. C | Page 4 of 21 θJA 53.1 θJC 4.55 Unit °C/W Data Sheet ADP5090 13 PGOOD 14 DIS_SW 16 SETPG 15 REF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SETSD 1 12 BACK_UP TERM 2 ADP5090 11 SYS AGND 3 TOP VIEW 10 BAT VIN 7 PGND 8 CBP 6 MPPT 5 SW NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 12263-002 9 MINOP 4 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic SETSD TERM AGND MINOP 5 MPPT 6 CBP 7 VIN 8 9 PGND SW 10 11 12 13 14 BAT SYS BACK_UP PGOOD DIS_SW 15 REF 16 SETPG EPAD Description Shutdown Setting. This pin sets the shutdown discharging voltage based on the BAT node voltage level. Termination Charging Voltage. This pin sets the terminal charging voltage based on the BAT node voltage level. Analog Ground. Connect the exposed pad to the analog ground on the board. Minimum Operating Power. Place a resistor on this pin to set the minimum operation input voltage level. The boost regulator starts switching after the CBP voltage exceeds the MINOP voltage. Connect this pin to AGND to disable MINOP function. Maximum Power Point Tracking. This pin sets the maximum power point tracking level for different energy harvesters. To disable MPPT, float this pin. Capacitor Bypass. Samples and holds the maximum power point level. Connect a 10 nF capacitor from this pin to AGND. When MPPT is disabled, tie CBP to an external reference that is lower than VIN. Input Supply from Energy Harvester Source. Connect at least a 4.7 μF capacitor as close as possible between this pin and PGND. Power Ground. Switching Node for the Inductive Boost Regulator with a Connection to the External Inductor. Connect a 22 μH inductor between this pin and VIN. Places Rechargeable Battery or Super Capacitor as a Storage for SYS Output Supply. Output Supply to System Load. Connect at least a 4.7 μF capacitor as close as possible between this pin and PGND. Optional Input Supply from the Backup Primary Battery Cell. Output Supply. Maintain a logic high signal when SYS voltage is higher than the SETPG threshold. Control Signal from the MCU or RF Transceiver. Stop the main boost switching by pulling this pin high. Enable the main boost switching by pulling this pin low. Provides Bias Voltage for the SETSD, TERM, and SETPG Pins. Connect the high side of the resistor divider networks to this bias voltage. Sets Power Good Voltage Based on the SYS Node Voltage Level. Exposed Pad. The exposed pad must be connected to AGND. Rev. C | Page 5 of 21 ADP5090 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 100 90 90 80 80 70 70 60 50 SYS = 2V SYS = 3V SYS = 5V 50 30 30 20 20 10 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 INPUT VOLTAGE (V) SYS = 2V SYS = 3V SYS = 5V 40 0 0 Figure 6. Efficiency vs. Input Voltage, IIN = 100 μA 80 90 70 80 60 EFFICIENCY (%) 100 70 60 SYS = 2V SYS = 3V SYS = 5V 50 50 40 20 30 10 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 INPUT VOLTAGE (V) SYS = 2V SYS = 3V SYS = 5V 30 40 0 0.01 12263-004 EFFICIENCY (%) Figure 3. Efficiency vs. Input Voltage, IIN = 10 μA 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 INPUT VOLTAGE (V) 0.1 1 10 INPUT CURRENT (mA) Figure 4. Efficiency vs. Input Voltage, IIN = 10 mA 12263-007 40 60 12263-006 EFFICIENCY (%) 100 12263-003 EFFICIENCY (%) IVIN = 5 mA, VBAT_TERM = 3.5 V, VSYS_PG = 3.0 V, VBAT_SD = 2.4 V, MPPT ratio (OCV) = 80%, L = 22 μH, CIN = CSYS = 4.7 μF, CCBP= 10 nF. Figure 7. Efficiency vs. Input Current, VIN = 0.2 V 90 90 85 80 80 EFFICIENCY (%) 75 SYS = 2V SYS = 3V SYS = 5V 60 50 SYS = 2V SYS = 3V SYS = 5V 70 65 60 55 40 50 30 20 0.01 0.1 1 10 INPUT CURRENT (mA) 100 40 0.01 0.1 1 10 INPUT CURRENT (mA) Figure 5. Efficiency vs. Input Current, VIN = 0.5 V Figure 8. Efficiency vs. Input Current, VIN = 1 V Rev. C | Page 6 of 21 100 12263-008 45 12263-005 EFFICIENCY (%) 70 Data Sheet ADP5090 100 90 95 80 70 SYS = 3V SYS = 5V 85 EFFICIENCY (%) 80 75 60 0.01 20 0.01 0.1 1 10 100 VIN = 0.5V, SYS = 3V VIN = 0.5V, SYS = 5V 0.1 1 10 100 INPUT CURRENT (mA) Figure 9. Efficiency vs. Input Current, VIN = 2 V 12263-212 30 12263-009 65 INPUT CURRENT (mA) Figure 12. ADP5090ACPZ-2-R7 Efficiency vs. Input Current, VIN = 0.5 V 90 100 80 95 90 EFFICIENCY (%) 70 60 50 40 85 80 75 70 30 65 VIN = 1V, SYS = 3V VIN = 1V, SYS = 5V 0.1 1 10 100 INPUT CURRENT (mA) 60 0.01 12263-210 20 0.01 VIN = 2V, SYS = 3V VIN = 2V, SYS = 5V 0.1 1 10 100 INPUT CURRENT (mA) 12263-213 EFFICIENCY (%) 50 40 70 Figure 13. ADP5090ACPZ-2-R7 Efficiency vs. Input Current, VIN = 2 V Figure 10. ADP5090ACPZ-2-R7 Efficiency vs. Input Current, VIN = 1 V 400 500 QUIESCENT CURRENT (nA) +125°C +85°C +25°C –40°C 450 400 350 300 250 +125°C +85°C +25°C –40°C 350 300 250 200 200 150 150 100 2.0 2.4 2.8 3.2 3.6 4.0 SYS VOLTAGE (V) 4.4 4.8 5.2 100 12263-111 QUIESCENT CURRENT (nA) 60 2.0 2.4 2.8 3.2 3.6 4.0 SYS VOLTAGE (V) 4.4 4.8 5.2 Figure 14. Quiescent Current vs. SYS Voltage (VMPPT < VMINOP) Figure 11. Quiescent Current vs. SYS Voltage (VMPPT ≥ VMINOP) Rev. C | Page 7 of 21 12263-214 EFFICIENCY (%) 90 ADP5090 Data Sheet 8 25 BACK_UP LEAKAGE CURRENT (nA) +125°C +85°C +25°C –40°C 20 15 10 5 6 5 4 +125°C +85°C +25°C –40°C 3 2 2.8 3.2 3.6 4.0 BAT VOLTAGE (V) 4.4 4.8 5.2 0 2.0 2.4 2.8 3.2 3.6 4.0 BACK_UP VOLTAGE (V) 4.4 4.8 5.2 Figure 18. BACK_UP Leakage Current vs. BACK_UP Voltage Figure 15. BAT Leakage Current vs. BAT Voltage VIN VIN 1 1 BAT SYS SYS BAT 2 SW 4 12263-110 4 CH1 1.00V BW CH3 1.00V BW CH2 1.00V BW CH4 2.00V BW M100ms A CH2 SW CH1 1.00V BW CH3 1.00V BW 1.02V 12263-114 2 CH2 1.00V BW CH4 2.00V M40.0ms A CH2 1.02V Figure 19. Startup with Empty 100 μF Battery Figure 16. Startup with 100 μF Battery, VBAT > VBAT_SD VIN VIN 1 1 BAT SYS BAT SYS 2 2 4 4 SW CH1 1.00V BW CH3 1.00V BW CH2 1.00V BW CH4 2.00V BW M20.0ms A CH2 12263-014 PGOOD CH1 500mV BW CH2 1.00V BW CH3 1.00V BW CH4 2.00V BW 1.02V M200ms A CH4 Figure 20. PGOOD Function Waveform Figure 17. Startup with 100 μF Battery, VBAT < VBAT_SD Rev. C | Page 8 of 21 920mV 12263-112 2.4 12263-109 0 2.0 7 1 12263-113 BAT LEAKAGE CURRENT (nA) 30 Data Sheet ADP5090 VIN 1 VIN CH2: SYS (AC) 3 1 SYS CH3: BAT (AC) BAT 2 SW 3 SW B CH2 50.0mV B CH1 1.00V W M20.0ms A CH3 W T 30.40% CH3 50.0mV BW CH4 2.00V 12263-119 4 12263-022 4 CH1 500mV BW CH2 2.00V BW CH3 2.00V BW CH4 5.00V 5.00mV Figure 21. Output Ripple of TERM Function with 100 μA Load M4.00s A CH2 1.04V Figure 24. MPPT Sampling Cycle Waveform VIN 1 VIN SYS 1 BAT BAT BACK_UP 3 SW SYS CH1 500mV BW CH2 2.00V BW CH3 2.00V BW CH4 2.00V M100µs A CH4 12263-021 2 12263-117 4 CH1 500mV BW CH2 1.00V BW CH3 1.00V BW CH4 1.00V BW 2.20V Figure 22. Main Boost PFM Waveform with 200 μA Load M2.00s A CH2 1.90V Figure 25. Backup Function, VBACK_UP < VBAT VIN VIN 1 BAT 1 SYS MINOP SYS 3 2 SW 2 CH1 500mV BW CH2 1.00V BW CH3 1.00V BW CH4 2.00V M400µs A CH2 SW 12263-020 4 12263-118 4 CH1 1.00V BW CH2 1.00V BW CH3 1.00V BW CH4 2.00V BW 1.88V Figure 23. Battery Protection Function Waveform M100ms T 20.20% A CH1 Figure 26. MINOP Function Waveform Rev. C | Page 9 of 21 1.26V ADP5090 Data Sheet VIN 1 VIN SYS 1 BAT BACK_UP DIS_SW 3 2 SW SYS CH1 500mV BW CH2 1.00V BW CH3 1.00V BW CH4 1.00V BW M2.00s A CH2 12263-023 4 12263-018 2 CH1 500mV BW CH2 1.00V BW CH3 2.00V BW CH4 2.00V BW 1.90V Figure 27. Backup Function, VBACK_UP > VBAT M100ms T 20.20% A CH3 Figure 28. DIS_SW Function Waveform Rev. C | Page 10 of 21 1.00V Data Sheet ADP5090 DETAILED FUNCTIONAL BLOCK DIAGRAM BACK_UP_M1 BACK_UP ADP5090 SYS RSYS BACK_UP_M2 CSYS SYS SWITCH SW SDB – CIN VIN BAT COLD-START CHARGE PUMP PG REF SYS ROC2 MPPT MPPT CONTROLLER TERM_REF ROC1 EN_BST CBP BOOST CONTROLLER SETSD SDB BATTERY BOOST CONTROL PGOOD MINOP SETPG PG SYS DIS_SW CLK – BAT + BAT SWITCH BSTO HS + VREF TERM_REF TRM BIAS REFERENCE AND OSCILLATOR TERM CONTROL TERM 2R R PGND AGND Figure 29. Detailed Functional Block Diagram Rev. C | Page 11 of 21 BAT 12263-024 PHOTOVOLTAIC CELL ADP5090 Data Sheet THEORY OF OPERATION The ADP5090 combines a nano powered boost regulator with a storage elements management controller. It converts power from low voltage, high impedance dc sources such as PV cells, TEGs, and piezoelectric modules. The device stores power in the rechargeable battery or capacitor with storage protection, and provides power to the load. It can also control an additional power path from a primary battery cell to the system. The ADP5090 includes a cold start up circuit, a synchronous boost controller with integrated MOSFETs, a charge controller with an integrated switch, and switches for the backup power path. The boost can be stopped temporarily by an external signal to prevent interference with RF transmission. VIN OPEN CIRCUIT AND MPPT The boost regulation reference is the VIN pin open circuit voltage scaled to a ratio programmed by the resistor divider at the MPPT pin. This voltage is periodically sampled and stored in the capacitor connected to the CBP pin. This storage keeps the VIN voltage operating at the level of maximum power points available from the energy harvester at the input of the ADP5090. The reference voltage refreshes every 19 sec by periodically disabling the boost regulator for 296 ms and sampling the open circuit voltage. The reference voltage is set by the following equation: ROC1 VMPPT = VIN (Open Circuit ) R OC1 + ROC2 COLD STARTUP (VSYS < VSYS_TH, VIN > VIN_COLD) The cold startup circuit is required when the VIN pin is above VIN_COLD, and the energy storage voltage at the SYS pin is below VSYS_TH, above which the boost regulator and energy storage controller start working. The charge-pump cold startup circuit extracts the energy available at the VIN pin and charges the capacitors at the SYS pin and the BAT pin up to VSYS_TH. The energy harvester must supply sufficient power to complete cold startup (see the Energy Harvester Selection section for more information). The cold start circuit, with lower efficiency compared to the boost regulator, can achieve a short startup time, creating a low shutdown current system load enabled by the PGOOD signal. To bypass the cold startup, place a primary battery at the BACK_UP pin (see the Backup Storage Path section for more information). BOOST REGULATOR (VBAT_TERM > VSYS ≥ VSYS_TH) The switching mode synchronous boost regulator, with an external inductor connected between the VIN and SW pins, operates in pulse frequency mode (PFM), transferring energy stored in the input capacitor to the system load (SYS) and energy storage connected to the BAT pin. The boost control loop regulates the VIN voltage at the level sampled at the MPPT pin and stored at the capacitor connected to the CBP pin. To maintain the high efficiency of the regulator across a wide input power range, the current sense circuitry employs the internal dither peak current limit to control the inductor current. The boost regulator operation turns off the SYS and BAT switches as an asynchronous mode via the energy storage controller when the BAT pin voltage is below the battery discharging protection threshold programmed at the SETSD pin, or stops switching when the BAT pin voltage is above the battery overcharging threshold programmed at the TERM pin. The boost regulator is disabled when the voltage of the CBP pin decreases to the threshold set by the resistor at the MINOP pin. In addition, the boost is periodically stopped by the open voltage sampling circuit, and can be temporary disabled by driving the DIS_SW pin high. (1) The typical MPPT ratio depends on the type of harvester. For example, it is around 0.8 for PV cells, and 0.5 for TEGs. The MPPT can be disabled and left floating. Set the CBP pin to an external voltage reference lower than the VIN voltage. If the input source is an ideal voltage source, connect the MPPT and CBP pins to ground. ENERGY STORAGE CHARGE MANAGEMENT Energy storage is connected to the BAT pin. The storage can be a rechargeable battery, super capacitor, or 100 μF or larger capacitor. The energy storage controller manages the charging and discharging operations, monitors the SYS pin voltage, and asserts the PGOOD signal high when it is above the threshold programmed at the SETPG pin. When the BAT pin voltage exceeds the charging protection threshold programmed at the TERM pin, the boost operation terminates to prevent battery overcharging. The overcharging protection threshold is programmable from 2.2 V to 5.2 V. When the BAT voltage drops below the discharging protection threshold level programmed at SETSD pin, the switches between the BAT pin and SYS pin are opened to prevent a deep, destructive battery discharge, and the boost reaches asynchronous mode. Although there is no current limit at the SYS and BAT pins, it is recommended to limit the system load current to lower than 800 mA. The large system load current generates a droop between the SYS pin and the rechargeable battery at the BAT pin, with consideration given to the resistance of the SYS switch, the BAT switch, and the rechargeable battery internal resistance. When no input source is attached, discharge the SYS pin to ground before attaching a storage element to the BAT pin. After hot plugging a charged storage element, release the SYS pin because the SYS voltage below VSYS_TH results in the BAT switch remaining off to protect the storage element until the SYS voltage reaches VSYS_TH. This can be described as store mode, a state with the lowest leakage (0.5 nA, typical) that allows a long store period without discharging the storage element on BAT. Rev. C | Page 12 of 21 Data Sheet ADP5090 BACKUP STORAGE PATH The ADP5090 provides an optional backup storage energy path, an integrated backup controller, and two back to back power switches between the BACK_UP pin and the SYS pin. When the system operates at a condition where the harvested and stored energy is periodically insufficient, a backup energy storage element can be attached to the BACK_UP pin. The backup controller enables when the SYS voltage is above 1.5 V (typical). When the BACK_UP pin voltage is higher than the BAT pin voltage, it turns on the internal power switches between the BACK_UP pin and the SYS pin. When the BACK_UP pin voltage is lower than the BAT pin voltage, the internal power switches are turned off. The 185 mV (typical) comparator input offset of the BAT pin prevents the input source and BAT pin charging the BACK_UP pin (see Figure 32). Considering the quiescent current consumption, the sum of the resistors must be more than 6 MΩ, that is, RTERM1 + RTERM2 ≥ 6 MΩ The overvoltage falling threshold is given by VBAT_TERM_HYS, which is internally set to the overvoltage threshold minus an internal hysteresis voltage denoted by VBAT_TERM_HYS. When the voltage at the battery exceeds the VBAT_TERM threshold, the main boost regulator is disabled. The main boost starts again when the battery voltage falls below the VBAT_TERM_HYS level. When the input energy is excessive, the VBAT pin voltage ripples between the VBAT_TERM and the VBAT_TERM_HYS levels. TERMS TERM_REF SDB In addition, the backup storage element can bypass the cold startup with inrush current protection circuitry. When the system current exceeds the internal current limit of 400 mA (typical), the BACK_UP switches turn off. Nevertheless, the current capability is only 250 µA (typical) when plugging in the backup battery for the first time. Restricting the system load current from the SYS pin ensures that the power path can enter normal operation status. Table 6 explains the power path working state. For long-term store mode, remove the backup storage element and then discharge SYS to ground. BAT RE RBAT_SD_HYS PG REF PGS SYS RSYS_PG_HYS RSD1 RPG1 RTERM1 RSD2 RPG2 RTERM2 SETSD SDB STEPG PG MINOP FUNCTION VREF TERM_REF DISABLING BOOST For noise or EMI sensitive applications, the boost switcher can be stopped temporarily by pulling the DIS_SW pin high to prevent interference with RF circuits. The boost switching resumes when the DIS_SW pin is pulled low. The transition delay is less than 1 μs (typical). BATTERY OVERCHARGING PROTECTION To prevent rechargeable batteries from being overcharged and damaged, the battery terminal voltage (VBAT_TERM) must be set by using external resistors. Figure 30 shows the VBAT_TERM rising threshold voltage given by Equation 2. (2) TRM TERM TERM CONTROL 2R R 12263-025 When the energy generated by the harvester cannot sustain the steady working state, the MINOP function can disable the boost regulator to prevent discharging the storage element. The MINOP function disables the MPPT function to achieve the lowest quiescent current of 260 nA (typical). When the voltage of the CBP pin decreases to the threshold set by the resistor at the MINOP pin, the boost regulator stops switching. Disable this function by connecting MINOP to AGND. The typical MINOP bias current is 2 μA. R 3 VBAT _ TERM = VREF 1 + TERM1 2 RTERM2 SDS BAT Figure 30. The ADP5090 Program Paramater Setting BATTERY DISCHARGING PROTECTION To prevent rechargeable batteries from being deeply discharged and damaged, the battery discharge shutdown voltage (VBAT_SD) must be set by using external resistors. Figure 30 shows the VBAT_SD falling threshold voltage given by Equation 3. R VBAT _ SD = VREF 1 + SD1 RSD2 (3) The ADP5090 has an internal resistor, RBAT_SD_HYS = 103.5 kΩ (typical), to program the hysteresis, given by Equation 4. VBAT _ SD _ HYS = VBAT _ SD × R BAT _ SD _ HYS RE (4) where VBAT_SD_HYS contains an internal resistor to program the hysteresis. Considering the quiescent current consumption, the sum of the resistors that comprise the resistor divider (RBAT_SD_HYS, RSD1, and RSD2) must be more than 6 MΩ, that is, RBAT_SD_HYS + RSD1 + RSD2 ≥ 6 MΩ Rev. C | Page 13 of 21 ADP5090 Data Sheet POWER GOOD (PGOOD) The ADP5090 allows users to set a programmable PGOOD voltage (VPGOOD) threshold, which indicates the SYS voltage is at an acceptable level. It must be set using external resistors. Figure 30 shows the VPGOOD falling threshold voltage given by Equation 5. R VSYS _ PGOOD = VREF 1 + PG1 RPG 2 For the best operation of the system, set up PGOOD to drive an external PFET between SYS and the system load via an inverter in order to determine when the load can be connected or removed to optimize the storage element capacity (see Figure 36). It is necessary to complete the cold start-up if the system load cannot be disabled. Table 5 shows programming threshold resistor examples corresponding to various voltages with a 10 MΩ resistor divider. Figure 31 shows states of various threshold voltages. MAXIMUM DEVICE RATING VOLTAGE (5) TURN OFF MAIN BOOST The ADP5090 has an internal resistor to program the hysteresis, RSYS_PG_HYS = 103.5 kΩ (typical), given by Equation 6. RE VBAT_TERM (6) where VSYS_PGOOD_HYS is the PGOOD hysteresis voltage. The equivalent resistor of the three external configuration resistor dividers, RE, is recommended to be comprised of the same three resistor dividers for easy resistor selection. Considering the quiescent current consumption, the sum of the resistors that comprise the power good resistor divider (RSYS_PG_HYS, RPG1, and RPG2) must be more than 6 MΩ, that is, RSYS_PG_HYS + RPG1 + RPG2 ≥ 6 MΩ VBAT_TERM_HYS INCREASING SYS VOLTAGE VSYS _ PGOOD _ HYS = VSYS _ PGOOD × RSYS _ PG _ HYS MAIN BOOST CHARGER OFF PGOOD BECOMES HIGH VBAT_PG_HYS VBAT_PG MAIN BOOST IN SYNCHRONOUS MODE TURN ON SWITCH BETWEEN BSTO AND BAT MAIN BOOST CHARGER ON VBAT_SD_HYS VBAT_SD TURN ON MAIN BOOST IN ASYNCHRONOUS MODE VSYS_TH (7) The logic high level on PGOOD is equal to the SYS voltage and the logic low level is ground. The logic high level has approximately 11.8 kΩ (typical) internally in series to limit the available current. The VPGOOD threshold must be greater than or equal to the VBAT_SD threshold. VSYS_TH ENABLE CHIP COLD-STARTUP 0V 12263-026 The equivalent resistor of the three external configuration resistor dividers, RE, is equivalent to the paralleling value of the three resistor dividers. Figure 31. States of Various Threshold Voltages Table 5. Programming Threshold Resistors Voltage Threshold (V) 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 RSD1 and RPG1 (MΩ) 3.92 4.22 4.53 4.75 4.99 5.11 5.36 5.49 5.62 5.76 5.9 6.04 6.2 6.34 6.49 6.49 6.65 6.8 6.81 6.98 RSD2 and RPG2 (MΩ) 6.04 5.76 5.49 5.23 5 4.87 4.64 4.53 4.32 4.22 4.02 3.9 3.74 3.65 3.57 3.48 3.4 3.3 3.2 3.09 Rev. C | Page 14 of 21 RTERM1 (MΩ) Not applicable Not applicable 1.74 2.1 2.43 2.74 3.01 3.3 3.48 3.74 3.92 4.12 4.32 4.53 4.64 4.87 4.99 5.1 5.23 5.36 RTERM2 (MΩ) Not applicable Not applicable 8.25 7.87 7.5 7.32 6.98 6.65 6.49 6.2 6.04 5.9 5.62 5.49 5.36 5.23 5 4.87 4.75 4.64 Data Sheet ADP5090 Voltage Threshold (V) 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 RSD1 and RPG1 (MΩ) 6.98 6.98 7.15 7.15 7.32 7.32 7.32 7.5 7.5 7.5 7.5 7.68 7.68 RSD2 and RPG2 (MΩ) 3.01 2.94 2.87 2.8 2.74 2.7 2.61 2.55 2.5 2.49 2.43 2.37 2.32 RTERM1 (MΩ) 5.49 5.6 5.62 5.76 5.9 5.9 6.04 6.19 6.2 6.34 6.34 6.49 6.49 RTERM2 (MΩ) 4.53 4.42 4.32 4.22 4.12 4.02 3.92 3.83 3.74 3.74 3.65 3.57 3.48 Table 6. Power Path Working State Power Path Without Backup Battery With Backup Battery Power Condition VSYS > VSYS_TH, VBAT_SD > VBAT VBAT_TERM > VBAT = VSYS > VBAT_SD VSYS > VSYS_TH, VBAT > VBAT_TERM VSYS > VSYS_TH, VBACK_UP > VBAT > VBAT_SD VSYS > VSYS_TH, VBACK_UP > VBAT_SD > VBAT 1.5 V < VSYS < VSYS_TH, VSYS < VBACK_UP VSYS < 1.5 V Main Boost Asynchronous Synchronous Disabled Synchronous Asynchronous Disabled Disabled BAT Switch Off On On On Off Off Off SYS Switch Off On On Off Off Off Off BACK_UP_M1 Off Off Off On On On Off BACK_UP_M2 Off Off Off On On On Off POWER PATH WORKING FLOW CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION Figure 32 shows the power switches structure when the backup primary battery is implemented. When the BACK_UP voltage is higher than the BAT voltage, the SYS switch prevents the BACK_UP primary battery from charging the BAT pin. Meanwhile, the BAT offset avoids input source charging BACK_UP primary battery. Table 6 shows the power path working state. The boost regulator in the ADP5090 includes current-limit protection circuitry to limit the amount of positive current flowing through the low-side boost switch. It is a cycle-by-cycle, three level peak current-limit protection with a third level of 100 mA (typical). D1 BACK_UP_M1 BACK_UP + – BACK_UP_M2 SYS The BACK_UP power path current limit of 400 mA (typical) protects the primary battery sinking large current. When the current from the BACK_UP pin is higher than the current limit, the BACK_UP switches turn off. SYS_SWITCH BAT_SWITCH HS BSTO BAT + THERMAL SHUTDOWN – LS GATE DRIVER GATE DRIVER Figure 32. Power Switches Structure 12263-027 SW Although there is no current limit at the SYS and BAT pins, it is recommended to limit the system load current to lower than 800 mA. The total resistance of the SYS switch and the BAT switch (1.03 Ω, typical), generates a voltage drop when the system load sinks a large current from BAT. It is necessary to consider the internal resistance of the storage elements connected to the BAT pin. In the event that the ADP5090 junction temperature rises above 125°C, the thermal shutdown (TSD) circuit turns off the switch between the BAT pin and the SYS pin to prevent the damage of energy storage at a high ambient temperature. The boost operation is also terminated. A 15°C hysteresis is included, allowing the ADP5090 to return to operation when the on-chip temperature drops below 110°C. When coming out of TSD, the boost regulator and the energy storage controller resume the functions. Rev. C | Page 15 of 21 ADP5090 Data Sheet APPLICATIONS INFORMATION The ADP5090 extracts the energy from the VIN pin to charge the SYS and BAT pins. This occurs in three stages: cold start, asynchronous boost, and synchronous boost. This section describes the procedures for selecting the external components to maintain the energy transmission system with the layout and assembly consideration. ENERGY HARVESTER SELECTION The energy harvester input source must provide a minimum level of power for cold start, asynchronous boost, and synchronous boost. The minimum input power required to complete cold start can be estimated using the following equation: VIN × IIN × ηCOLD > VSYS_TH × (ISTR_LEAK + ISYS_LOAD) where: VIN is clamped to VIN_COLD = 380 mV (typical), which indicates cold start real input power. IIN is the input current. ηCOLD is the cold start efficiency, which is about 5% to 7%. VSYS_TH is the current with the bias voltage, and an estimation of worst case. ISTR_LEAK is the storage element leakage current at the BAT pin. ISYS_LOAD is the system load current of the SYS pin. Minimizing the system load accelerates the cold start. Programming the PGOOD threshold to enable the system load current is recommended. After the ADP5090 completes the cold start, the MPPT function enables. To meet the average system load current, the input source must provide the boost regulator with enough power to charge the storage element fully while the system is in low power or sleep mode. The power required by the system can be estimated using the following equation: VIN × IIN × ηBOOST > VBAT_TERM × (ISTR_LEAK + ISYS_LOAD) where: VIN is regulated to the CBP pin voltage (MPPT ratio × OCV). IIN is the input current. ηBOOST is the boost regulator efficiency. See the efficiency figures in the Typical Performance Characteristics section for more information. VBAT_TERM is the current with the bias voltage, and an estimation of worst case. ISTR_LEAK is the storage element leakage current at the BAT pin. ISYS_LOAD is the average system load current of the SYS pin. ENERGY STORAGE ELEMENT SELECTION In order to protect the storage element from overcharging or overdischarging, the storage element must be connected to the BAT pin and the system load tied to the SYS pin. The ADP5090 supports many types of storage elements, such as rechargeable batteries, super capacitors, and conventional capacitors. A storage element with a 100 μF equivalent capacitance is required to filter the pulse currents of the PFM switching converter. The storage element capacity must provide the entire system load when the input source is no longer generating power. If there is high pulse current or the storage element has significant impedance, it may be necessary to increase the SYS capacitor from the 4.7 μF minimum, or add additional capacitance to the BAT pin in order to prevent a droop in the SYS voltage. Note that increasing the SYS capacitor causes the boost regulator to operate in the less efficient cold start stage for a longer period at startup. If the application cannot accept the longer cold start time, place the additional capacitor parallel to the storage element. See the Capacitor Selection section for more information. INDUCTOR SELECTION The boost regulator needs an appropriate inductor for proper operation. The inductor saturation current must be at least 30% higher than the expected peak inductor currents, as well as a low series resistance (DCR) to maintain high efficiency. The boost regulator internal control circuitry is designed to optimize the efficiency and control the switching behavior with a nominal inductance of 22 μH ± 20%. Table 7 lists some recommended inductors. Table 7. Recommended Inductors Vendor Würth Elektronik Coilcraft Device No. 74437324220 744042220 LPS4018-223M L (µH) 22 22 22 ISAT (A) 2 0.6 0.8 IRMS (A) 1 0.88 0.65 DCR (mΩ) 470 255 360 CAPACITOR SELECTION Low leakage capacitors are required for ultralow power applications that are sensitive to the leakage current. Any leakage from the capacitors reduces efficiency, increases the quiescent current, and degrades the MPPT effectiveness. Input Capacitor A capacitor CIN connected to the VIN pin and the PGND pin stores energy from the input source. For the energy harvester, the source impedance is dominated by capacitive behavior. Scale the input capacitor according to the value of the output capacitance of the energy harvester; a minimum of 4.7 μF is recommended. For the primary battery as an input source application, a larger capacitance helps to reduce the input voltage ripple and keep the source current stable in order to extend the battery life. SYS Capacitor The ADP5090 requires two capacitors to be connected between the SYS pin and the PGND pin. Connect a low ESR ceramic capacitor of at least 4.7 μF parallel to a high frequency bypass capacitor of 0.1 μF. Connect the bypass capacitor as close as possible between SYS and PGND. Rev. C | Page 16 of 21 Data Sheet ADP5090 CBP Capacitor The operation of the MPPT pin depends on the sampled value of the OCV. The VIN pin is regulated to the voltage stored on the CBP capacitor. This capacitor is sensitive to leakage because the holding period is around 19 sec. As the capacitor voltage drops due to leakage, the VIN regulation voltage also drops and influences the effectiveness of MPPT. When the IC junction temperature exceeds 85°C, the leakage current of the CBP pin significantly increases so that a larger capacitance is beneficial to the effectiveness of the MPPT. It is recommended to keep the same RC time constant of the MPPT resistors and CBP capacitor (up to 220 nF) as the typical application circuit in Figure 33. Considering the time constant of the MPPT resistor divider and the CBP capacitor, a low leakage X7R or C0G 10 nF ceramic capacitor is recommended. LAYOUT AND ASSEMBLY CONSIDERATIONS Carefully consider the printed circuit board (PCB) layout during the design of the switching power supply, especially at high peak currents and high switching frequency. Therefore, it is recommended to use wide and short traces for the main power path and the power ground paths. Place the input capacitors, output capacitors, inductor, and storage elements as close as possible to the IC. It is most important for the boost regulator to minimize the power path from output to ground. Therefore, place the output capacitor as close as possible between the SYS pin and the PGND pin. Keep a minimum power path from the input capacitor to the inductor from the VIN pin to the PGND pin. Place the input capacitor as close as possible between the VIN pin and the PGND pin, and place the inductor close to the VIN pin and the SW pin. It is best to use vias and bottom traces for connecting the inductors to their respective pins. To minimize noise pickup by the high impedance threshold setting nodes (REF, TERM, SETSD, and SETPG), place the external resistors close to the IC with short traces. The CBP capacitor must hold the MPPT voltage for 19 sec, as any leakage can degrade the MPPT effectiveness. During board assembly and cleaning, contaminants such as solder flux and residue may form parasitic resistance to ground, especially in humid environments with fast airflow. This can significantly degrade the voltage regulation and change threshold levels set by the external resistors. Therefore, it is recommended that no ground planes be poured near the CBP capacitor or the threshold setting resistors. In addition, the boards must be carefully cleaned. If possible, clean ionic contamination with deionized water for the CBP capacitor and the threshold setting resistors. Rev. C | Page 17 of 21 ADP5090 Data Sheet TYPICAL APPLICATION CIRCUITS PGOOD 22µH SOLAR HARVESTER SYS SW 4.7µF 4.7µF ADP160/ ADP161 SENSOR VIN 6.34MΩ BAT + MPPT 14.7MΩ – PAS409HR 0.03F 3.3V 12µAh CBP 10nF ADP5090 MCU (ALWAYS ON) REF BACK_UP CR2032 3V 225mAh DIS_SW SETSD MINOP SETPG 20kΩ ADF7xxx TERM (Rx/Tx) PGND 12263-028 AGND Figure 33. ADP5090 Based Energy Harvester Wireless Sensor Application with PV Cell as the Harvesting Energy Source (Trony 0.7 V, 60 μA, Alta Devices 0.72 V, 42 µA, Gcell 1.1 V, 100 μA), Shoei Electronics Polyacene Coin Type Capacitor PAS409HR as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery THERMOELECTRIC GENERATOR PGOOD 22µH SYS SW + 4.7µF 4.7µF VIN 10MΩ BAT MPPT 10MΩ + – PAS409HR 0.03F 3.3V 12µAh CBP 10nF ADP5090 REF BACK_UP CR2032 3V 225mAh DIS_SW SETSD MINOP SETPG 20kΩ TERM PGND 12263-029 AGND Figure 34. ADP5090 Based Energy Harvester Circuit with a Thermoelectric Generator as the Harvesting Energy Source, Shoei Electronics Polyacene Coin Type Capacitor PAS409HR as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery Rev. C | Page 18 of 21 Data Sheet ADP5090 PIEZOELECTRIC HARVESTER PGOOD 22µH SYS SW 4.7µF 4.7µF VIN 10MΩ BAT MPPT 10MΩ + – PAS409HR 0.03F 3.3V 12µAh CBP 10nF ADP5090 REF BACK_UP CR2032 3V 225mAh DIS_SW SETSD MINOP SETPG 20kΩ TERM PGND 12263-030 AGND Figure 35. ADP5090 Based Energy Harvester Circuit with a Piezoelectric Generator as the Harvesting Energy Source, Shoei Electronics Polyacene Coin Type Capacitor PAS409HR as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery 22µH SOLAR HARVESTER SYSTEM LOAD SYS SW 4.7µF 4.7µF VIN SYS 4.7MΩ PGOOD MPPT 18MΩ BAT CBP 10nF + – ADP5090 REF BACK_UP CR2032 3V 225mAh + – DIS_SW SETSD MINOP SETPG 20kΩ TERM PGND 12263-131 AGND Figure 36. ADP5090 PGOOD Function Determines the Time to Enable the System Load Rev. C | Page 19 of 21 ADP5090 Data Sheet FACTORY PROGRAMMABLE OPTIONS To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 8. Input Peak Current Option Option 0 Option 1 Description 100 mA (default) 195 mA Rev. C | Page 20 of 21 Data Sheet ADP5090 OUTLINE DIMENSIONS 0.30 0.25 0.18 0.50 BSC 13 PIN 1 INDICATOR (0.30) 16 1 12 1.80 1.70 SQ 1.60 EXPOSED PAD 9 *0.45 TOP VIEW PKG-004087/PKG-005014 0.80 0.75 0.70 4 5 8 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4 WITH EXCEPTION TO LEAD LENGHT. 10-22-2015-B PIN 1 INDICATOR 3.10 3.00 SQ 2.90 Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-33) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP5090ACPZ-1-R7 ADP5090ACPZ-2-R7 ADP5090-1-EVALZ ADP5090-2-EVALZ 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 100 mA Current Limit 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ], 195 mA Current Limit Evaluation Board Evaluation Board with Solar Harvester Z = RoHS Compliant Part. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12263-0-12/15(C) Rev. C | Page 21 of 21 Package Option CP-16-33 CP-16-33 Branding LPN LT3