Preliminary Technical Data Ultralow Power Energy Harvester PMU with MPPT and Charge Management ADP5091/ADP5092 FEATURES PGND TYPICAL APPLICATION CIRCUIT AGND Boost regulator with maximum power point tracking (MPPT) with dynamic sensing or none-sensing mode Hysteresis mode for best ultra light load efficiency 450 nA ultralow quiescent current (CBP ≥ MINOP) 360 nA ultralow quiescent current (CBP < MINOP) Input voltage operation range from 80 mV to 3.3 V Fast cold start from 380 mV (typical) with charge pump Programmable shutdown point on MINOP pin based on input open circuit voltage (OCV) 150mA regulated output from 1.5V to 3.6V Programmable voltage monitor (2 V to 5.2 V) to support charging storage elements Optional BACK_UP power path management RF transmission friendly to shut down switcher temporarily via micro-controller (MCU) communication APPLICATIONS Photovoltaic (PV) cell energy harvesting TEG energy harvesting Industrial monitoring Self-powered wireless sensor devices Portable and wearable devices with energy harvesting Figure 1. GENERAL DESCRIPTION The ADP5091/92 is an intelligent integrated energy harvesting nano-powered management solution that converts dc power from PV cells or thermoelectric generators (TEGs).The device charges storage elements such as rechargeable Li-Ion batteries, thin film batteries, super capacitors, or conventional capacitors, and powers up small electronic devices and battery-free systems. The ADP5091/92 provides efficient conversion of the harvested limited power from a 16 μW to 600 mW range with sub-μW operation losses. With the internal cold-start circuit, the regulator can start operating at an input voltage as low as 380 mV. After cold startup, the regulator is functional at an input voltage range of 80 mV to 3.3 V. An additional 150mA regulated output can be programmed by an external resistor divide or VID pin. By sensing the input voltage, the control loop keeps the input voltage ripple in a fixed range to maintain stable dc-to-dc boost conversion. The OCV dynamic sensing mode and none-sensing mode both programming regulation points of the input voltage allow extraction of the highest possible energy from the harvester. A programmable minimum operation threshold Rev. PrA (MINOP) enables boost shutdown during a low light condition. As a low light indicator for microprocessor, the LLD is the MIONP comparator output. In addition, the DIS_SW pin can temporarily shut down the boost regulator and is RF transmission friendly. The charging control function of ADP5091/92 protects rechargeable energy storage, which is achieved by monitoring the battery voltage with programmable charging termination voltage and shutdown discharging voltage. In addition, a programmable PGOOD flag with programmable hysteresis monitors the SYS voltage. An optional primary cell battery can be connected and managed by an integrated power path management control block that is programmable to switch the power source from the energy harvester, rechargeable battery, and primary cell battery. The ADP5091/92 is available in a 24-lead LFCSP and is rated for a −40°C to +125°C junction temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumed by Analog Devices for its use,nor foranyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5091/92 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Typical Application Circuit ............................................................. 1 Detailed Functional Block Diagram ...............................................9 General Description ......................................................................... 1 Typical Application Circuits ......................................................... 10 Specifications..................................................................................... 3 Factory Programmable Options ................................................... 12 Regulated Output Specifications ................................................ 4 Outline Dimensions ....................................................................... 13 Absolute Maximum Ratings ............................................................ 6 Ordering Guide TBD ................................................................. 13 Thermal Resistance ...................................................................... 6 Rev. PrA | Page 2 of 13 Preliminary Technical Data ADP5091/92 SPECIFICATIONS VIN = 1.2 V, VSYS =VBAT = 3V, TJ = -40°C to 125°C for minimum/maximum specifications and TA =25°C for typical specifications, unless otherwise noted. External components L = 22 μH, CIN = 4.7 μF, CSYS= 4.7 μF. Table 1. Parameter Symbol QUIESCENT CURRENT Operating Quiescent Current of SYS Pin IQ_SYS Test Conditions/Comments Min Typ Max Unit REG_D0=low, REG_D1=low 450 nA REG_D0=high, REG_D1= low 488 nA REG_D0= low, REG_D1= high 520 nA REG_D0= high, REG_D1= high 500 nA IIQ_SLEEP_SYS REG_D0= low, REG_D1= low 360 nA VIN_COLD PIN_COLD VSYS_TH VSYS_HYS VSYS = 0 V, 0°C < TA < 85°C 380 16 1.93 125 VIN PIN VSYS_CHG VSYS_CHG_HYS Cold-start completed Cold-start completed, VIN = 3 V IIN_PEAK Factory trim, 1 bit (200mA, 300mA) Low-Side Switch on Resistance High-Side Switch on Resistance SYS Switch on Resistance DIS_SW High Voltage DIS_SW Low Voltage DIS_SW Delay VIN CONTROL AND MINOP VIN Open Circuit Voltage Sampling Cycle VIN Open Circuit Voltage Sampling Time MINOP Bias Current MINOP Operation Voltage Range of Dynamic MPPT sensing Mode MINOP Threshold of MPPT Nonesensing Mode MPPT Bias Current of MPPT Nonesensing Mode LLD Pull High Resistor (ADP5091/92 Only) LLD Pull Low Resistor (ADP5091/92 Only) LLD High Voltage RLS_DS_ON RHS_DS_ON RSYS_DS_ON DIS_SWHIGH DIS_SWLOW tDIS_DELAY Pin-to-pin measurement Pin-to-pin measurement TVOC_CYCLE Factory trim, 2 bit (4 s , 8 s, 16 s, 32 s) Leakage Current at CBP Pin ENERGY STORAGE MANAGEMENT Internal Voltage of Charging BAT Internal Reference Voltage ICBP_LEAK (VIN > VCBP ≥ VMINOP) Sleeping Quiescent Current of SYS Pin (VCBP < VMINOP) COLD-START CIRCUIT Minimum Input Voltage for Cold-Start Minimum Input Power for Cold-Start End of Cold-Start Operation Threshold End of Cold-Start Operation Hysteresis BOOST REGULATOR Input Voltage Operation Range Input Power Operation Range SYS Threshold of Starting Charging BAT SYS Hysteresis of Stopping Charging BAT Input Peak Current 1.8 0.1 440 2.03 3.3 600 V mW V mV 300 400 TBD TBD 0.70 1 mA mA Ω Ω Ω V V μs 16 s 2.1 150 200 300 0.5 1 0.48 1 0.5 TVOC_SAMPL IMINOP VMINOP_DSM 1.45 256 2 2.55 1.5 1.8 VMINOP_NSM IMPPT 1.45 2 0.98 Rev. PrA | Page 3 of 13 ms μA V V 2.55 μA 11.4 kΩ 11.4 kΩ VLLD_IH VCHR VREF mV μW V mV 10 REG_O UT 100 pA 2.2 1 1.02 V V ADP5091/ADP5092 Parameter Battery Stop Discharging Threshold Battery Stop Discharging Hysteresis Resistor Battery Terminal Charging Threshold Battery Terminal Charging Hysteresis PGOOD Rising Threshold at SYS Pin PGOOD Pull High Resistor PGOOD Pull Low Resistor PGOOD High Voltage Battery Switches on Resistance Battery Source Current Leakage Current at BAT Pin BACKUP POWER PATH Turning off BACK_UP Switch Threshold Turning off BACK_UP Switch Hysteresis Resistor BACK_UP and BAT Comparator Offset BACK_UP and BAT Comparator Hysteresis BACK_UP Current Capability Leakage Current at BACK_UP Pin THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Preliminary Technical Data Symbol VBAT_SD RBAT_SD_HYS Test Conditions/Comments VBAT_TERM VBAT_TERM_HYS VSYS_PG Min 2.0 65 Typ Max VBAT_TERM 150 Unit V kΩ 5.2 3.7 VBAT_TERM 15 0.5 SYS TBD 1 50 20 V % V kΩ kΩ V Ω A nA nA 103.5 VBAT_TERM 150 V kΩ 185 75 400 6 250 100 520 18 mV mV mA nA 103.5 2.2 3 VBAT_SD 11.4 11.4 VPGOOD_IH RBAT_SW_ON IBAT IBAT_LEAK Pin-to-pin measurement TBD VBAT = 2 V, VBAT_SD = 2.2 V, VSYS =2 V VBAT = 3.3 V, VBAT_SD = 2.2 V, VSYS =0 V VBK_TF RBK_TF_HYS 2.0 65 VBKP_OFFSET VBAT_HYS IBKP IBKP_LEAK VSYS ≥ VSYS_TH VSYS ≥ VSYS_TH VSYS ≥ VSYS_TH VBACK_UP = VSYS = VBAT = 3 V TSHDN THYS VSYS ≥ VSYS_TH 135 55 0.6 135 15 °C °C REGULATED OUTPUT SPECIFICATIONS VIN = 1.2 V, VSYS =VBAT = 3 V, VREG_OUT=2V, L = 22 μH, CIN = 4.7 μF, CSYS= 4.7 uF, CREG_OUT=4.7 uF; TJ = -40°C to 125°C for minimum/maximum specifications and TA =25°C for typical specifications, unless otherwise noted. Table 2. Parameter REGULATED OUTPUT Output Options by VID Control REG_OUT OF BOOST MODE REG_OUT Wake Threshold REG_OUT Sleep Threshold High-Side Switches on Resistance Current Limit Threshold of Boost Mode REG_OUT OF LDO MODE REG_OUT Accuracy Symbol Min VREG_OUT 1.5 VREG_WAKE VREG_SLEEP RBST_DS_ON VREG_BST_LIM 1.005 1.015 VREG_LDO Adjustable REG_OUT Accuracy VREG_LDO_ADJ REG_OUT Dropout Current Limit Threshold of LDO Mode Output Noise VREG_ DROP IREG_LIM OUTNOISE Power Supply Rejection Ratio PSRR REG_D0 and REG_D1 Input Logic High Test Conditions/Comments IOUT = 10 mA 0 μA < IOUT < 150 mA, VSYS = (VREG_OUT + 0.5 V) IOUT = 10 mA 0 μA < IOUT < 150 mA, VSYS = (VREG_OUT + 0.5 V) IOUT = 150 mA VSYS ≥ VSYS_TH 10Hz to 100kHz 0.99 0.97 1 1 220 100 320 100 65 50 1.2 Rev. PrA | Page 4 of 13 1.020 1.030 1 100 -1 -3.5 100Hz 1kHz VREG_DX_IH Typ Max Unit 3.6 V 1.036 1.046 TBD TBD V V Ω mA 1 3.5 % % 1.01 1.03 V V mV mA uV rms dB dB V Preliminary Technical Data Parameter Input Logic Low Input Leakage Current REG_GOOD (ADP5092 Only) REG_GOOD Rising Threshold REG_GOOD Hysteresis REG_GOOD Pull High Resistor REG_GOOD Pull Low Resistor REG_GOOD High Voltage ADP5091/92 Symbol VREG_DX_IL IREG_DX_LEAK Test Conditions/Comments VREG_GOOD VREG_GOOD_HYS VREG_GOOD_IH Min Typ Max 0.4 20 Unit V nA 90 5 11.4 11.4 % % kΩ kΩ REG_O UT Rev. PrA | Page 5 of 13 ADP5091/ADP5092 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter VIN, MPPT, CBP, MINOP DIS_SW, TERM, SETPG,SETSD, SETBK, PGOOD, PG_HYS, REF, REG_D0, VID, REG_D1, LLD to AGND SW, SYS, BAT, BACK_UP, REG_OUT, REG_FB to PGND PGND to AGND θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating −0.3 V to +3.6 V −0.3 V to +6.0 V Table 4 Package Type 24-Lead LFCSP Package −0.3 V to +0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. PrA | Page 6 of 13 θJA TBD θJC TBD Unit Preliminary Technical Data ADP5091/92 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. ADP5091 LFCSP Package Pin Configuration Figure 3. ADP5092 LFCSP Package Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 Mnemonic REF SETSD SETBK 4 TERM 5 6 7 8 SETPG SETHYST AGND CBP 9 MPPT 10 VIN 11 LLD 12 13 REG_GOOD PGND SW 14 15 16 BAT REG_FB SYS 17 18 19 20 21 REG_OUT BACK_UP PGOOD VID MINOP Description Provides Voltage Reference for the SETSD, SETPG, SETBK and TERM Pins. Shutdown Setting. This pin sets the shutdown discharging voltage based on the BAT node voltage level. Sets BACK_UP disabled threshold monitoring BAT voltage. Connect this pin to AGND without BACK_UP storage element. Termination Charging Voltage. This pin sets the termination charging voltage based on the BAT node voltage level. Sets Power Good Voltage Based on SYS Node Voltage Level. Sets PGOOD Falling Hysteresis. Resistor divider input for PGOOD Falling Hysteresis. Analog Ground. Capacitor bypass. Samples and Holds the Maximum Power Point Level. Connect a 10 nF capacitor from this pin to AGND. When MPPT is disabled, tie CBP to an external reference that is lower than VIN. Analog Ground. Maximum Power Point Tracking. This pin sets the maximum power point tracking level for different energy harvesters. Place a resistor through AGND to set MPPT voltage at MINOP voltage higher than the threshold of MPPT None-sensing Mode. Input Supply from Energy Harvester Source. Connect at least a 4.7 μF capacitor as close as possible between this pin and PGND. Low light density indicator to MCU. LLD pulls high at the MINOP voltage higher than CBP voltage. ADP5091 only. Regulated Output Power Good. ADP5092 only. Power Ground. Switching Node for Inductive Boost Regulator with Connection to External Inductor. Connect a 22 μH inductor between this pin and VIN. Places Rechargeable Battery or Super Cap as a Storage for SYS Output Supply. Regulated Output Feedback Voltage Sense Input. Connect to a resistor divider from REG_OUT. Output Supply to System Load. Connect at least a 4.7 μF capacitor as close as possible between this pin and PGND. Regulated output. Connect at least a 1 μF capacitor as close as possible between this pin and PGND. Optional Input Supply from the Backup Primary Battery Cell. Output Supply to MCU. Maintains a pulled high signal when SYS is higher than SETPG threshold. Voltage Configuration Pin of REG_OUT. Set up to 8 different REG_OUT tied low through a resistor to AGND. Minimum Operating Power. Place a resistor on this pin to set the minimum operating input voltage level. The boost regulator starts switching when the CBP voltage exceeds the MINOP voltage. When MINOP voltage is above the threshold of MPPT None-sensing Mode, IC operates at a fixed MPPT ratio. Connect this pin through AGND to disable MINOP function. Rev. PrA | Page 7 of 13 ADP5091/ADP5092 Pin No. 22 23 24 Mnemonic DIS_SW REG_D1 REG_D0 EPAD Preliminary Technical Data Description Control Signal from MCU or RF Transceiver to Stop Switching Boost Charger. Regulated output working mode set. Regulated output working mode set. Exposed Pad. The exposed pad must be connected to AGND. Rev. PrA | Page 8 of 13 Preliminary Technical Data ADP5091/92 DETAILED FUNCTIONAL BLOCK DIAGRAM SYS LDO REG_SWITCHES CSYS REG_OUT BACK_UP + REG_FB REG_D0 REG_D1 HYSTERESIS REGULATOR AND LDO BACK_UP SWITCHES L SW BAT BSTO + - BAT SWITCHES HS + - BKB SYS SWITCH VID PHOTOVOLTAIC CELL BACK_UP CONTROL CIN SYS VIN LS COLD START CHARGE PUMP BKB BAT SDB REF BAT ROC2 MPPT MPPT CONTROL TERM_REF ROC1 CBP BOOST CONTROL MINOP EN_BST CHARGE CONTROL AND POWER PATH MANAGEMENT SETSD SDB PGOOD PG PGB DIS_SW BKB TERM_REF TRM 2R R PGND AGND Figure 4. Detailed Functional Block Diagram Rev. PrA | Page 9 of 13 PGB SETHYST TERM CONTROL VREF CLK STEPG VREF LLD BIAS REFERENCE AND OSCILLATOR PG BAT STEBK TERM RSYS ADP5091/ADP5092 Preliminary Technical Data TYPICAL APPLICATION CIRCUITS Figure 5. The ADP5091/92-Based Energy Harvester Wireless Sensor Application with Solarprint 0.5 V 450 μa PV-Cell as the Harvesting Energy Source, Shoei Electronics Polyacene Coin Type Capacitor PAS409HR as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery. Figure 6. The ADP5091/92-Based Energy Harvester Circuit with a Thermo Electric Generator as the Harvesting Energy Source, Shoei Electronics Polyacene Coin Type Capacitor Pas409hr as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell Cr2032 as the Backup Battery. Rev. PrA | Page 10 of 13 Preliminary Technical Data ADP5091/ADP5092 Figure 7. The ADP5091/92-Based Energy Harvester Circuit with a Piezoelectric Generator as the Harvesting Energy Source, Shoei Electronics Polyacene Coin Type Capacitor Pas409hr as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell Cr2032 as the Backup Battery. Figure 8. PGOOD Function Determines the Time to Enable the System Load Rev. PrA | Page 11 of 13 ADP5091/ADP5092 Preliminary Technical Data FACTORY PROGRAMMABLE OPTIONS To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative. Table 6. Input Current Limit Options Option Option 0 Option 1 Description 200 mA (default) 300 mA Table 7. VIN Open Circuit Voltage Sampling Cycle Options Option Option 0 Option 1 Option 2 Option 3 Description 4 s (default) 8s 16 s 32 s Rev. PrA | Page 12 of 13 Preliminary Technical Data ADP5091/ADP5092 OUTLINE DIMENSIONS Figure 9. 24-Lead Lead Frame Chip Scale Package [LFCSP-WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE TBD Model1 ADP5091ACPZ-R7 ADP5092ACPZ-R7 ADP5091-EVALZ ADP5092-EVALZ 1 Temperature Range −40°C to + 125°C −40°C to + 125°C Package Description 24-Lead LFCSP_WQ 24-Lead LFCSP_WQ Evaluation Board Evaluation Board Package Option CP-24-10 CP-24-10 Z = RoHS Compliant Part. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR14145-0-1/16(PrA) Rev. PrA | Page 13 of 13