VBUS053AZ-HAF Datasheet

VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
USB-OTG BUS-Port ESD-Protection for VBUS = 12 V
FEATURES
• Ultra compact LLP75-7L package
6
5
• Low package height < 0.6 mm
4
• 3-line USB ESD-protection with max. 
working range = 5.5 V
• VBUS - protection with 12 V working range
7
1
2
3
• Low leakage current
21102
• Low load capacitance CD = 0.7 pF
20517
• ESD-protection to IEC 61000-4-2
± 15 kV contact discharge
± 15 kV air discharge
1
MARKING (example only)
XX
YY
• Surge current acc. IEC 61000-4-5 IPP > 3 A
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
21001



Dot = Pin 1 marking
XX = Date code
YY = Type code (see table below)
ORDERING INFORMATION
DEVICE NAME
VBUS053AZ-HAF
ORDERING CODE
TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL)
MINIMUM ORDER QUANTITY
VBUS053AZ-HAF-GS08
15 000
15 000
PACKAGE DATA
DEVICE NAME
PACKAGE
NAME
TYPE
CODE
WEIGHT
MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VBUS053AZ-HAF
LLP75-7L
U9
4.2 mg
UL 94 V-0
MSL level 1
(according J-STD-020)
260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS VBUS053AZ-HAF
PARAMETER
TEST CONDITIONS
SYMBOL
VALUE
UNIT
Data line D+, D-, ID: Pin 1, 2 and 3 to ground (pin 7)
Peak pulse current
acc. IEC 61000-4-5; tp = 8/20 μs; single shot
IPPM
3
A
Peak pulse power
acc. IEC 61000-4-5; tp = 8/20 μs; single shot
PPP
36
W
ESD immunity
Contact discharge acc. IEC 61000-4-2; 10 pulses
Air discharge acc. IEC 61000-4-2; 10 pulses
VESD
± 15
± 15
kV
VBUS: Pin 6 to ground (pin 7)
Peak pulse current
acc. IEC 61000-4-5; tp = 8/20 μs/single shot
IPPM
8
A
Peak pulse power
acc. IEC 61000-4-5; tp = 8/20 μs/single shot
PPP
240
W
ESD immunity
Operating temperature
Storage temperature
Rev. 1.5, 15-Jul-15
Contact discharge acc. IEC 61000-4-2; 10 pulses
Air discharge acc. IEC 61000-4-2; 10 pulses
Junction temperature
VESD
± 30
± 30
kV
TJ
-40 to +125
°C
TSTG
-55 to +150
°C
Document Number: 81845
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
ELECTRICAL CHARACTERISTICS VBUS053AZ-HAF All inputs (pin 1, 2, and 3) to ground (pin 7)
PARAMETER
Protection paths
Reverse stand-off voltage
Reverse current
TEST CONDITIONS/REMARKS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Number of lines which can be protected
Nchannel
-
-
3
lines
at IR = 0.1 μA
VRWM
-
-
5.5
V
at VR = VRWM = 3.3 V; T = 65 °C
IR
-
-
0.085
μA
at VR = VRWM = 5.5 V
IR
-
-
1
μA
Forward voltage
at IF = 15 mA
VF
0.7
-
1.2
V
Reverse breakdown voltage
at IR = 1 mA
VBR
6.5
-
10
V
at IPP = 1 A; acc. IEC 61000-4-5; T = 25 °C
VC
-
10
12
V
at IPP = 3 A; acc. IEC 61000-4-5; T = 25 °C
VC
-
15
18
V
at IF = 3 A; acc. IEC 61000-4-5
VF
-
3.4
4.1
V
Test pin at VR = 0 V;
any other I/O pin at VR = 3.3 V, f = 1 MHz
CD
-
0.7
1
pF
Difference of the line capacitance
dCD
-
-
0.1
pF
Among pins 1, 2 and 3
at VR = 0 V; f = 1 MHz
CDD
-
0.35
0.5
pF
Reverse clamping voltage
Forward clamping voltage
Line capacitance
Line symmetry
Line to line capacitance
Note
• Tamb = - 40 °C to 85 °C, unless otherwise specified
ELECTRICAL CHARACTERISTICS VBUS (pin 6) to ground (pin 7)
PARAMETER
Protection paths
Reverse working voltage
TEST CONDITIONS/REMARKS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Number of line which can be protected
Nchannel
-
-
1
line
at IR = 100 nA
VRWM
12
-
-
V
Reverse current
at VR = VRWM = 12 V
IR
-
-
100
nA
Forward voltage
at IF = 10 mA
VF
0.6
0.75
0.9
V
Reverse breakdown voltage
at IR = 1 mA
VBR
15
-
18
V
at IPP = 1 A; acc. IEC 61000-4-5; T = 25 °C
VC
-
17.5
20
V
at IPP = 8 A; acc. IEC 61000-4-5; T = 25 °C
VC
-
25
30
V
at IF = 8 A; acc. IEC 61000-4-5
VF
-
-
2.2
V
at VR = 0 V, f = 1 MHz
CD
-
70
85
pF
Reverse clamping voltage
Forward clamping voltage
Line capacitance
Note
• Tamb = -40 °C to +85 °C, unless otherwise specified
Rev. 1.5, 15-Jul-15
Document Number: 81845
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
APPLICATION NOTE
The VBUS053AZ-HAF is intended as an ESD-protection and transient voltage suppressor for one USB-OTG port.
The LLP75-7L package contains two separate dies which are mounted on a common ground plane (pin 7). The high-speed data
lines D-, D+ and ID, are connected to any of the pins no. 1 to 3. As long as the signal voltage on the data lines is between the
ground- and the 5 V working range, the low capacitance PN-diodes offer a very high isolation to ground and to the other data lines.
But as soon as any transient signal like an ESD-signal, exceeds this working range of 5 V in either the positive or negative direction,
one of the PN-diodes gets into the forward mode and clamps the transient either to ground or to the avalanche break through level.
An extra avalanche diode (separate die) clamps the supply line voltage (VBUS at pin 6) above the 12 V working range to ground
(pin 7).
Due to the “two die construction” the VBUS line has a very high isolation to the data lines. In case of a destructive transient signal,
i.e. coming from a charger, the data lines will not be influenced.
(pinning top view)
VBUS
6
5
4
nc. nc.
6
5
4
2
3
7
GND
7
1
D-
2
D+
3
ID
1
21103
Remark:
The input pins no. 1, 2 and 3 are symmetrical. Each of the data signals D-, D+ and ID can be connected to pin 1, 2 or 3.
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
120 %
80
f = 1 MHz
Rise time = 0.7 ns to 1 ns
Discharge Current IESD
Pin 6 to pin 7
70
100 %
60
CD (pF)
80 %
60 %
53 %
50
40
30
40 %
20
27 %
20 %
10
0%
-10 0 10 20 30 40 50 60 70 80 90 100
0
5
21468
Time (ns)
20557
0
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
10
15
VR (V)
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
0.8
f = 1 MHz, one I/O pin at 3.3 V
8 µs to 100 %
100 %
0.7
0.6
CD (pF)
80 %
IPPM
60 %
20 µs to 50 %
40 %
0.5
0.4
0.3
Pin 1, 2 or 3 to pin 7
0.2
20 %
0.1
0%
0
0
20548
10
20
30
Time (µs)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Formacc. IEC 61000-4-5
Rev. 1.5, 15-Jul-15
0
40
21469
0.5
1
1.5
2
2.5
3
3.5
VR (V)
Fig. 4 - Typical Capacitance CD vs. Reverse Voltage VR
Document Number: 81845
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
100
30
Measured acc. IEC 61000-4-5
(8/20 µs - wave form)
25
10
P in 6 to p in 7
Pin 6 to pin 7
20
VC (V)
IF (mA)
1
Pin 1, 2 or 3 to pin 7
0.1
VC
15
10
0.01
5
P in 7 to p in 6
0.001
0.5
0
0.6
0.7
0.8
0.9
1
0
1.1
VF (V)
21470
21473
Fig. 5 - Typical Forward Current IF vs. Forward Voltage VF
1
2
3
4
5
6
7
8
9 10 11
IPP (A)
Fig. 8 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
20
18
Pin 6 to pin 7
16
VR (V)
14
12
10
8
Pin 1, 2 or 3 to pin 7
6
4
2
0
0.01
0.1
1
10
100
1000 10 000
IR (µA)
21471
Fig. 6 - Typical Reverse Voltage VR vs. Reverse Current IR
18
Measured acc. IEC 61000-4-5 (8/20 µs - wave form)
16
14
P in 1 , 2 o r 3 to p in 7
VC (V)
12
10
VF
8
6
4
P in 7 to p in 1 , 2 o r 3
2
0
0
21472
1
2
3
4
IPP (A)
Fig. 7 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
Rev. 1.5, 15-Jul-15
Document Number: 81845
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
0.45 (0.018)
0.55 (0.022)
0.2 (0.008)
0.3 (0.012)
0.2 (0.008)
0.3 (0.012)
1 (0.039)
0.2 (0.008)
0.3 (0.012)
Heat sink
0.95 (0.037)
1.05 (0.041)
PACKAGE DIMENSIONS in millimeters (inches): LLP75-7L
0.5 (0.020)
0.6 (0.024)
0.6 (0.024)
0.54 (0.021)
1.65 (0.065)
1.55 (0.061)
0.05 (0.002)
0 (0.000)
0.15 (0.006)
0.25 (0.010)
1.65 (0.065)
Pin 1 marking
1.55 (0.061)
Foot print recommendation:
0.5 (0.020)
0.5 (0.020)
0.3 (0.012)
0.3 (0.012)
Document no.:S8-V-3906.02-014 (4)
Created - Date: 04. April 2006
0.15 (0.006)
1 (0.039)
0.5 (0.020)
1 (0.039)
0.25 (0.010)
0.15 (0.006)
Solder resist mask
Solder pad
0.5 (0.020)
20500
Rev. 1.5, 15-Jul-15
Document Number: 81845
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VBUS053AZ-HAF
www.vishay.com
Vishay Semiconductors
LLP75-7x
S9
F5
Pad layout - view from top / seen at bottom side
S8-V-3906.02-008a (4)
10.12.2009
Rev. 1.5, 15-Jul-15
Pin 1 - location
Document Number: 81845
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 02-Oct-12
1
Document Number: 91000