INFINEON TDA5102

Wireless Components
ASK/FSK Transmitter 915 MHz
TDA 5102 Version 1.1
Specification October 2001
Revision History
Current Version: 1.1 as of October 2001
Previous Version: 1.0, March 2001
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
2-2, 5-3, 5-6
2-2, 5-3, 5-6
Frequency range increased
3-3 ... 3-6
3-3 ... 3-6
ESD-structures added to interface schematics
3-10, 5-3
3-10, 5-3
Typical value for Power-Down-Mode current added
4-8 ... 4-10
Description of Application board deleted
5-2
5-2
Supply voltage range added to Absolute Maximum Ratings
5-2
5-2
ESD integrity specified in detail
5-3, 5-6
5-3, 5-6
Loop filter voltages adapted
5-4, 5-7
5-4, 5-7
Saturation voltage of Clock Driver Output reduced
5-5, 5-8
5-5, 5-8
Output Power Tolerances reduced
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Edition 15.02.2001
Published by Infineon Technologies AG,
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81541 München
© Infineon Technologies AG 2001.
All Rights Reserved.
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1
Table of Contents
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-i
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3.2
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3.3
Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
3.4
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4.1
50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
4.2
50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
4.3
Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
4.4
Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
5.2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
5.3
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
TDA 5102
Product Info
Product Info
General Description
Features
Applications
The TDA 5102 is a single chip ASK/ Package
FSK transmitter for the frequency band
905-925 MHz. The IC offers a high
level of integration and needs only a
few external components. The device
contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special
circuit design and an unique power
amplifier design are used to save current consumption and therefore to save
battery life. Additionally features like a
power down mode, a low power detect,
a selectable crystal oscillator frequency
and a divided clock output are implemented. The IC can be used for both
ASK and FSK modulation.
■
fully integrated frequency synthesizer
■
power down mode
■
VCO without external components
■
low voltage sensor
■
high efficiency power amplifier
■
selectable crystal oscillator
7.15 MHz/14.3 MHz
■
frequency range 905-925 MHz
■
programmable divided clock output
for µC
■
ASK/FSK modulation
■
low supply current (typically 7mA)
■
low external component count
■
voltage supply range 2.1 - 4 V
■
Keyless entry systems
■
Alarm systems
■
Remote control systems
■
Communication systems
Ordering Information
Type
Ordering Code
Package
TDA 5102
Q67036-A1175
P-TSSOP-16
available on tape and reel
Wireless Components
Product Info
Specification, October 2001
2
Product Description
Contents of this Chapter
2.1
2.2
2.3
2.4
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5102
Product Description
2.1 Overview
The TDA 5102 is a single chip ASK/FSK transmitter for the frequency band 905925 MHz. The IC offers a high level of integration and needs only a few external
components. The device contains a fully integrated PLL synthesizer and a high
efficiency power amplifier to drive a loop antenna. A special circuit design and
an unique power amplifier design are used to save current consumption and
therefore to save battery life. Additional features like a power down mode, a low
power detect, a selectable crystal oscillator frequency and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation.
2.2 Applications
■
Keyless entry systems
■
Remote control systems
■
Alarm systems
■
Communication systems
2.3 Features
Wireless Components
■
fully integrated frequency synthesizer
■
VCO without external components
■
high efficiency power amplifier
■
frequency range 905-925 MHz
■
ASK/FSK modulation
■
low supply current (typically 7 mA)
■
voltage supply range 2.1 - 4 V
■
power down mode
■
low voltage sensor
■
selectable crystal oscillator 7.15 MHz/14.3 MHz
■
programmable divided clock output for µC
■
low external component count
2-2
Specification, October 2001
TDA 5102
Product Description
2.4 Package Outlines
Figure 2-1
Wireless Components
P-TSSOP-16
2-3
Specification, October 2001
3
Functional Description
Contents of this Chapter
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.5.1
3.4.5.2
3.4.5.3
3.4.5.4
3.4.6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Power mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Recommended timing diagrams for ASK- and FSK-Modulation . . 3-12
TDA 5102
Functional Description
3.1 Pin Configuration
PDWN
1
16
CSEL
LPD
2
15
FSEL
VS
3
14
PAOUT
LF
4
13
PAGND
TDA 5102
GND
5
12
FSKGND
ASKDTA
6
11
FSKOUT
FSKDTA
7
10
COSC
CLKOUT
8
9
CLKDIV
Pin_config.wmf
Figure 3-1
IC Pin Configuration
Table 3-1
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Wireless Components
Symbol
PDWN
LPD
VS
LF
GND
ASKDTA
FSKDTA
CLKOUT
CLKDIV
COSC
FSKOUT
FSKGND
PAGND
PAOUT
FSEL
CSEL
Function
Power Down Mode Control
Low Power Detect Output
Voltage Supply
Loop Filter
Ground
Amplitude Shift Keying Data Input
Frequency Shift Keying Data Input
Clock Driver Output
Clock Divider Control
Crystal Oscillator Input
Frequency Shift Keying Switch Output
Frequency Shift Keying Ground
Power Amplifier Ground
Power Amplifier Output
Frequency Range Selection: Has to be left open for
915 MHz operation
Crystal Frequency Selection (7.15 or 14.3 MHz)
3-2
Specification, October 2001
TDA 5102
Functional Description
3.2 Pin Definitions and Functions
Table 3-2
Pin
No.
Symbol
1
PDWN
Interface Schematic
Function
Disable pin for the complete transmitter circuit.
VS
40 µA ∗ (ASKDTA+FSKDTA)
A logic low (PDWN < 0.7 V) turns off all
transmitter functions.
5 kΩ
A logic high (PDWN > 1.5 V) gives access to
all transmitter functions.
1
"ON"
150 kΩ
PDWN input will be pulled up by 40 µA internally by either setting FSKDTA or ASKDTA
to a logic high-state.
250 kΩ
2
LPD
This pin provides an output indicating the
low-voltage state of the supply voltage VS.
VS
VS < 2.15 V will set LPD to the low-state.
40 µA
2
300 Ω
3
VS
Wireless Components
An internal pull-up current of 40 µA gives the
output a high-state at supply voltages above
2.15 V.
This pin is the positive supply of the transmitter electronics.
An RF bypass capacitor should be connected directly to this pin and returned to
GND (pin 5) as short as possible.
3-3
Specification, October 2001
TDA 5102
Functional Description
4
LF
Output of the charge pump and input of the
VCO control voltage.
The loop bandwidth of the PLL is 150 kHz
when only the internal loop filter is used.
The loop bandwidth may be reduced by
applying an external RC network referencing
to the positive supply VS (pin 3).
VS
140 pF
15 pF
35 kΩ
10 kΩ
4
5
GND
6
ASKDTA
VS
General ground connection.
VS
Digital amplitude modulation can be
imparted to the Power Amplifier through this
pin.
+1.2 V
A logic high (ASKDTA > 1.5 V or open)
enables the Power Amplifier.
60 kΩ
6
+1.1 V
90 kΩ
50 pF
7
30 µA
FSKDTA
VS
A logic low (ASKDTA < 0.5 V)
disables the Power Amplifier.
Digital frequency modulation can be
imparted to the Xtal Oscillator by this pin.
The VCO-frequency varies in accordance to
the frequency of the reference oscillator.
+1.2 V
60 kΩ
7
+1.1 V
90 kΩ
30 µA
A logic high (FSKDTA > 1.5V or open)
sets the FSK switch to a high impedance
state.
A logic low (FSKDTA < 0.5 V)
closes the FSK switch
from FSKOUT (pin 11) to FSKGND (pin 12).
A capacitor can be switched to the reference
crystal network this way. The Xtal Oscillator
frequency will be shifted giving the designed
FSK frequency deviation.
Wireless Components
3-4
Specification, October 2001
TDA 5102
Functional Description
8
CLKOUT
Clock output to supply an external device.
An external pull-up resistor has to be added
in accordance to the driving requirements of
the external device.
A clock frequency of 3.57 MHz is selected
by a logic low at CLKDIV input (pin9).
A clock frequency of 894 kHz is selected by
a logic high at CLKDIV input (pin9).
VS
8
300 Ω
9
CLKDIV
This pin is used to select the desired clock
division rate for the CLKOUT signal.
VS
+1.2 V
VS
A logic low (CLKDIV < 0.2 V) applied to this
pin selects the 3.57 MHz output signal at
5 µA
CLKOUT (pin 8).
60 kΩ
A logic high (CLKDIV open) applied to this
+0.8 V pin selects the 894 kHz output signal at
60 kΩ
CLKOUT (pin 8).
9
10
COSC
This pin is connected to the reference oscillator circuit.
The reference oscillator is working as a negative impedance converter. It presents a
negative resistance in series to an inductance at the COSC pin.
VS
VS
6 kΩ
10
100 µA
11
FSKOUT
This pin is connected to a switch to
FSKGND (pin 12).
VS
VS
The switch is closed when the signal at
FSKDTA (pin 7) is in a logic low state.
The switch is open when the signal at
FSKDTA (pin 7) is in a logic high state.
200 µA
1.5 kΩ
11
FSKOUT can switch an additional capacitor
to the reference crystal network to pull the
crystal frequency by an amount resulting in
the desired FSK frequency shift of the transmitter output frequency.
12
Wireless Components
3-5
Specification, October 2001
TDA 5102
Functional Description
12
FSKGND
13
PAGND
Ground connection for FSK modulation output FSKOUT.
Ground connection of the power amplifier.
The RF ground return path of the power
amplifier output PAOUT (pin 14) has to be
concentrated to this pin.
14
PAOUT
RF output pin of the transmitter.
14
A DC path to the positive supply VS has to
be supplied by the antenna matching network.
13
15
FSEL
This pin has to be left open to select the
915 MHz transmitter frequency range.
+1.2 V
VS
A logic low (FSEL < 0.5 V) applied to this pin
sets the transmitter to the 457 MHz frequency range.
30 kΩ
15
+1.1 V
90 kΩ
30 µA
16
CSEL
VS
+1.2 V
60 kΩ
A logic high (FSEL open) applied to this pin
sets the transmitter to the 915 MHz frequency range.
This pin is used to select the desired reference frequency.
VS
5 µA
16
A logic low (CSEL < 0.2 V) applied to this pin
sets the internal frequency divider to accept
a reference frequency of 7.15 MHz.
+0.8 V
60 kΩ
Wireless Components
A logic high (CSEL open) applied to this pin
sets the internal frequency divider to accept
a reference frequency of 14.3 MHz.
3-6
Specification, October 2001
Figure 3-2
Wireless Components
3-7
Clock Output
Frequency
Select
0.894/3.57 MHz
9
10
11
FSK
Switch
Crystal
7.15/14.3 MHz
12
FSK
Ground
XTAL
Osc
Clock
Output
8
:2/8
:4/16
PFD
7
FSK
Data
Input
OR
1
Power
Down
Control
Crystal
Select
7.15/14.3 MHz
16
:128/64
6
ASK
Data
Input
Loop
Filter
4
LF
VCO
15
:1/2
On
Ground
5
Power
AMP
Low Voltage
Sensor 2.2V
2
Low Power
Detect Output
Frequency Select
Open for 915 MHz
Power
Supply
3
Positive
Supply
VS
Power
Amplifier
Output
Power
Amplifier
Ground
14
13
TDA 5102
Functional Description
3.3 Functional Block diagram
Funct_Block_Diagram.wmf
Functional Block diagram
Specification, October 2001
TDA 5102
Functional Description
3.4 Functional Blocks
3.4.1 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator
(VCO), an asynchronous divider chain, a phase detector, a charge pump and a
loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the
VCO is 915 MHz. The oscillator signal is fed both, to the synthesizer divider
chain and to the power amplifier. The overall division ratio of the asynchronous
divider chain is 128 in case of a 7.15 MHz crystal or 64 in case of a 14.3 MHz
crystal and can be selected via CSEL (pin 16). The phase detector is a Type IV
PD with charge pump. The passive loop filter is realized on chip.
3.4.2 Crystal Oscillator
The crystal oscillator operates either at 7.15 MHz or at 14.3 MHz.
The reference frequency can be chosen by the signal at CSEL (pin 16).
Table 3-3
CSEL (pin 16)
1)
7.15 MHz
14.3 MHz
Low
Open2)
1) Low:
2) Open:
Crystal Frequency
Voltage at pin < 0.2 V
Pin open
For both quartz frequency options, 894 kHz or 3.57 MHz are available as output
frequencies of the clock output CLKOUT (pin 8) to drive the clock input of a
micro controller.
The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)
Table 3-4
CLKDIV (pin 9)
1)
3.57 MHz
894 kHz
Low
Open2)
1) Low:
2) Open:
Wireless Components
CLKOUT Frequency
Voltage at pin < 0.2 V
Pin open
3-8
Specification, October 2001
TDA 5102
Functional Description
To achieve FSK transmission, the oscillator frequency can be detuned by a
fixed amount by switching an external capacitor via FSKOUT (pin 11).
The condition of the switch is controlled by the signal at FSKDTA (pin 7).
Table 3-5
FSKDTA (pin7)
FSK Switch
1)
CLOSED
OPEN
Low
Open2), High3)
1) Low:
2) Open:
3) High:
Voltage at pin < 0.5 V
Pin open
Voltage at pin > 1.5 V
3.4.3 Power Amplifier
For operation at 915 MHz, the power amplifier is fed directly from the voltage
controlled oscillator. It is possible to feed the power amplifier with the VCO frequency divided by 2. This is controlled by FSEL (pin 15) as described in the
table below.
Table 3-6
FSEL (pin 15)
Radiated Frequency Band
1)
457 MHz
915 MHz
Low
Open2)
1) Low:
2) Open:
Voltage at pin < 0.5 V
Pin open
The Power Amplifier can be switched on and off
by the signal at ASKDTA (pin 6).
Table 3-7
ASKDTA (pin 6)
1)
Low
Open2), High3)
1) Low:
2) Open:
3) High:
Power Amplifier
OFF
ON
Voltage at pin < 0.5 V
Pin open
Voltage at pin > 1.5 V
The Power Amplifier has an Open Collector output at PAOUT (pin 14) and
requires an external pull-up coil to provide bias. The coil is part of the tuning and
matching LC circuitry to get best performance with the external loop antenna.
To achieve the best power amplifier efficiency, the high frequency voltage swing
at PAOUT (pin 14) should be twice the supply voltage.
The power amplifier has its own ground pin PAGND (pin 13) in order to reduce
the amount of coupling to the other circuits.
Wireless Components
3-9
Specification, October 2001
TDA 5102
Functional Description
3.4.4 Low Power Detect
The supply voltage is sensed by a low power detector. When the supply voltage
drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To minimize the external component count, an internal pull-up current of 40 µA gives
the output a high-state at supply voltages above 2.15 V.
The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off
the PA as soon as the supply voltage drops below 2.15 V or it can be used to
inform a micro-controller to stop the transmission after the current data packet.
3.4.5 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL
ENABLE MODE and the TRANSMIT MODE.
3.4.5.1 Power Down Mode
In the POWER DOWN MODE the complete chip is switched off.
The current consumption is typically 0.3 nA at 3 V 25°C.
3.4.5.2 PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is
turned off to avoid undesired power radiation during the time the PLL needs to
settle. The turn on time of the PLL is determined mainly by the turn on time of
the crystal oscillator and is typically less than 1 msec, depending on the crystal.
The current consumption is typically 3.5 mA.
3.4.5.3 Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is
turned on too.
The current consumption of the IC is typically 7 mA when using a proper transforming network at PAOUT, see Figure 4-1.
3.4.5.4 Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1).
When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are
pulled up internally.
Forcing the voltage at the pins low overrides the internally set state.
Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the
PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open.
Wireless Components
3 - 10
Specification, October 2001
TDA 5102
Functional Description
The principle schematic of the power mode control circuitry is shown in
Figure 3-5.
PDWN
ASKDTA
OR
FSKDTA
On
Bias
Source
Bias Voltage
120 kΩ
120 kΩ
FSKOUT
FSK
On
PLL
915
MHz
PA
PAOUT
IC
Power_Mode.wmf
Figure 3-5
Power mode control circuitry
Table 3-8 provides a listing of how to get into the different power modes
Table 3-8
PDWN
FSKDTA
ASKDTA
Low1)
Low, Open
Low, Open
Open2)
Low
Low
High3)
Low, Open, High
Low
Open
High
Low
High
Low, Open, High
Open, High
Open
High
Open, High
Open
Low, Open, High
High
1) Low:
2) Open:
3) High:
MODE
POWER DOWN
PLL ENABLE
TRANSMIT
Voltage at pin < 0.7 V (PDWN)
Voltage at pin < 0.5 V (FSKDTA, ASKDTA)
Pin open
Voltage at pin > 1.5 V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not
recommended.
Wireless Components
3 - 11
Specification, October 2001
TDA 5102
Functional Description
3.4.6 Recommended timing diagrams for ASK- and FSK-Modulation
ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
High
FSKDTA
Low
to
t
DATA
Open, High
ASKDTA
Low
to
t
min. 1 msec.
ASK_mod.wmf
Figure 3-6
ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
DATA
High
FSKDTA
Low
to
t
to
t
High
ASKDTA
Low
min. 1 msec.
FSK_mod.wmf
Figure 3-7
Wireless Components
FSK Modulation
3 - 12
Specification, October 2001
TDA 5102
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to
t
DATA
Open, High
ASKDTA
Low
to
t
min. 1 msec.
Alt_ASK_mod.wmf
Figure 3-8
Alternative ASK Modulation
Alternative FSK Modulation
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to
t
to
t
Open, High
ASKDTA
Low
DATA
Open, High
FSKDTA
Low
to
t
min. 1 msec.
Alt_FSK_mod.wmf
Figure 3-9
Wireless Components
Alternative FSK Modulation
3 - 13
Specification, October 2001
4
Applications
Contents of this Chapter
4.1
4.2
4.3
4.4
50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 4-2
50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 4-4
Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
TDA 5102
Applications
4.1 50 Ohm-Output Testboard Schematic
X2SMA
C8
C2
C4
L2
L1
VCC
C7
C3
C6
10
9
8
11
7
12
13
14
15
7.15 (14.3)
MHz
16
Q1
0.89 (3.6)
MHz
VCC
6
5
4
3
2
VCC
1
TDA5102
C1
T1
R3A
R3F
R4
R2
FSK
ASK
R1
C5
X1SMA
50ohm_test_v5.wmf
Figure 4-1
Wireless Components
50 Ω-Output testboard schematic
4-2
Specification, October 2001
TDA 5102
Applications
4.2 50 Ohm-Output Testboard Layout
Wireless Components
Figure 4-2
Top Side of TDA 5102-Testboard with 50 Ω-Output.
It is the same testboard as for the TDA 5100.
Figure 4-3
Bottom Side of TDA 5102-Testboard with 50 Ω-Output.
It is the same testboard as for the TDA 5100.
4-3
Specification, October 2001
TDA 5102
Applications
4.3 Bill of material (50 Ohm-Output Testboard)
Table 4-1 Bill of material
Part
R1
ASK
FSK
915 MHz
915 MHz
4.7 kΩ
4.7 kΩ
0805, ± 5%
12 kΩ
0805, ± 5%
R2
R3A
15 kΩ
0805, ± 5%
R3F
Wireless Components
Specification
15 kΩ
0805, ± 5%
R4
open
open
0805, ± 5%
C1
47 nF
47 nF
0805, X7R, ± 10%
C2
47 pF
47 pF
0805, COG, ± 5%
C3
2.7 pF
2.7 pF
0805, COG, ± 0.1 pF
C4
100 pF
100 pF
0805, COG, ± 5%
C5
1 nF
1 nF
0805, X7R, ± 10%
C6
5.6 pF
5.6 pF
0805, COG, ± 0.1 pF
C7
0 Ω Jumper
47 pF
0805, COG, ± 5%
0805, 0Ω Jumper
C8
8.2 pF
8.2 pF
0805, COG, ± 5%
L1
33 nH
33 nH
TOKO LL2012-J
L2
15 nH
15 nH
TOKO LL1608-J
Q3
14.3 MHz
14.3 MHz
IC1
TDA 5102
TDA 5102
B1
Battery clip
Battery clip
HU2031-1, RENATA
T1
Push-button
Push-button
replaced by a short
X1
SMA-S
SMA-S
SMA standing
X2
SMA-S
SMA-S
SMA standing
4-4
Specification, October 2001
TDA 5102
Applications
4.4 Hints
1. Application Hints on the crystal oscillator
As mentioned before, the crystal oscillator achieves a turn on time less than
1 msec. To achieve this, a NIC oscillator type is implemented in the TDA 5102.
The input impedance of this oscillator is a negative resistance in series to an
inductance. Therefore the load capacitance of the crystal CL (specified by the
crystal supplier) is transformed to the capacitance Cv.
-R
L
f, CL Cv
IC
Cv =
1
Formula 1)
1
+ω2L
CL
CL:
crystal load capacitance for nominal frequency
ω:
angular frequency
L:
inductivity of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced
by a short to ground. Assume a crystal frequency of 14.3 MHz and a crystal load
capacitance of CL = 20 pF. The inductance L is specified within the electrical
characteristics at 14.3 MHz to a value of 11 µH. Therefore C6 is calculated to
7.2 pF.
Cv =
Wireless Components
4-5
1
1
+ω 2L
CL
= C6
Specification, October 2001
TDA 5102
Applications
Example for the FSK-Mode:
FSK modulation is achieved by switching the load capacitance of the crystal as
shown below.
FSKDTA
FSKOUT
Csw
-R
L
f, CL Cv1
Cv2
COSC
IC
The frequency deviation of the crystal oscillator is multiplied with the divider
factor N of the Phase Locked Loop to the output of the power amplifier. In case
of small frequency deviations (up to +/- 1000 ppm), the two desired load
capacitances can be calculated with the formula below.
2(C 0 + CL )
∆f
)
(1 +
N * f1
C1
2(C 0 + CL )
∆f
)
1±
(1 +
N * f1
C1
CL # C 0
CL ± =
C L:
C 0:
f:
ω:
N:
df:
crystal load capacitance for nominal frequency
shunt capacitance of the crystal
frequency
ω = 2πf: angular frequency
division ratio of the PLL
peak frequency deviation
Because of the inductive part of the TDA 5102, these values must be corrected
by formula 1). The value of Cv± can be calculated.
Wireless Components
4-6
Specification, October 2001
TDA 5102
Applications
If the FSK switch is closed, Cv- is equal to Cv1 (C6 in the application diagram).
If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
Cv 2 = C 7 =
Csw ∗ Cv1 − (Cv + ) ∗ (Cv1 + Csw)
(Cv + ) − Cv1
Csw:
parallel capacitance of the FSK switch (3 pF)
Remark:
These calculations are only approximations. The necessary values
depend on the layout also and must be adapted for the specific
application board.
2. Design hints on the buffered clock output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL)
should be connected between this pin and the positive supply voltage. The
value of RL is depending on the clock frequency and the load capacitance CLD
(PCB board plus input capacitance of the microcontroller). RL can be calculated
to:
RL =
1
fCLKOUT * 8 * CLD
Table 4-2
fCLKOUT=
894 kHz
CLD[pF]
RL[kOhm]
CLD[pF]
RL[kOhm]
5
27
5
6.8
10
12
10
3.3
20
6.8
20
1.8
Remark:
Wireless Components
fCLKOUT=
3.57 MHz
To achieve a low current consumption and a low
spurious radiation, the largest possible RL should be chosen.
4-7
Specification, October 2001
5
Reference
Contents of this Chapter
5.1
5.2
5.3
5.3.1
5.3.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
AC/DC Characteristics at 3V, 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
AC/DC Characteristics at 2.1 V ... 4.0 V, -25°C ... +85°C. . . . . . . . . . 5-6
TDA 5102
Reference
5.1 Absolute Maximum Ratings
The AC / DC characteristic limits are not guaranteed. The maximum ratings
must not be exceeded under any circumstances, not even momentarily and
individually, as permanent damage to the IC may result.
Table 5-1
Symbol
Parameter
Limit Values
Min
Max
Unit
Junction Temperature
TJ
-40
150
°C
Storage Temperature
Ts
-40
125
°C
230
K/W
Thermal Resistance
RthJA
Supply voltage
Remarks
VS
-0.3
4.0
V
ESD integrity, all pins
VESD
-1
+1
kV
100 pF, 1500 Ω
ESD integrity,
pins 11 and 14 not tested
VESD
-2
+2
kV
100 pF, 1500 Ω
Ambient Temperature under bias: TA=-25 to +85°C
5.2 Operating Range
Within the operational range the IC operates as described in the circuit
description.
Table 5-2
Parameter
Symbol
Limit Values
Min
Max
Unit
Supply voltage
VS
2.1
4.0
V
Ambient temperature
TA
-25
85
°C
Wireless Components
5-2
Test Conditions
Specification, October 2001
TDA 5102
Reference
5.3 AC/DC Characteristics
5.3.1
AC/DC Characteristics at 3V, 25°C
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C
Parameter
Symbol
Limit Values
Min
Unit
Typ
Max
Test Conditions
Current consumption
Power down mode
IS PDWN
0.3
100
nA
V (Pins 1, 6, and 7)
< 0.2 V
PLL enable mode
IS PLL_EN
3.3
4.2
mA
Transmit mode
IS TRANSM
7
9
mA
Load tank see
Figure 4-1
Power Down Mode Control (Pin 1)
Power down mode
VPDWN
0
0.7
V
VASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL enable mode
VPDWN
1.5
VS
V
VASKDTA < 0.5 V
Transmit mode
VPDWN
1.5
VS
V
VASKDTA > 1.5 V
Input bias current PDWN
IPDWN
30
µA
VPDWN = VS
Low Power Detect Output (Pin 2)
Internal pull up current
I LPD1
30
µA
VS = 2.3 V ... VS
Input current low voltage
I LPD2
1
mA
VS = 1.9 V ... 2.1 V
V
fVCO = 915 MHz
928
MHz
VS-VLF =
0.54V...1.76V
VFSEL = open
Loop Filter (Pin 4)
VCO tuning voltage
VLF
Output frequency range
915 MHz-band
fOUT, 915
VS - 1.5
VS - 0.7
902
915
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled
VASKDTA
0
0.5
V
ASK Transmit enabled
VASKDTA
1.5
VS
V
Input bias current ASKDTA
IASKDTA
30
µA
VASKDTA = VS
Input bias current ASKDTA
IASKDTA
µA
VASKDTA = 0 V
ASK data rate
fASKDTA
Wireless Components
-20
20
5-3
kHz
Specification, October 2001
TDA 5102
Reference
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C
Parameter
Symbol
Limit Values
Min
Typ
Unit
Test Conditions
Max
FSK Modulation Data Input (Pin 7)
FSK Switch on
VFSKDTA
0
0.5
V
FSK Switch off
VFSKDTA
1.5
VS
V
Input bias current FSKDTA
IFSKDTA
30
µA
VFSKDTA = VS
Input bias current FSKDTA
IFSKDTA
µA
VFSKDTA = 0 V
FSK data rate
fFSKDTA
-20
20
kHz
Clock Driver Output (Pin 8)
Output current (Low)
ICLKOUT
Output current (High)
ICLKOUT
Saturation Voltage (Low)
VSATL
1
mA
VCLKOUT = VS
5
µA
VCLKOUT = 0 V
0.56
V
ICLKOUT = 1 mA
0.2
V
Clock Divider Control (Pin 9)
Setting Clock Driver output
frequency fCLKOUT=3.57 MHz
VCLKDIV
Setting Clock Driver output
frequency fCLKOUT=894 kHz
VCLKDIV
Input bias current CLKDIV
ICLKDIV
Input bias current CLKDIV
ICLKDIV
0
30
-20
V
pin open
µA
VCLKDIV = VS
µA
VCLKDIV = 0 V
Crystal Oscillator Input (Pin 10)
Load capacitance
CCOSCmax
Serial Resistance of the crystal
Input inductance of the
COSC pin
5
pF
100
Ω
f = 7.15 MHz
µH
f = 7.15 MHz
Ω
f = 14.3 MHz
µH
f = 14.3 MHz
12
Serial Resistance of the crystal
100
11
Input inductance of the
COSC pin
FSK Switch Output (Pin 11)
On resistance
RFSKOUT
220
Ω
VFSKDTA = 0 V
On capacitance
CFSKOUT
6
pF
VFSKDTA = 0 V
Off resistance
RFSKOUT
kΩ
VFSKDTA = VS
Off capacitance
CFSKOUT
pF
VFSKDTA = VS
Wireless Components
10
1.5
5-4
Specification, October 2001
TDA 5102
Reference
Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C
Parameter
Symbol
Limit Values
Unit
Min
Typ
Max
0
2
4
Test Conditions
Power Amplifier Output (Pin 14)
Output Power1)
transformed to 50 Ohm
POUT915
dBm
fOUT = 915 MHz
VFSEL = open
V
pin open
Frequency Range Selection (Pin 15)
Transmit frequency 915 MHz
VFSEL
Transmit frequency 457 MHz
VFSEL
Input bias current FSEL
IFSEL
Input bias current FSEL
IFSEL
0
0.5
V
30
µA
VFSEL = VS
µA
VFSEL = 0 V
-20
Crystal Frequency Selection (Pin 16)
Crystal frequency 7.15 MHz
VCSEL
Crystal frequency 14.3 MHz
VCSEL
Input bias current CSEL
ICSEL
Input bias current CSEL
ICSEL
0
0.2
50
-25
V
V
pin open
µA
VCSEL = VS
µA
VCSEL = 0 V
1) Power amplifier in overcritical C-operation.
Matching circuitry as used in the 50 Ohm-Output Testboard.
Tolerances of the passive elements not taken into account.
Wireless Components
5-5
Specification, October 2001
TDA 5102
Reference
5.3.2
AC/DC Characteristics at 2.1 V ... 4.0 V, -25°C ... +85°C
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C
Parameter
Symbol
Limit Values
Min
Typ
Unit
Test Conditions
Max
Current consumption
Power down mode
IS PDWN
PLL enable mode
IS PLL_EN
Transmit mode
IS TRANSM
250
nA
V (Pins 1, 6, and 7)
< 0.2 V
3.3
4.6
mA
7
9.5
mA
Load tank see
Figure 4-1 and 4-2
Power Down Mode Control (Pin 1)
Power down mode
VPDWN
0
0.5
V
VASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL enable mode
VPDWN
1.5
VS
V
VASKDTA < 0.5 V
Transmit mode
VPDWN
1.5
VS
V
VASKDTA > 1.5 V
Input bias current PDWN
IPDWN
30
µA
VPDWN = VS
Low Power Detect Output (Pin 2)
Internal pull up current
I LPD1
30
µA
VS = 2.3 V ... VS
Input current low voltage
I LPD2
1
mA
VS = 1.9 V ... 2.1 V
V
fVCO = 915 MHz
925
MHz
VS-VLF = 0.4V...1.95V
VFSEL = open
Loop Filter (Pin 4)
VCO tuning voltage
VLF
Output frequency range
915 MHz-band
fOUT, 915
VS - 1.74
905
VS - 0.52
915
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled
VASKDTA
0
0.5
V
ASK Transmit enabled
VASKDTA
1.5
VS
V
Input bias current ASKDTA
IASKDTA
30
µA
VASKDTA = VS
Input bias current ASKDTA
IASKDTA
µA
VASKDTA = 0 V
ASK data rate
fASKDTA
Wireless Components
-20
20
5-6
kHz
Specification, October 2001
TDA 5102
Reference
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C
Parameter
Symbol
Limit Values
Min
Typ
Unit
Test Conditions
Max
FSK Modulation Data Input (Pin 7)
FSK Switch on
VFSKDTA
0
0.5
V
FSK Switch off
VFSKDTA
1.5
VS
V
Input bias current FSKDTA
IFSKDTA
30
µA
VFSKDTA = VS
Input bias current FSKDTA
IFSKDTA
µA
VFSKDTA = 0 V
FSK data rate
fFSKDTA
-20
20
kHz
Clock Driver Output (Pin 8)
Output current (Low)
ICLKOUT
Output current (High)
ICLKOUT
Saturation Voltage (Low)1)
VSATL
1
mA
VCLKOUT = VS
5
µA
VCLKOUT = 0 V
0.5
V
ICLKOUT = 0.8 mA
0.2
V
Clock Divider Control (Pin 9)
Setting Clock Driver output
frequency fCLKOUT=3.57 MHz
VCLKDIV
Setting Clock Driver output
frequency fCLKOUT=894 kHz
VCLKDIV
Input bias current CLKDIV
ICLKDIV
Input bias current CLKDIV
ICLKDIV
0
30
-20
V
pin open
µA
VCLKDIV = VS
µA
VCLKDIV = 0 V
Crystal Oscillator Input (Pin 10)
Load capacitance
CCOSCmax
Serial Resistance of the crystal
5
pF
100
Ω
f = 7.15 MHz
µH
f = 7.15 MHz
Ω
f = 14.3 MHz
µH
f = 14.3 MHz
12
Input inductance of the
COSC pin
Serial Resistance of the crystal
100
Input inductance of the
COSC pin
11
FSK Switch Output (Pin 11)
On resistance
RFSKOUT
220
Ω
VFSKDTA = 0 V
On capacitance
CFSKOUT
6
pF
VFSKDTA = 0 V
Off resistance
RFSKOUT
kΩ
VFSKDTA = VS
Off capacitance
CFSKOUT
pF
VFSKDTA = VS
Wireless Components
10
1.5
5-7
Specification, October 2001
TDA 5102
Reference
Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -25°C ... +85°C
Parameter
Symbol
Limit Values
Min
Typ
Max
Unit
Test Conditions
Power Amplifier Output (Pin 14)
Output Power 2) at 915 MHz
transformed to 50 Ohm.
POUT, 915
-2.3
0.2
1.8
dBm
VS = 2.1 V
POUT, 915
-2.0
2
4.9
dBm
VS = 3.0 V
VFSEL = open
POUT, 915
-1.7
3.2
7.2
dBm
VS = 4.0 V
V
pin open
Frequency Range Selection (Pin 15)
Transmit frequency 915 MHz
VFSEL
Transmit frequency 457 MHz
VFSEL
Input bias current FSEL
IFSEL
Input bias current FSEL
IFSEL
0
0.5
V
30
µA
VFSEL = VS
µA
VFSEL = 0 V
-20
Crystal Frequency Selection (Pin 16)
Crystal frequency 7.15 MHz
VCSEL
Crystal frequency 14.3 MHz
VCSEL
Input bias current CSEL
ICSEL
Input bias current CSEL
ICSEL
0
0.2
50
-25
V
V
pin open
µA
VCSEL = VS
µA
VCSEL = 0 V
1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA
2) Matching circuitry as used in the 50 Ohm-Output Testboard for 915 MHz operation.
Range @ 2.1 V, +25°C: 0.2 dBm +/- 1.0 dBm
Temperature dependency at 2.1 V: +0.6 [email protected]°C and -1.5 [email protected]+85°C, reference +25°C.
Range @ 3.0 V, +25°C: 2.0 dBm +/- 2.0 dBm
Temperature dependency at 3.0 V: +0.9 [email protected]°c and -2.0 [email protected]+85°C, reference +25°C.
Range @ 4.0 V, +25°C: 3.2 dBm +/- 2.7 dBm
Temperature dependency at 4.0 V: +1.3 [email protected]°c and -2.2 [email protected]+85°C, reference +25°C.
Tolerances of the passive elements not taken into account.
A smaller load impedance reduces the supply-voltage dependency.
A higher load impedance reduces the temperature dependency.
Wireless Components
5-8
Specification, October 2001