Wireless Components ASK/FSK Transmitter 315 MHz TDK 5101 Version 1.0 Specification October 2002 Preliminary Revision History Current Version: Version 1.0 as of 31.10.2002 Previous Version: Version 0.1 as of February 2002 Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) 4-4 4-4 BOM of 50 Ohm-Output Testboard defined 4-7 4-5 ... 4-13 Ohm-Output Testboard Measurement results added Application Hints on the Power Amplifier added 5-2 5-2 ESD-specification added 5-3, 5-6 5-3, 5-6 VCO-frequency range specified 5-4, 5-7 5-4, 5-7 Tolerances of Lcosc specified Value of Iclkout corrected 5-5, 5-8 5-5, 5-8 Tolerances of output power specified ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. Edition 31.10.2001 Published by Infineon Technologies AG, Balanstraße 73, 81541 München © Infineon Technologies AG 2002. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. 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TDK 5101 Product Info Product Info General Description Features Applications The TDK 5101 is a single chip ASK/ Package FSK transmitter for the frequency band 311-317 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additionally features like a power down mode, a low power detect and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation. ■ fully integrated frequency synthesizer ■ voltage supply range 2.1 ... 4 V ■ VCO without external components ■ temperature range -40 ... +125°C ■ high efficiency power amplifier ■ power down mode ■ frequency range 311 ... 317 MHz ■ low voltage sensor ■ ASK/FSK modulation ■ programmable divided clock output for µC ■ low supply current (typically 7mA) ■ low external component count ■ Keyless entry systems ■ Alarm systems ■ Remote control systems ■ Communication systems Ordering Information Type Ordering Code Package TDK 5101 Q67100-H2062 P-TSSOP-16 available on tape and reel Wireless Components Product Info Specification, October 2002 2 Product Description Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 TDK 5101 Product Description 2.1 Overview The TDK 5101 is a single chip ASK/FSK transmitter for the frequency band 311317 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features like a power down mode, a low power detect and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation. 2.2 Applications ■ Keyless entry systems ■ Remote control systems ■ Alarm systems ■ Communication systems 2.3 Features Wireless Components ■ fully integrated frequency synthesizer ■ VCO without external components ■ high efficiency power amplifier ■ frequency range 311 MHz ... 317 MHz ■ ASK/FSK modulation ■ low supply current (typically 7 mA) ■ voltage supply range 2.1 V ... 4 V ■ temperature range -40°C ... 125°C ■ power down mode ■ low voltage sensor ■ programmable divided clock output for µC ■ low external component count 2-2 Specification, October 2002 TDK 5101 Product Description 2.4 Package Outlines Figure 2-1 Wireless Components P-TSSOP-16 2-3 Specification, October 2002 3 Functional Description Contents of this Chapter 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.5.1 3.4.5.2 3.4.5.3 3.4.5.4 3.4.6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Power mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Recommended timing diagrams for ASK- and FSK-Modulation . . 3-12 TDK 5101 Functional Description 3.1 Pin Configuration PDWN 1 16 CSEL LPD 2 15 FSEL VS 3 14 PAOUT LF 4 13 PAGND TDK 5101 GND 5 12 FSKGND ASKDTA 6 11 FSKOUT FSKDTA 7 10 COSC CLKOUT 8 9 CLKDIV Pin_config.wmf Figure 3-1 IC Pin Configuration Table 3-1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Wireless Components Symbol PDWN LPD VS LF GND ASKDTA FSKDTA CLKOUT CLKDIV COSC FSKOUT FSKGND PAGND PAOUT FSEL CSEL Function Power Down Mode Control Low Power Detect Output Voltage Supply Loop Filter Ground Amplitude Shift Keying Data Input Frequency Shift Keying Data Input Clock Driver Output Clock Divider Control Crystal Oscillator Input Frequency Shift Keying Switch Output Frequency Shift Keying Ground Power Amplifier Ground Power Amplifier Output Frequency Range Selection: Has to be shorted to ground for 315 MHz operation Crystal Frequency Selection: Has to be left open 3-2 Specification, October 2002 TDK 5101 Functional Description 3.2 Pin Definitions and Functions Table 3-2 Pin No. Symbol 1 PDWN Function Interface Schematic1) Disable pin for the complete transmitter circuit. VS 40 µA ∗ (ASKDTA+FSKDTA) A logic low (PDWN < 0.7 V) turns off all transmitter functions. 5 kΩ A logic high (PDWN > 1.5 V) gives access to all transmitter functions. 1 "ON" PDWN input will be pulled up by 40 µA internally by setting FSKDTA or ASKDTA to a logic high-state. 150 kΩ 250 kΩ 2 LPD This pin provides an output indicating the low-voltage state of the supply voltage VS. VS VS < 2.15 V will set LPD to the low-state. 40 µA 2 300 Ω 3 VS Wireless Components An internal pull-up current of 40 µA gives the output a high-state at supply voltages above 2.15 V. This pin is the positive supply of the transmitter electronics. An RF bypass capacitor should be connected directly to this pin and returned to GND (pin 5) as short as possible. 3-3 Specification, October 2002 TDK 5101 Functional Description 4 LF Output of the charge pump and input of the VCO control voltage. The loop bandwidth of the PLL is 150 kHz when only the internal loop filter is used. The loop bandwidth may be reduced by applying an external RC network referencing to the positive supply VS (pin 3). VS 140 pF 15 pF 35 kΩ 10 kΩ 4 5 GND 6 ASKDTA VS General ground connection. VS Digital amplitude modulation can be imparted to the Power Amplifier through this pin. +1.2 V A logic high (ASKDTA > 1.5 V or open) enables the Power Amplifier. 60 kΩ 6 +1.1 V 90 kΩ 50 pF 7 30 µA FSKDTA VS A logic low (ASKDTA < 0.5 V) disables the Power Amplifier. Digital frequency modulation can be imparted to the Xtal Oscillator by this pin. The VCO-frequency varies in accordance to the frequency of the reference oscillator. +1.2 V 60 kΩ 7 +1.1 V 90 kΩ 30 µA A logic high (FSKDTA > 1.5V or open) sets the FSK switch to a high impedance state. A logic low (FSKDTA < 0.5 V) closes the FSK switch from FSKOUT (pin 11) to FSKGND (pin 12). A capacitor can be switched to the reference crystal network this way. The Xtal Oscillator frequency will be shifted giving the designed FSK frequency deviation. Wireless Components 3-4 Specification, October 2002 TDK 5101 Functional Description 8 CLKOUT Clock output to supply an external device. An external pull-up resistor has to be added in accordance to the driving requirements of the external device. A clock frequency of 2.46 MHz is selected by a logic low at CLKDIV input (pin9). A clock frequency of 615 kHz is selected by a logic high at CLKDIV input (pin9). VS 8 300 Ω 9 CLKDIV This pin is used to select the desired clock division rate for the CLKOUT signal. VS +1.2 V VS A logic low (CLKDIV < 0.2 V) applied to this pin selects the 2.46 MHz output signal at 5 µA CLKOUT (pin 8). 60 kΩ A logic high (CLKDIV open) applied to this +0.8 V pin selects the 615 kHz output signal at 60 kΩ CLKOUT (pin 8). 9 10 COSC VS VS 6 kΩ 10 This pin is connected to the reference oscillator circuit. The reference oscillator is working as a negative impedance converter. It presents a negative resistance in series to an inductance at the COSC pin. 100 µA 11 FSKOUT This pin is connected to a switch to FSKGND (pin 12). VS VS The switch is closed when the signal at FSKDTA (pin 7) is in a logic low state. The switch is open when the signal at FSKDTA (pin 7) is in a logic high state. 200 µA 1.5 kΩ 11 FSKOUT can switch an additional capacitor to the reference crystal network to pull the crystal frequency by an amount resulting in the desired FSK frequency shift of the transmitter output frequency. 12 12 FSKGND Wireless Components Ground connection for FSK modulation output FSKOUT. 3-5 Specification, October 2002 TDK 5101 Functional Description 13 PAGND Ground connection of the power amplifier. The RF ground return path of the power amplifier output PAOUT (pin 14) has to be concentrated to this pin. 14 PAOUT RF output pin of the transmitter. 14 A DC path to the positive supply VS has to be supplied by the antenna matching network. 13 15 FSEL This pin has to be shorted to ground to select the 315 MHz transmitter frequency range. +1.2 V VS 30 kΩ 15 +1.1 V A logic low (FSEL < 0.5 V) applied to this pin sets the transmitter to the 315 MHz frequency range. 90 kΩ 30 µA 16 CSEL VS +1.2 V A logic high (FSEL open) applied to this pin sets the transmitter to the 630 MHz frequency range. This pin is used to select the desired reference frequency. VS 5 µA 60 kΩ 16 A logic high (CSEL open) applied to this pin sets the internal frequency divider to accept a reference frequency of 9.84 MHz. +0.8 V 60 kΩ 1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode. In Power Down Mode, the values are zero or high-ohmic. Wireless Components 3-6 Specification, October 2002 Wireless Components GND POWER DOWN MODE GND VS 3-7 Functional Block diagram 3 1 7 12 ASK DATA INPUT 11 6.78/13.56 10 MHz XTAL Osc PD :128/64 5 Power Supply OR 6 VCO LOW POWER DETECT OUTPUT 2 Low voltage Sensor 2.2V :1/2 Power AMP 14 13 CLKDIV 9 :2/8 :4/16 16 CRYSTAL 6.78/13.56 4 15 LOOP FILTER 434/868 MHz ASK 6 DATA INPUT POWER AMPLIFIER ON POWER AMPLIFIER GND TDK 5101 Functional Description CLKOUT Funct_Block_Diagram.wmf Specification, October 2002 8 LF POWER AMPLIFIER OUTPUT 3.3 Functional Block diagram Figure 3-2 FSK DATA INPUT TDK 5101 Functional Description 3.4 Functional Blocks 3.4.1 PLL Synthesizer The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO), an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the VCO is 630 MHz. The oscillator signal is fed both, to the synthesizer divider chain and to the power amplifier. The overall division ratio of the asynchronous divider chain is 64. The phase detector is a Type IV PD with charge pump. The passive loop filter is realized on chip. In all 315 MHz applications, the FSEL pin is shorted to ground (logic low) and the CSEL pin is not connected (logic high). 3.4.2 Crystal Oscillator The crystal oscillator operates at 9.84 MHz. Frequencies of 615 kHz or 2.46 MHz are available at the clock output CLKOUT (pin 8) to drive the clock input of a micro controller. The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9) Table 3-3 CLKDIV (pin 9) 1) 2.46 MHz 615 kHz Low Open2) 1) Low: 2) Open: CLKOUT Frequency Voltage at pin < 0.2 V Pin open To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount by switching an external capacitor via FSKOUT (pin 11). The condition of the switch is controlled by the signal at FSKDTA (pin 7). Table 3-4 FSKDTA (pin7) 1) Low Open2), High3) 1) Low: 2) Open: 3) High: Wireless Components FSK Switch CLOSED OPEN Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V 3-8 Specification, October 2002 TDK 5101 Functional Description 3.4.3 Power Amplifier For operation at 315 MHz, the power amplifier is fed with the VCO frequency divided by 2. It is possible to feed the power amplifier directly from the voltage controlled oscillator. This is controlled by FSEL (pin 15) as described in the table below. Table 3-5 FSEL (pin 15) Radiated Frequency Band 1) 315 MHz 630 MHz Low Open2) 1) Low: 2) Open: Voltage at pin < 0.5 V Pin open In all 315 MHz applications, the pin FSEL is connected to ground. The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6). Table 3-6 ASKDTA (pin 6) 1) Low Open2), High3) 1) Low: 2) Open: 3) High: Power Amplifier OFF ON Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V The Power Amplifier has an Open Collector output at PAOUT (pin 14) and requires an external pull-up coil to provide bias. The coil is part of the tuning and matching LC circuitry to get best performance with the external loop antenna. To achieve the best power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 14) should be twice the supply voltage. The power amplifier has its own ground pin PAGND (pin 13) in order to reduce the amount of coupling to the other circuits. 3.4.4 Low Power Detect The supply voltage is sensed by a low power detector. When the supply voltage drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To minimize the external component count, an internal pull-up current of 40 µA gives the output a high-state at supply voltages above 2.15 V. The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off the PA as soon as the supply voltage drops below 2.15 V or it can be used to inform a micro-controller to stop the transmission after the current data packet. Wireless Components 3-9 Specification, October 2002 TDK 5101 Functional Description 3.4.5 Power Modes The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE MODE and the TRANSMIT MODE. 3.4.5.1 Power Down Mode In the POWER DOWN MODE the complete chip is switched off. The current consumption is typically 0.3 nA at 3 V 25°C. This current doubles every 8°C. The values for higher temperatures are typically 14 nA at 85°C and typically 600 nA at 125°C. 3.4.5.2 PLL Enable Mode In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off to avoid undesired power radiation during the time the PLL needs to settle. The turn on time of the PLL is determined mainly by the turn on time of the crystal oscillator and is less than 1 msec when the specified crystal is used. The current consumption is typically 3.5 mA. 3.4.5.3 Transmit Mode In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too. The current consumption of the IC is typically 7 mA when using a proper transforming network at PAOUT, see Figure 4-1. 3.4.5.4 Power mode control The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1). When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up internally. Forcing the voltage at the pins low overrides the internally set state. Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open. The principle schematic of the power mode control circuitry is shown in Figure 3-5. Wireless Components 3 - 10 Specification, October 2002 TDK 5101 Functional Description PDWN ASKDTA OR FSKDTA On Bias Source Bias Voltage 120 kΩ 120 kΩ FSKOUT FSK On PLL 315 MHz PA PAOUT IC Power_Mode.wmf Figure 3-5 Power mode control circuitry Table 3-7 provides a listing of how to get into the different power modes Table 3-7 PDWN FSKDTA ASKDTA Low1) Low, Open Low, Open Open2) Low Low High3) Low, Open, High Low Open High Low High Low, Open, High Open, High Open High Open, High Open Low, Open, High High 1) Low: 2) Open: 3) High: MODE POWER DOWN PLL ENABLE TRANSMIT Voltage at pin < 0.7 V (PDWN) Voltage at pin < 0.5 V (FSKDTA, ASKDTA) Pin open Voltage at pin > 1.5 V Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not recommended. Wireless Components 3 - 11 Specification, October 2002 TDK 5101 Functional Description 3.4.6 Recommended timing diagrams for ASK- and FSK-Modulation ASK Modulation using FSKDTA and ASKDTA, PDWN not connected Modes: Power Down PLL Enable Transmit High FSKDTA Low to t DATA Open, High ASKDTA Low to t min. 1 msec. ASK_mod.wmf Figure 3-6 ASK Modulation FSK Modulation using FSKDTA and ASKDTA, PDWN not connected Modes: Power Down PLL Enable Transmit DATA High FSKDTA Low to t to t High ASKDTA Low min. 1 msec. FSK_mod.wmf Figure 3-7 Wireless Components FSK Modulation 3 - 12 Specification, October 2002 TDK 5101 Functional Description Alternative ASK Modulation, FSKDTA not connected. Modes: Power Down PLL Enable Transmit High PDWN Low to t DATA Open, High ASKDTA Low to t min. 1 msec. Alt_ASK_mod.wmf Figure 3-8 Alternative ASK Modulation Alternative FSK Modulation Modes: Power Down PLL Enable Transmit High PDWN Low to t to t Open, High ASKDTA Low DATA Open, High FSKDTA Low to t min. 1 msec. Alt_FSK_mod.wmf Figure 3-9 Wireless Components Alternative FSK Modulation 3 - 13 Specification, October 2002 4 Applications Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 4.6 4.7 50 Ohm-Output Testboard Schematic . . . . . . . . . . . . . . . . . . . . . . . . 4-2 50 Ohm-Output Testboard Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Bill of material (50 Ohm-Output Testboard) . . . . . . . . . . . . . . . . . . . . 4-4 50 Ohm-Output Testboard: Measurement results . . . . . . . . . . . . . . . 4-5 Application Hints on the crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 4-6 Design hints on the buffered clock output (CLKOUT). . . . . . . . . . . . . 4-8 Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . 4-9 TDK 5101 Applications 4.1 50 Ohm-Output Testboard Schematic X2SMA C8 C2 C4 L2 L1 VCC C7 C3 C6 10 9 7 8 11 12 13 14 15 16 Q1 0.615 (2.46) MHz VCC 6 5 4 3 2 VCC 1 TDK5101 C1 T1 R3A R3F R4 R2 FSK ASK R1 C5 X1SMA 50ohm_test_v5.wmf Figure 4-1 Wireless Components 50 Ω-Output testboard schematic 4-2 Specification, October 2002 TDK 5101 Applications 4.2 50 Ohm-Output Testboard Layout Wireless Components Figure 4-2 Top Side of TDK 5101-Testboard with 50 Ω-Output. It is the same testboard as for the TDA 5100. Figure 4-3 Bottom Side of TDK 5101-Testboard with 50 Ω-Output. It is the same testboard as for the TDA 5100. 4-3 Specification, October 2002 TDK 5101 Applications 4.3 Bill of material (50 Ohm-Output Testboard) Table 4-1 Bill of material Part R1 ASK 315 MHz FSK 315 MHz Specification 4.7 kΩ 4.7 kΩ 0805, ± 5% 12 kΩ 0805, ± 5% R2 R3A 15 kΩ 0805, ± 5% R3F Wireless Components 15 kΩ 0805, ± 5% R4 open open 0805, ± 5% C1 47 nF 47 nF 0805, X7R, ± 10% C2 33 pF 33 pF 0805, COG, ± 5% C3 5.6 pF 5.6 pF 0805, COG, ± 0.1 pF C4 330 pF 330 pF 0805, COG, ± 5% C5 1 nF 1 nF 0805, X7R, ± 10% C6 8.2 pF 8.2 pF 0805, COG, ± 0.1 pF C7 0 Ω Jumper 47 pF 0805, COG, ± 5% 0805, 0Ω Jumper C8 22 pF 22 pF 0805, COG, ± 5% L1 150 nH 150 nH TOKO LL2012-J L2 56 nH 56 nH TOKO LL2012-J Q1 9843.75 kHz, CL=12pF 9843.75 kHz, CL=12pF Tokyo Denpa TSS-3B 9843.75 kHz Spec.No. 10-50221 IC1 TDK 5101 TDK 5101 T1 Push-button Push-button replaced by a short B1 Battery clip Battery clip HU2031-1, RENATA X1 SMA-S SMA-S SMA standing X2 SMA-S SMA-S SMA standing 4-4 Specification, October 2002 TDK 5101 Applications 4.4 50 Ohm-Output Testboard: Measurement results Note the specified operating range: 2.1 V to 4.0 V and −40°C to +125°C. Pout over temperature TDK5101 315 MHz 9,00 8,00 7,00 4,0 V Pout [dBm] 6,00 3,0 V 5,00 2,1 V 4,00 2,0 V 1,9 V 3,00 2,00 1,00 0,00 -50 0 50 100 150 T [°C] Pout_over_Temp_315.wmf Figure 4-4 Pout over Temperature of the 50Ω-testboard with TDK5101 at 315 MHz Is over temperature TDK5101 315 MHz 9 8,5 8 4,0 V Is [mA] 7,5 3,0 V 2,1 V 7 2,0 V 6,5 1,9 V 6 5,5 5 -50 0 50 100 150 T [°C] is_over_temp_315.wmf Figure 4-5 Wireless Components Is over temperature of the 50Ω-testboard with TDK5101 at 315 MHz 4-5 Specification, October 2002 TDK 5101 Applications 4.5 Application Hints on the crystal oscillator As mentioned before, the crystal oscillator achieves a turn on time less than 1 msec. To achieve this, a NIC oscillator type is implemented in the TDK 5101. The input impedance of this oscillator is a negative resistance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv. -R L f, CL Cv IC Cv = 1 1 + ω 2L CL (1) CL: crystal load capacitance for nominal frequency ω: angular frequency L: inductance of the crystal oscillator Example for the ASK-Mode: Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced by a short to ground. Assume a crystal frequency of 9.84 MHz and a crystal load capacitance of CL = 12 pF. The inductance L at 9.84 MHz is about 4.4 µH. Therefore C6 is calculated to 10 pF. Cv = Wireless Components 4-6 1 1 +ω 2L CL = C6 Specification, October 2002 TDK 5101 Applications Example for the FSK-Mode: FSK modulation is achieved by switching the load capacitance of the crystal as shown below. FSKDTA FSKOUT Csw -R L f, CL Cv1 Cv2 COSC IC The frequency deviation of the crystal oscillator is multiplied with the divider factor N of the Phase Locked Loop to the output of the power amplifier. In case of small frequency deviations (up to +/- 1000 ppm), the two desired load capacitances can be calculated with the formula below. 2(C 0 + CL ) ∆f ) (1 + N * f1 C1 2(C 0 + CL ) ∆f ) 1± (1 + N * f1 C1 CL # C 0 CL ± = C L: C 0: f: ω: N: df: crystal load capacitance for nominal frequency shunt capacitance of the crystal frequency ω = 2πf: angular frequency division ratio of the PLL peak frequency deviation Because of the inductive part of the TDK 5101, these values must be corrected by formula 1). The value of Cv± can be calculated. Wireless Components 4-7 Specification, October 2002 TDK 5101 Applications If the FSK switch is closed, Cv- is equal to Cv1 (C6 in the application diagram). If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated. Cv 2 = C 7 = Csw ∗ Cv1 − (Cv + ) ∗ (Cv1 + Csw) (Cv + ) − Cv1 Csw: parallel capacitance of the FSK switch (3 pF incl. layout parasitics) Remark: These calculations are only approximations. The necessary values depend on the layout also and must be adapted for the specific application board. The 50Ω-Output testboard shows an FSK-deviation of +/- 22.5 kHz, typically. 4.6 Design hints on the buffered clock output (CLKOUT) The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be connected between this pin and the positive supply voltage. The value of RL is depending on the clock frequency and the load capacitance CLD (PCB board plus input capacitance of the microcontroller). RL can be calculated to: RL = 1 fCLKOUT * 8 * CLD Table 4-2 fCLKOUT= 615 kHz CLD[pF] RL[kOhm] CLD[pF] RL[kOhm] 5 39 5 10 10 18 10 4.7 20 10 20 2.2 Remark: Wireless Components fCLKOUT= 2.46 MHz To achieve a low current consumption and a low spurious radiation, the largest possible RL should be chosen. 4-8 Specification, October 2002 TDK 5101 Applications 4.7 Application Hints on the Power-Amplifier The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of θ<<π. A frequency selective network at the amplifier output passes the fundamental frequency component of the pulse spectrum of the collector current to the load. The load and its resonance transformation to the collector of the power amplifier can be generalized by the equivalent circuit of Figure 4-6. The tank circuit L//C//RL in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the transmitter. VS L C RL Equivalent_power_wmf. Figure 4-6 Equivalent power amplifier tank circuit The optimum load at the collector of the power amplifier for “critical” operation under idealized conditions at resonance is: R LC = VS 2 2 PO The theoretical value of RLC for an RF output power of Po= 5 dBm (3.16 mW) is: R LC = 32 = 1423 Ω 2 * 0 .00316 “Critical” operation is characterized by the RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage VS. The high degree of efficiency under “critical” operating conditions can be explained by the low power losses at the transistor. During the conducting phase of the transistor, its collector voltage is very small. This way the power loss of the transistor, equal to iC*uCE , is minimized. This is particularly true for small current flow angles of θ<<π. In practice the RF-saturation voltage of the PA transistor and other parasitics reduce the “critical” RLC. Wireless Components 4-9 Specification, October 2002 TDK 5101 Applications The output power Po is reduced by operating in an “overcritical” mode characterised by RL > RLC. The power efficiency (and the bandwidth) increase when operating at a slightly higher RL, as shown in Figure 4-7. The collector efficiency E is defined as E= PO VS I C The diagram of Figure 4-7 was measured directly at the PA-output at VS = 3 V. Losses in the matching circuitry decrease the output power by about 1.5 dB. As can be seen from the diagram, 700 Ω is the optimum impedance for operation at 3 V. For an approximation of ROPT and POUT at other supply voltages those 2 formulas can be used: ROPT ~ VS and POUT ~ ROPT 0 *E o [m W ] 7 6 5 4 3 1 0 *E 2 Po 1 0 0 1000 2000 3000 R L [O h m ] Power_E_vs_RL.wmf Figure 4-7 Output power Po (mW) and collector efficiency E vs. load resistor RL. The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of “overcritical” operation. The depth of this dip will increase with higher values of RL. Wireless Components 4 - 10 Specification, October 2002 TDK 5101 Applications As Figure 4-8 shows, detuning beyond the bandwidth of the matching circuit results in a significant increase of collector current of the power amplifier and in some loss of output power. This diagram shows the data for the circuit of the test board at the frequency of 315 MHz. The effective load resistance of this circuit is RL = 700 Ω, which is the optimum impedance for operation at 3 V. This will lead to a dip of the collector current of approx. 40%. Ic [mA ] Po [d B m] 6 5 4 3 2 1 0 420 430 440 450 f [M H z ] pout_vs_frequ.wmf Figure 4-8 Output power and collector current vs. frequency C3, L2-C2 and C8 are the main matching components which are used to transform the 50 Ω load at the SMA-RF-connector to a higher impedance at the PA-output (700 Ω @ 3 V). L1 can be used for some finetuning of the resonant frequency but should not become too small in order to keep its losses low. The transformed impedance of 700+j0 Ω at the PA-output-pin can be verified with a network analyzer using the following measurement procedure: 1. Calibrate your network analyzer. 2. Connect some short, low-loss 50 Ω cable to your network analyzer with an open end on one side. Semirigid cable works best. 3. Use the „Port Extension“ feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable. 4. Connect the center-conductor of the cable to the solder pad of the pin „PA“ of the IC. The outer conductor has to be grounded. Very short connections have to be used. Do not remove the IC or any part of the matching-components! 5. Screw a 50 Ω dummy-load on the RF-I/O-SMA-connector 6. Be sure that your network analyzer is AC-coupled and turn on the power supply of the IC. The TDK5101 must not be in Transmit-Mode. 7. Measure the S-parameter S11 Wireless Components 4 - 11 Specification, October 2002 TDK 5101 Applications Plot0.pcx Figure 4-9 Sparam_measured_200M Above you can see the measurement of the evalboard with a span of 100 MHz. The evalboard has been optimized for 3 V. The load is about 700+j0 Ω at the transmit frequency. A tuning-free realization requires a careful design of the components within the matching network. A simple linear CAE-tool will help to see the influence of tolerances of matching components. Suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. The total spectrum of a typical 50 Ω-Output testboard can be summarized as: Table 4-3 Output Power 315 MHz Testboard Frequency 315 MHz +5 dBm 315 MHz − 9.84 MHz −72 dBc 315 MHz + 9.84 MHz −74 dBc harmonic −49 dBc 3rd harmonic −43 dBc 2 Wireless Components nd 4 - 12 Specification, October 2002 5 Reference Contents of this Chapter 5.1 5.2 5.3 5.3.1 5.3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics at 3V, 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics at 2.1 V ... 4.0 V, -40°C ... +125°C. . . . . . . . . 5-6 TDK 5101 Reference 5.1 Absolute Maximum Ratings The AC / DC characteristic limits are not guaranteed. The maximum ratings must not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result. Table 5-1 Symbol Parameter Limit Values Min Max Unit Junction Temperature TJ -40 150 °C Storage Temperature Ts -40 125 °C 230 K/W Thermal Resistance RthJA Remarks VS -0.3 4.0 V Voltage at any pin excluding pin 14 Vpins -0.3 VS + 0.3 V Voltage at pin 14 Vpin14 -0.3 2 * VS V Current into pin 11 Ipin11 -10 10 mA ESD integrity, all pins VESD -1 +1 kV JEDEC Standard JESD22-A114-B ESD integrity, all pins excluding pin 14 VESD -2 +2 kV JEDEC Standard JESD22-A114-B Supply voltage No ESD-Diode to VS Ambient Temperature under bias: TA=-40°C to +125°C Note: All voltages referred to ground (pins) unless stated otherwise. Pins 5, 12 and 13 are grounded. 5.2 Operating Range Within the operational range the IC operates as described in the circuit description. Table 5-2 Parameter Symbol Limit Values Min Max Unit Supply voltage VS 2.1 4.0 V Ambient temperature TA -40 125 °C Wireless Components 5-2 Test Conditions Specification, October 2002 TDK 5101 Reference 5.3 AC/DC Characteristics 5.3.1 AC/DC Characteristics at 3V, 25°C Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C Parameter Symbol Limit Values Min Unit Typ Max Test Conditions Current consumption Power down mode IS PDWN 0.3 100 nA V (Pins 1, 6 and 7) < 0.2 V PLL enable mode IS PLL_EN 3.5 4.2 mA Transmit mode IS TRANSM 7 9 mA Load tank see Figure 4-1 and 4-2 Power Down Mode Control (Pin 1) Power down mode VPDWN 0 0.7 V VASKDTA < 0.2 V VFSKDTA < 0.2 V PLL enable mode VPDWN 1.5 VS V VASKDTA < 0.5 V Transmit mode VPDWN 1.5 VS V VASKDTA > 1.5 V Input bias current PDWN IPDWN 30 µA VPDWN = VS Low Power Detect Output (Pin 2) Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS Input current low voltage I LPD2 1 mA VS = 1.9 V ... 2.1 V V fVCO = 630 MHz 325 MHz VFSEL = 0 V fOUT = fVCO / 2 Loop Filter (Pin 4) VCO tuning voltage VLF Output frequency range 315 MHz-band fOUT, 315 VS - 1.4 VS - 0.7 305 315 ASK Modulation Data Input (Pin 6) ASK Transmit disabled VASKDTA 0 0.5 V ASK Transmit enabled VASKDTA 1.5 VS V Input bias current ASKDTA IASKDTA 30 µA VASKDTA = VS Input bias current ASKDTA IASKDTA µA VASKDTA = 0 V ASK data rate fASKDTA Wireless Components -20 20 5-3 kHz Specification, October 2002 TDK 5101 Reference Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C Parameter Symbol Limit Values Min Typ Unit Test Conditions Max FSK Modulation Data Input (Pin 7) FSK Switch on VFSKDTA 0 0.5 V FSK Switch off VFSKDTA 1.5 VS V Input bias current FSKDTA IFSKDTA 30 µA VFSKDTA = VS Input bias current FSKDTA IFSKDTA µA VFSKDTA = 0 V FSK data rate fFSKDTA 20 kHz Output current (High) ICLKOUT 5 µA VCLKOUT = VS Saturation Voltage (Low)1) VSATL 0.56 V ICLKOUT = 1 mA 0.2 V -20 Clock Driver Output (Pin 8) Clock Divider Control (Pin 9) Setting Clock Driver output frequency fCLKOUT=2.46 MHz VCLKDIV Setting Clock Driver output frequency fCLKOUT=615 kHz VCLKDIV Input bias current CLKDIV ICLKDIV Input bias current CLKDIV ICLKDIV 0 30 -20 V pin open µA VCLKDIV = VS µA VCLKDIV = 0 V Crystal Oscillator Input (Pin 10) Load capacitance CCOSCmax Serial Resistance of the crystal 3.4 Input inductance of the COSC pin 4.4 5 pF 100 Ω f = 9.84 MHz 5.4 µH f = 9.84 MHz FSK Switch Output (Pin 11) On resistance RFSKOUT 220 Ω VFSKDTA = 0 V On capacitance CFSKOUT 6 pF VFSKDTA = 0 V Off resistance RFSKOUT kΩ VFSKDTA = VS Off capacitance CFSKOUT pF VFSKDTA = VS Wireless Components 10 1.5 5-4 Specification, October 2002 TDK 5101 Reference Table 5-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25°C Parameter Symbol Limit Values Min Typ Max 4 5 6 Unit Test Conditions dBm fOUT = 315 MHz VFSEL = 0 V Power Amplifier Output (Pin 14) Output Power2) transformed to 50 Ohm POUT315 Frequency Range Selection (Pin 15) Transmit frequency 315 MHz VFSEL Input bias current FSEL IFSEL Input bias current FSEL IFSEL 0 0.5 V 30 µA VFSEL = VS µA VFSEL = 0 V V pin open µA VCSEL = VS µA VCSEL = 0 V -20 Crystal Frequency Selection (Pin 16) Crystal frequency 9.84 MHz VCSEL Input bias current CSEL ICSEL Input bias current CSEL ICSEL 1) 2) 50 -25 Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA Power amplifier in overcritical C-operation. Matching circuitry as used in the 50 Ohm-Output Testboard. Tolerances of the passive elements not taken into account. Wireless Components 5-5 Specification, October 2002 TDK 5101 Reference 5.3.2 AC/DC Characteristics at 2.1 V ... 4.0 V, -40°C ... +125°C Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C Parameter Symbol Limit Values Min Typ Unit Test Conditions Max Current consumption Power down mode IS PDWN PLL enable mode IS PLL_EN Transmit mode IS TRANSM 4 µA 3.5 4.6 mA 7 9.5 mA Load tank see Figure 4-1 and 4-2 V (Pins 1, 6, and 7) < 0.2 V Power Down Mode Control (Pin 1) Power down mode VPDWN 0 0.5 V VASKDTA < 0.2 V VFSKDTA < 0.2 V PLL enable mode VPDWN 1.5 VS V VASKDTA < 0.5 V Transmit mode VPDWN 1.5 VS V VASKDTA > 1.5 V Input bias current PDWN IPDWN 38 µA VPDWN = VS Low Power Detect Output (Pin 2) Internal pull up current I LPD1 30 µA VS = 2.3 V ... VS Input current low voltage I LPD2 0.5 mA VS = 1.9 V ... 2.1 V V fVCO = 630 MHz 317 MHz VFSEL = 0 V fOUT = fVCO / 2 Loop Filter (Pin 4) VCO tuning voltage VLF Output frequency range 1) 315 MHz-band fOUT, 315 VS - 1.85 311 VS - 0.45 315 ASK Modulation Data Input (Pin 6) ASK Transmit disabled VASKDTA 0 0.5 V ASK Transmit enabled VASKDTA 1.5 VS V Input bias current ASKDTA IASKDTA 33 µA VASKDTA = VS Input bias current ASKDTA IASKDTA µA VASKDTA = 0 V ASK data rate fASKDTA -20 20 kHz 1) The output-frequency range can be increased by limiting the temperature and supply voltage range. Minimum fOUT − 1 MHz => Minimum Tamb + 10°C Maximum fOUT + 1 MHz => Maximum Tamb − 10°C Maximum fOUT + 1 MHz => Minimum VS + 50 mV, max. + 20 MHz. Wireless Components 5-6 Specification, October 2002 TDK 5101 Reference Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C Parameter Symbol Limit Values Min Typ Unit Test Conditions Max FSK Modulation Data Input (Pin 7) FSK Switch on VFSKDTA 0 0.5 V FSK Switch off VFSKDTA 1.5 VS V Input bias current FSKDTA IFSKDTA 35 µA VFSKDTA = VS Input bias current FSKDTA IFSKDTA µA VFSKDTA = 0 V FSK data rate fFSKDTA 20 kHz Output current (High) ICLKOUT 5 µA VCLKOUT = VS Saturation Voltage (Low)1) VSATL 0.5 V ICLKOUT = 0.6 mA 0.2 V -20 Clock Driver Output (Pin 8) Clock Divider Control (Pin 9) Setting Clock Driver output frequency fCLKOUT=2.46 MHz VCLKDIV Setting Clock Driver output frequency fCLKOUT=615 kHz VCLKDIV Input bias current CLKDIV ICLKDIV Input bias current CLKDIV ICLKDIV 0 30 -20 V pin open µA VCLKDIV = VS µA VCLKDIV = 0 V Crystal Oscillator Input (Pin 10) Load capacitance CCOSCmax Serial Resistance of the crystal Input inductance of the COSC pin 3.2 4.6 5 pF 100 Ω f = 9.84 MHz 6.3 µH f = 9.84 MHz FSK Switch Output (Pin 11) On resistance RFSKOUT 280 Ω VFSKDTA = 0 V On capacitance CFSKOUT 6 pF VFSKDTA = 0 V Off resistance RFSKOUT kΩ VFSKDTA = VS Off capacitance CFSKOUT pF VFSKDTA = VS 10 1.5 1) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA Wireless Components 5-7 Specification, October 2002 TDK 5101 Reference Table 5-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C Parameter Symbol Limit Values Min Typ Unit Test Conditions dBm VS = 2.1 V dBm VS = 3.0 V dBm VS = 4.0 V Max Power Amplifier Output (Pin 14) Output Power 1) at 315 MHz transformed to 50 Ohm. POUT, 315 -0.5 2.2 POUT, 315 0.5 5 VFSEL = 0 V POUT, 315 1.5 7.4 7 Frequency Range Selection (Pin 15) Transmit frequency 315 MHz VFSEL Input bias current FSEL IFSEL Input bias current FSEL IFSEL 0 0.5 V 35 µA VFSEL = VS µA VFSEL = 0 V V pin open µA VCSEL = VS µA VCSEL = 0 V -20 Crystal Frequency Selection (Pin 16) Crystal frequency 9.84 MHz VCSEL Input bias current CSEL ICSEL Input bias current CSEL ICSEL 55 -25 1) Matching circuitry as used in the 50 Ohm-Output Testboard. Tolerances of the passive elements not taken into account. Range @ 2.1 V, +25°C: 2.2 dBm +/- 0.7 dBm Typ. temperature dependency at 2.1 V: +0.3 dBm@-40°C and -1.4 dBm@+125°C, reference +25°C Range @ 3.0 V, +25°C: 5.0 dBm +/- 1.0 dBm Typ. temperature dependency at 3.0 V: +0.4 dBm@-40°C and -1.9 dBm@+125°C, reference +25°C Range @ 4.0 V, +25°C: 7,4 dBm +/- 2.0 dBm Typ. temperature dependency at 4.0 V: +0.6 dBm@-40°C and -3.1 dBm@+125°C, reference +25°C A smaller load impedance reduces the supply-voltage dependency. A higher load impedance reduces the temperature dependency. Wireless Components 5-8 Specification, October 2002